SN54LVC00A, SN74LVC00A

SCAS279U – JANUARY 1993 – REVISED JULY 2024

SNx4LVC00A Quadruple 2-Input Positive-NAND Gates

1 Features 3 Description
• ESD protection exceeds JESD 22 The SN54LVC00A quadruple 2-input positive-NAND
– 2000V Human-Body Model gate is designed for 2.7V to 3.6V VCC operation, and
– 1000V Charged-Device Model the SN74LVC00A quadruple 2-input positive-NAND
• SN74LVC00A operates from 1.65V to 3.6V gate is designed for 1.65V to 3.6V VCC operation.
• SN54LVC00A operates from 2V to 3.6V The SNx4LVC00A devices perform the Boolean
• SNx4LVC00A specified from –40°C to +85°C and function Y = A • B or Y = A + B in positive logic.
–40°C to +125°C
• SN54LVC00A specified from –55°C to +125°C Inputs can be driven from either 3.3V or 5V devices.
• Inputs accept voltages to 5.5V This feature allows the use of these devices as
• Max tpd of 4.3ns at 3.3V translators in a mixed 3.3V/5V system environment.
• Typical VOLP (output ground bounce) Device Information
< 0.8V at VCC = 3.3V, TA = 25°C PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
• Typical VOHV (output VOH undershoot) BQA (WQFN, 14) 3mm × 2.5mm 3mm × 2.5mm
> 2V at VCC = 3.3V, TA = 25°C D (SOIC, 14) 8.65mm × 6mm 8.65 mm × 3.91 mm
• Latch-up performance exceeds 250 mA DB (SSOP, 14) 6.2mm × 7.8mm 6.20 mm × 5.30 mm
per JESD 17 NS (SOP, 14) 10.2mm × 7.8mm 10.30 mm × 5.30 mm
• On products compliant to MIL-PRF-38535, SNx4LVC00A PW (TSSOP, 14) 5mm × 4.4mm 5.00 mm × 4.40 mm
all parameters are tested unless otherwise noted. RGY (VQFN, 14) 3.5mm × 3.5mm 3.50 mm × 3.50 mm
On all other products, production processing does FK (LCCC, 20) 8.9mm x 8.9mm 8.89 mm × 8.89 mm
not necessarily include testing of all parameters. J (CDIP, 14) 19.55mm x 7.9mm 19.55 mm x 6.7mm
W (CFP, 14) 9.21mm x 9mm 9.21mm x 6.28mm
2 Applications
(1) For more information, see Section 11.
• AV Receivers (2) The package size (length × width) is a nominal value and
• Audio Docks: Portable includes pins, where applicable.
• Blu-Ray Players and Home Theater (3) The body size (length × width) is a nominal value and does
not include pins.
• MP3 Players or Recorders
• Personal Digital Assistants (PDAs) A
Y
• Power: Telecom/Server AC/DC Supply: Single B
Controller: Analog and Digital A
Y
• Solid State Drives (SSDs): Client and Enterprise B
• TVs: LCD, Digital, and High-Definition (HDTV) A
Y
• Tablets: Enterprise B
• Video Analytics: Server A
• Wireless Headsets, Keyboards, and Mice B
Y

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC00A, SN74LVC00A
SCAS279U – JANUARY 1993 – REVISED JULY 2024 www.ti.com

Table of Contents
1 Features............................................................................1 7 Detailed Description........................................................9
2 Applications..................................................................... 1 7.1 Overview..................................................................... 9
3 Description.......................................................................1 7.2 Functional Block Diagram........................................... 9
4 Pin Configuration and Functions...................................3 7.3 Feature Description.....................................................9
5 Specifications.................................................................. 4 7.4 Device Functional Modes..........................................10
5.1 Absolute Maximum Ratings........................................ 4 8 Application and Implementation.................................. 11
5.2 ESD Ratings............................................................... 4 8.1 Application Information..............................................11
5.3 Recommended Operating Conditions, 8.2 Typical Application.................................................... 11
SN54LVC00A................................................................ 4 8.3 Layout....................................................................... 12
5.4 Recommended Operating Conditions, 9 Device and Documentation Support............................13
SN74LVC00A................................................................ 5 9.1 Related Links............................................................ 13
5.5 Thermal Information....................................................5 9.2 Receiving Notification of Documentation Updates....13
5.6 Electrical Characteristics, SN54LVC00A.................... 6 9.3 Support Resources................................................... 13
5.7 Electrical Characteristics, SN74LVC00A.................... 6 9.4 Trademarks............................................................... 13
5.8 Switching Characteristics, SN54LVC00A....................6 9.5 Electrostatic Discharge Caution................................13
5.9 Switching Characteristics, SN74LVC00A....................7 9.6 Glossary....................................................................13
5.10 Operating Characteristics......................................... 7 11 Mechanical, Packaging, and Orderable
5.11 Typical Characteristics.............................................. 7 Information.................................................................... 14
6 Parameter Measurement Information............................ 8

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4 Pin Configuration and Functions

VCC
NC
1B
1A

4B
1A 1 14 VCC
1B 2 13 4B
3 2 1 20 19
1Y 3 12 4A 1Y 4 18 4A
2A 4 11 4Y NC 5 17 NC
2B 5 10 3B 2A 6 16 4Y
2Y 6 9 3A NC 7 15 NC
GND 7 8 3Y 2B 8 14 3B
9 10 11 12 13

Figure 4-1. SN54LVC00A J or W Package;

GND
NC
2Y

3Y
3A
SN74LVC00A D, DB, NS, or PW Package 14-Pin
CDIP, CFP NC - No internal connection
SOIC, SSOP, SO, or TSSOP (Top View) Figure 4-2. SN54LVC00A FK Package 20-Pin LCCC
(Top View)

VCC
1A
1 14
1B 2 13 4B
1Y 3 12 4A
2A 4 11 4Y
2B 5 10 3B
2Y 6 9 3A
7 8
GND

3Y

Figure 4-3. SN74LVC00A BQA or RGY Package 14-Pin WQFN or VQFN (Top View)

Table 4-1. Pin Functions

PIN
SN74LVC00A SN54LVC00A TYPE DESCRIPTION
NAME
D, DB, NS, PW BQA, RGY J, W FK
1A 1 1 1 2 I Gate 1 input
1B 2 2 2 3 I Gate 1 input
1Y 3 3 3 4 O Gate 1 output
2A 4 4 4 6 I Gate 2 input
2B 5 5 5 8 I Gate 2 input
2Y 6 6 6 9 O Gate 2 output
GND 7 7 7 10 I Ground Pin
3Y 8 8 8 12 O Gate 3 output
3A 9 9 9 13 I Gate 3 input
3B 10 10 10 14 I Gate 3 input
4Y 11 11 11 16 O Gate 4 output
4A 12 12 12 18 I Gate 4 input
4B 13 13 13 19 I Gate 4 input
VCC 14 14 14 20 — Positive supply
1
5
7
NC — — — — No Connection
11
15
17

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 6.5 V
VI Input voltage(2) –0.5 6.5 V
VO Output voltage (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
VCC Continuous current through GND ±100 mA
Ptot Power dissipation(4) (5) TA = –40°C to +125°C 500 mW
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
(4) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.
(5) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.
5.2 ESD Ratings
VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22- V
±1000
C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions, SN54LVC00A
over operating free-air temperature range (unless otherwise noted)(1)
SN54LVC00A
–55°C to +125°C UNIT
MIN MAX
Operating 2 3.6
VCC Supply voltage V
Data retention only 1.5
VIH High-level input voltage VCC = 2.7 V to 3.6 V 2 V
VIL Low-level input voltage VCC = 2.7 V to 3.6 V 0.8 V
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 2.7 V –12
IOH High-level output current mA
VCC = 3 V –24
VCC = 2.7 V 12
IOL Low-level output current mA
VCC = 3 V 24

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.

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5.4 Recommended Operating Conditions, SN74LVC00A

over operating free-air temperature range (unless otherwise noted)(1)
SN74LVC00A
TA = 25°C –40°C to 85°C –40°C to 125°C UNIT
MIN MAX MIN MAX MIN MAX
Operating 1.65 3.6 1.65 3.6 1.65 3.6
VCC Supply voltage V
Data retention only 1.5 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × VCC 0.65 × VCC 0.65 × VCC
High-level
VIH VCC = 2.3 V to 2.7 V 1.7 1.7 1.7 V
input voltage
VCC = 2.7 V to 3.6 V 2 2 2
VCC = 1.65 V to 1.95 V 0.35 × VCC 0.35 × VCC 0.35 × VCC
Low-level
VIL VCC = 2.3 V to 2.7 V 0.7 0.7 0.7 V
input voltage
VCC = 2.7 V to 3.6 V 0.8 0.8 0.8
VI Input voltage 0 5.5 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC 0 VCC V
VCC = 1.65 V –4 –4 –4

High-level VCC = 2.3 V –8 –8 –8

IOH mA
output current VCC = 2.7 V –12 –12 –12
VCC = 3 V –24 –24 –24
VCC = 1.65 V 4 4 4

Low-level VCC = 2.3 V 8 8 8

IOL mA
output current VCC = 2.7 V 12 12 12
VCC = 3 V 24 24 24

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs, SCBA004.
5.5 Thermal Information
SN74LVC00A
BQA DB PW RGY
THERMAL METRIC(1) D (SOIC) NS (SOP) UNIT
(WQFN) (SSOP) (TSSOP) (VQFN)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 102.3 127.8 140.4 123.8 150.8 92.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.6 Electrical Characteristics, SN54LVC00A

over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC00A
PARAMETER TEST CONDITIONS VCC –55°C to +125°C UNIT
MIN MAX
IOH = –100 µA 2.7 V to 3.6 V VCC – 0.2
2.7 V 2.2
VOH IOH = –12 mA V
3V 2.4
IOH = –24 mA 3V 2.2
IOL = 100 µA 2.7 V to 3.6 V 0.2
VOL IOL = 12 mA 2.7 V 0.4 V
IOL = 24 mA 3V 0.55
II VI = 5.5 V or GND 3.6 V ±5 µA
ICC VI = VCC or GND, IO = 0 3.6 V 10 µA
ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V 500 µA

5.7 Electrical Characteristics, SN74LVC00A

over recommended operating free-air temperature range (unless otherwise noted)
SN74LVC00A
PARAMETER TEST CONDITIONS VCC TA = 25°C –40°C to +85°C –40°C to +125°C UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = –100 µA 1.65 V to 3.6 V VCC – 0.2 VCC – 0.2 VCC – 0.3
IOH = –4 mA 1.65 V 1.29 1.2 1.05
IOH = –8 mA 2.3 V 1.9 1.7 1.55
VOH V
2.7 V 2.2 2.2 2.05
IOH = –12 mA
3V 2.4 2.4 2.25
IOH = –24 mA 3V 2.3 2.2 2
IOL = 100 µA 1.65 V to 3.6 V 0.1 0.2 0.3
IOL = 4 mA 1.65 V 0.24 0.45 0.6
VOL IOL = 8 mA 2.3 V 0.3 0.7 0.85 V
IOL = 12 mA 2.7 V 0.4 0.4 0.6
IOL = 24 mA 3V 0.55 0.55 0.8
II VI = 5.5 V or GND 3.6 V ±1 ±5 ±20 µA
VI = VCC or GND,
ICC 3.6 V 1 10 40 µA
IO = 0
One input at
VCC – 0.6 V,
ΔICC 2.7 V to 3.6 V 500 500 5000 µA
Other inputs at
VCC or GND
Ci VI = VCC or GND 3.3 V 5 pF

5.8 Switching Characteristics, SN54LVC00A

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit and Voltage Waveforms)
SN54LVC00A
FROM TO
PARAMETER VCC –55°C to +125°C UNIT
(INPUT) (OUTPUT)
MIN MAX
2.7 V 5.1
tpd A or B Y ns
3.3 V ± 0.3 V 1 4.3

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5.9 Switching Characteristics, SN74LVC00A

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit and Voltage Waveforms)
SN74LVC00A
FROM TO
PARAMETER VCC TA = 25°C –40°C to +85°C –40°C to +125°C UNIT
(INPUT) (OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
1.8 V ± 0.15 V 1 6 12 1 12.5 1 14
2.5 V ± 0.2 V 1 4.6 5.9 1 6.4 1 7.9
tpd A or B Y ns
2.7 V 1 4.3 4.9 1 5.1 1 6.5
3.3 V ± 0.3 V 1 3.5 4.1 1 4.3 1 5.5
tsk(o) 3.3 V ± 0.3 V 1 1.5 ns

5.10 Operating Characteristics

TA = 25°C
PARAMETER TEST CONDITIONS VCC TYP UNIT
1.8 V 18
Cpd Power dissipation capacitance per gate f = 10 MHz 2.5 V 18 pF
3.3 V 19

5.11 Typical Characteristics

5
TPD (ns)

1
TPD
0
1.5 2.0 2.5 3.0 3.5 4.0
VCC Input (V) C001

Figure 5-1. TPD vs VCC (TA = 25°C)

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6 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
RL tPLZ/tPZL VLOAD
(see Note A)
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VΔ
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
2.7 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
3.3 V ± 0.3 V 2.7 V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V

VI
Timing Input VM
0V
tw

VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + VΔ
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH – VΔ
Output VM
S1 at GND
VOL ≈0 V
(see Note B)
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t PLZ and t PHZ are the same as t dis.
F. t PZL and tPZH are the same as t en .
G. t PLH and t PHL are the same as tpd .
H. All parameters and waveforms are not applicable to all devices.

Figure 6-1. Load Circuit and Voltage Waveforms

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7 Detailed Description
7.1 Overview
The maximum sink and source current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of this
device as translators in a mixed-system environment.
7.2 Functional Block Diagram
A
Y
B
Figure 7-1. Logic Diagram, Each Gate (Positive Logic)

7.3 Feature Description

7.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Section 5.1 must be followed at
all times.
7.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Section 5.6 and Section 5.7. The worst case resistance is calculated with the maximum
input voltage, given in the Section 5.1, and the maximum input leakage current, given in the Section 5.6 and
Section 5.7, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Section 5.3 and Section
5.4 to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be utilized to condition the input signal prior to the standard CMOS input.
7.3.3 Clamp Diodes
The inputs and outputs to this device have negative clamping diodes.

CAUTION
Voltages beyond the values specified in the Section 5.1 table can cause damage to the device.
The input negative-voltage and output voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.

VCC
Device

Input Logic Output

-IIK -IOK

GND

Figure 7-2. Electrical Placement of Clamping Diodes for Each Input and Output

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7.3.4 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Section 5.1.
7.4 Device Functional Modes
Table 7-1 lists the functional modes of SN54LVC00A and SN74LVC00A.
Table 7-1. Function Table
(Each Gate)
INPUTS OUTPUT
A B Y

H H L
L X H
X L H

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

SN74LVC00A is a high-drive CMOS device that can be used for a multitude of buffer-type functions. It can
produce 24 mA of drive current at 3.3 V. Therefore, this device is ideal for driving multiple inputs and for
high-speed applications up to 100 MHz. The inputs and outputs are 5.5-V tolerant allowing the device to allowing
the device to perform mixed-voltage input down translation. For example the A input can be 3.3 V and the B
input can be 5 V, while VCC = 2.5 V and the device will operate properly to output a 2.5 V signal.
8.2 Typical Application
1.65-V to 3.6-V VCC

1A
1Y
1B

4A
4Y
4B

Figure 8-1. Typical NAND Gate Application and Supply Voltage

8.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads;
therefore, routing and load conditions should be considered to prevent ringing.
8.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• Rise time and fall time specs: See (Δt/ΔV) in the Section 5.4 table.
• Specified high and low levels: See (VIH and VIL) in the Section 5.4 table.
• Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommended Output Conditions
• Load currents should not exceed 25 mA per output and 50 mA total for the part.
• Outputs should not be pulled above 5.5 V.

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8.2.3 Application Curve

Figure 8-2. ICC vs Frequency

Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 5.4
table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 µF is recommended; if there are multiple VCC pins, then 0.01 µF or 0.022 µF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µF
and a 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
8.3 Layout
8.3.1 Layout Guidelines
When using multiple bit logic devices inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not
be left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Section 8.3.2 specifies the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs, unless the part is a transceiver.
8.3.2 Layout Example
GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to
0.1 F the device

1A 1 14 VCC
Unused inputs
1B 2 13 4B tied to VCC
1Y 3 12 4A
Unused output
2A 4 11 4Y
left floating
2B 5 10 3B
2Y 6 9 3A
Avoid 90°
corners for GND 7 8 3Y
signal lines

Figure 8-3. Layout Diagram for the SNx4LVC00A

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9 Device and Documentation Support

9.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 9-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
SN54LVC00A Click here Click here Click here Click here Click here
SN74LVC00A Click here Click here Click here Click here Click here

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3.1 Community Resources
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision T (May 2024) to Revision U (July 2024) Page
• Updated RθJA values: D = 86 to 127.8, all values in °C/W................................................................................5
• Added Typical Characteristics ........................................................................................................................... 7

Changes from Revision S (March 2024) to Revision T (May 2024) Page

• Updated RθJA values: DB = 96 to 140.4, NS = 76 to 123.8, PW = 113 to 150.8, RGY = 47 to 92.1; Updated
DB, NS, PW, and RGY packages for RθJC(top), RθJB, ΨJT, ΨJB, and RθJC(bot), all values in °C/W............5

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: SN54LVC00A SN74LVC00A
SN54LVC00A, SN74LVC00A
SCAS279U – JANUARY 1993 – REVISED JULY 2024 www.ti.com

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: SN54LVC00A SN74LVC00A

PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9753301Q2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9753301Q2A
SNJ54LVC
00AFK
5962-9753301QCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9753301QC Samples
& Green A
SNJ54LVC00AJ
5962-9753301QDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9753301QD Samples
& Green A
SNJ54LVC00AW
5962-9753301VDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9753301VD Samples
& Green A
SNV54LVC00AW
SN74LVC00ABQAR ACTIVE WQFN BQA 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples

SN74LVC00AD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples

SN74LVC00ADBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples

SN74LVC00ADBRG4 ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples

SN74LVC00ADE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples

SN74LVC00ADR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples

SN74LVC00ADRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples

SN74LVC00ADT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples

SN74LVC00ANSR ACTIVE SOP NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples

SN74LVC00ANSRG4 ACTIVE SOP NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LVC00A Samples

SN74LVC00APW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples

SN74LVC00APWE4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples

SN74LVC00APWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LVC00APWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 LC00A Samples

SN74LVC00APWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples

SN74LVC00APWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples

SN74LVC00APWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 LC00A Samples

SN74LVC00ARGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 LC00A Samples

SNJ54LVC00AFK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9753301Q2A
SNJ54LVC
00AFK
SNJ54LVC00AJ ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9753301QC Samples
& Green A
SNJ54LVC00AJ
SNJ54LVC00AW ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9753301QD Samples
& Green A
SNJ54LVC00AW

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2024

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54LVC00A, SN54LVC00A-SP, SN74LVC00A :

• Catalog : SN74LVC00A, SN54LVC00A

• Automotive : SN74LVC00A-Q1, SN74LVC00A-Q1
• Enhanced Product : SN74LVC00A-EP, SN74LVC00A-EP
• Military : SN54LVC00A
• Space : SN54LVC00A-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC00ABQAR WQFN BQA 14 3000 180.0 12.4 2.8 3.3 1.1 4.0 12.0 Q1
SN74LVC00ADBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74LVC00ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC00ADT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LVC00ANSR SOP NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LVC00APWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC00APWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC00APWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74LVC00ARGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC00ABQAR WQFN BQA 14 3000 210.0 185.0 35.0
SN74LVC00ADBR SSOP DB 14 2000 356.0 356.0 35.0
SN74LVC00ADR SOIC D 14 2500 353.0 353.0 32.0
SN74LVC00ADT SOIC D 14 250 210.0 185.0 35.0
SN74LVC00ANSR SOP NS 14 2000 356.0 356.0 35.0
SN74LVC00APWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74LVC00APWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
SN74LVC00APWT TSSOP PW 14 250 356.0 356.0 35.0
SN74LVC00ARGYR VQFN RGY 14 3000 356.0 356.0 35.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Dec-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9753301Q2A FK LCCC 20 55 506.98 12.06 2030 NA
5962-9753301QDA W CFP 14 25 506.98 26.16 6220 NA
5962-9753301VDA W CFP 14 25 506.98 26.16 6220 NA
SN74LVC00AD D SOIC 14 50 506.6 8 3940 4.32
SN74LVC00ADE4 D SOIC 14 50 506.6 8 3940 4.32
SN74LVC00APW PW TSSOP 14 90 530 10.2 3600 3.5
SN74LVC00APWE4 PW TSSOP 14 90 530 10.2 3600 3.5
SN74LVC00APWG4 PW TSSOP 14 90 530 10.2 3600 3.5
SNJ54LVC00AFK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54LVC00AW W CFP 14 25 506.98 26.16 6220 NA

Pack Materials-Page 3
PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
GENERIC PACKAGE VIEW
BQA 14 WQFN - 0.8 mm max height
2.5 x 3, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4227145/A

www.ti.com
PACKAGE OUTLINE
BQA0014A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

2.6 A
B 2.4

3.1
PIN 1 INDEX AREA 2.9

0.8 C
0.7

SEATING PLANE
0.05 1.1 0.08 C
0.00 0.9
2X 0.5 (0.2) TYP
7 8
8X 0.5
6
9

SYMM
2X 1.6
2 15 1.4

13
2
14X 0.3
0.2
PIN 1 ID 1 14 0.1 C A B
(OPTIONAL) SYMM 14X 0.5
0.3 0.05 C

4224636/A 11/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
EXAMPLE BOARD LAYOUT
BQA0014A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(1)
2X (0.5)
1 14

2 13
8X (0.5)

2X (0.5) SYMM
(2) (1.5) (2.8)

9
6
14X (0.25)
(Ø0.2) VIA
TYP 14X (0.6)
7 8
SYMM

(R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 20X

0.07 MAX 0.07 MIN METAL UNDER

ALL AROUND ALL AROUND SOLDER MASK

METAL
EXPOSED METAL

SOLDER MASK SOLDER MASK

EXPOSED METAL
OPENING OPENING

NON-SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED

4224636/A 11/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
EXAMPLE STENCIL DESIGN
BQA0014A WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD

(2.3)

(0.95)
2X (0.5)
1 14

2 13
8X (0.5)

SYMM
(2) (1.38) (2.8)

9
6
14X (0.25)

14X (0.6)
7 8
SYMM

(R0.05) TYP

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
88% PRINTED COVERAGE BY AREA
SCALE: 20X

4224636/A 11/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DB0014A SCALE 2.000
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
PLANE
12X 0.65
14
1

2X
6.5
3.9
5.9
NOTE 3

7
8 0.38
14X
0.22
0.15 C A B
5.6
B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4220762/A 05/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
EXAMPLE BOARD LAYOUT
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

1 (R0.05) TYP

14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220762/A 05/2024
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN
DB0014A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

14X (1.85) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220762/A 05/2024
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

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