SN74AHC1G04

SCLS318V – MARCH 1996 – REVISED FEBRUARY 2024

SN74AHC1G04 Single Inverter Gate

1 Features 3 Description
The SN74AHC1G04 contains one inverter gate. The
• Operating range 2 V to 5.5 V
device performs the Boolean function Y = A.
• Max tpd of 6.5 ns at 5 V
• Low power consumption, 10-μA max ICC Package Information
• ±8-mA output drive at 5 V PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)

• Schmitt-trigger action at all inputs makes the circuit DBV (SOT-23, 5) 2.8 mm × 2.8 mm 2.9 mm x 1.6 mm

tolerant for slower input rise and fall time SN74AHC1G04 DCK (SC-70, 5) 2.00 mm × 1.25 mm 2 mm × 1.25 mm

• Latch-up performance exceeds 250 mA per JESD DRL (SOT-553, 5) 1.6 mm x 1.6 mm 1.6 mm × 1.2 mm

17 (1) For all available packages, see the orderable addendum at

the end of the data sheet.
2 Applications (2) The package size (length × width) is a nominal value and
• Cameras includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does
• E-Meters not include pins.
• Ethernet Switches
• Infotainment

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1G04
SCLS318V – MARCH 1996 – REVISED FEBRUARY 2024 www.ti.com

Table of Contents
1 Features............................................................................1 7.3 Feature Description.....................................................8
2 Applications..................................................................... 1 7.4 Device Functional Modes............................................8
3 Description.......................................................................1 8 Application and Implementation.................................... 9
4 Pin Configuration and Functions...................................3 8.1 Application Information............................................... 9
5 Specifications.................................................................. 4 8.2 Typical Application...................................................... 9
5.1 Absolute Maximum Ratings........................................ 4 8.3 Power Supply Recommendations.............................10
5.2 ESD Ratings............................................................... 4 8.4 Layout....................................................................... 10
5.3 Recommended Operating Conditions.........................4 9 Device and Documentation Support............................11
5.4 Thermal Information....................................................5 9.1 Documentation Support (Analog)..............................11
5.5 Electrical Characteristics.............................................5 9.2 Receiving Notification of Documentation Updates.... 11
5.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........6 9.3 Support Resources................................................... 11
5.7 Switching Characteristics, VCC = 5 V ± 0.5 V..............6 9.4 Trademarks............................................................... 11
5.8 Operating Characteristics........................................... 6 9.5 Electrostatic Discharge Caution................................ 11
5.9 Typical Characteristics................................................ 6 9.6 Glossary.................................................................... 11
6 Parameter Measurement Information............................ 7 10 Revision History.......................................................... 11
7 Detailed Description........................................................8 11 Mechanical, Packaging, and Orderable
7.1 Overview..................................................................... 8 Information.................................................................... 12
7.2 Functional Block Diagram........................................... 8

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4 Pin Configuration and Functions

DBV PACKAGE DCK PACKAGE DRL PACKAGE
(TOP VIEW) (TOP VIEW) (TOP VIEW)

NC 1 5 VCC NC 1 5 VCC
NC 1 5 VCC
A 2 A 2

A 2
GND 3 4 Y
GND 3 4 Y

GND 3 4 Y

NC – No internal connection
See mechanical drawings for dimensions.

Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NO. NAME
1 NC — No Connection
2 A I Input A
3 GND — Ground Pin
4 Y O Output Y
5 VCC — Power Pin

(1) Signal Types: I = Input, O = Output, I/O = Input or Output

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
VI Input voltage range(2) –0.5 7 V
VO Output voltage range(2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through each VCC or GND ±50 mA
Tstg Storage temperature range –65 150 °C
TJ Junction temperature 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±3500
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22-C101, V
±1000
all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 3 V 2.1 V
VCC = 5.5 V 3.85
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 3 V 0.9 V
VCC = 5.5 V 1.65
VIH Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 2 V –50 µA
IOH High-level output current VCC = 3.3 V ± 0.3 V –4
mA
VCC = 5 V ± 0.5 V –8
VCC = 2 V 50 µA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4
mA
VCC = 5 V ± 0.5 V 8
VCC = 3.3 V ± 0.3 V 100
Δt/Δv Input transition rise or fall rate ns/V
VCC = 5 V ± 0.5 V 20

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over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).

5.4 Thermal Information

SN74AHC1G04
THERMAL METRIC(1) DBV DCK DRL UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance 278 289.2 328.7
RθJC(top) Junction-to-case (top) thermal resistance 180.5 205.8 105.1
RθJB Junction-to-board thermal resistance 184.4 176.2 150.3
°C/W
ψJT Junction-to-top characterization parameter 115.4 117.6 6.9
ψJB Junction-to-board characterization parameter 183.4 175.1 148.4
RθJC(bot) Junction-to-case (bot) thermal resistance N/A N/A N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
TEST T A = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER VCC UNIT
CONDITIONS MIN TYP MAX MIN MAX MIN MAX
2V 1.9 2 1.9 1.9
IOH = –50 µA 3V 2.9 3 2.9 2.9
VOH High level output voltage 4.5 V 4.4 4.5 4.4 4.4 V
IOH = –4 mA 3V 2.58 2.48 2.48
IOH = –8 mA 4.5 V 3.94 3.8 3.8
2V 0.1 0.1 0.1
IOH = 50 µA 3V 0.1 0.1 0.1
VOL Low level output voltage 4.5 V 0.1 0.1 0.1 V
IOL = 4 mA 3V 0.36 0.44 0.44
IOL = 8 mA 4.5 V 0.36 0.44 0.44
VI = 5.5 V or 0 V to
II Input leakage current ±0.1 ±1 ±1 µA
GND 5.5 V
VI = VCC or
ICC Supply current 5.5 V 1 10 10 µA
GND, IO = 0
Ci Input Capacitance V VI = VCC or GND 5V 2 10 10 10 pF

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5.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit And Voltage Waveforms)
FROM TO OUTPUT TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 5 7.1 1 8.5 1 9.5
A Y CL = 15 pF ns
tPHL 5 7.1 1 8.5 1 9.5
tPLH 7.5 10.6 1 12 1 13
A Y CL = 50 pF ns
tPHL 7.5 10.6 1 12 1 13

5.7 Switching Characteristics, VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range (unless otherwise noted) (see Load Circuit And Voltage Waveforms)
FROM TO OUTPUT TA = 25°C –40°C to 85°C –40°C to 125°C
PARAMETER UNIT
(INPUT) (OUTPUT) CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 3.8 5.5 1 6.5 1 7
A Y CL = 15 pF ns
tPHL 3.8 5.5 1 6.5 1 7
tPLH 5.3 7.5 1 6.5 1 7
A Y CL = 50 pF ns
tPHL 5.3 7.5 1 6.5 1 7

5.8 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 12 pF

5.9 Typical Characteristics

4 5

3.5
4
3

2.5 3
TPD (ns)

TPD (ns)

1.5 2

1
1
0.5
TPD in ns TPD in ns
0 0
-100 -50 0 50 100 150 0 1 2 3 4 5 6
Temperature (qC) D001
VCC D002

Figure 5-1. TPD vs Temperature at 5 V Figure 5-2. TPD vs VCC at 25°C

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6 Parameter Measurement Information

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

VCC
Timing Input 50% VCC
tw 0V
th
VCC tsu
VCC
Input 50% VCC 50% VCC
Data Input 50% VCC 50% VCC
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input 50% VCC 50% VCC 50% VCC 50% VCC
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈VCC
In-Phase 50% VCC 50% VCC 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2
50% VCC 50% VCC 50% VCC VOH − 0.3 V
Output S1 at GND
VOL (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 6-1. Load Circuit And Voltage Waveforms

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7 Detailed Description
7.1 Overview
The SN74AHC1G04 device contains one inverter gate. The device performs the Boolean function Y = A.
This single gate inverter has Schmitt-Trigger action on its input, allowing for slower rise and fall times and some
noise rejection. This is not a true Schmitt-Trigger, so there is a limit on rise and fall times.
7.2 Functional Block Diagram

Figure 7-1. Logic Diagram (Positive Logic)

7.3 Feature Description

• Wide operating voltage range
– Operates from 2 V to 5.5 V
• Allows down-voltage translation
– Inputs accept voltages to 5.5 V
• Lower drive
– This will produce slower edges and help prevent ringing on outputs
7.4 Device Functional Modes
Table 7-1. Function Table
INPUT (1) OUTPUT(2)
A Y
H L
L H

(1) H = High Voltage Level, L =

Low Voltage Level, X = Don’t
Care
(2) H = Driving High, L = Driving
Low, Z = High Impedance
State

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

SN74AHC1G04 is a low-drive CMOS device that can be used for a multitude of inverting buffer type functions.
It can produce 8 mA of drive current at 5 V, making it Ideal for driving multiple outputs and good for low-noise
applications. The inputs are 5.5-V tolerant, allowing it to translate down to VCC.
8.2 Typical Application
5-V accessory 3.3-V or 5-V regulated

0.1 µF

Figure 8-1. Typical Application Schematic

8.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create
fast edges into light loads, so routing and load conditions should be considered to prevent ringing.
8.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• For rise time and fall time specifications, see Δt/ΔV in the Section 5.3 table.
• For specified High and low levels, see VIH and VIL in the Section 5.3 table.
• Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
• Load currents should not exceed 25 mA per output and 50 mA total for the part.
• Outputs should not be pulled above VCC.

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8.2.3 Application Curves

Figure 8-2. Typical Application Curve

8.3 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 5.3
table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
8.4 Layout
8.4.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 8-3 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part
is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
8.4.2 Layout Example
Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 8-3. Layout Diagram

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9 Device and Documentation Support

9.1 Documentation Support (Analog)
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application note
• Texas Instruments, Designing With Logic application note
• Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices
application note
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application note
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
Changes from Revision U (October 2023) to Revision V (February 2024) Page
• Updated thermal values for DBV package from RθJA = 231.3 to 278, RθJC(top) = 119.9 to 180.5, RθJB =
60.6 to 184.4, ΨJT = 17.8 to 115.4, ΨJB = 60.1 to 183.4, RθJC(bot) = N/A, all values in °C/W ...................... 5

Changes from Revision T (January 2016) to Revision U (October 2023) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74AHC1G04DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (A043, A04G, A04J, Samples
A04L, A04S)
SN74AHC1G04DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A04G Samples

SN74AHC1G04DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A04G Samples

SN74AHC1G04DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A04G Samples

SN74AHC1G04DCK3 ACTIVE SC70 DCK 5 3000 RoHS & SNBI Level-1-260C-UNLIM -40 to 85 ACY Samples
Non-Green
SN74AHC1G04DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (AC3, ACG, ACJ, AC Samples
L, ACS)
SN74AHC1G04DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AC3 Samples

SN74AHC1G04DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AC3 Samples

SN74AHC1G04DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AC3 Samples

SN74AHC1G04DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (ACB, ACS) Samples

SN74AHC1G04DRLRG4 ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 (ACB, ACS) Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AHC1G04 :

• Automotive : SN74AHC1G04-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

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PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHC1G04DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G04DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74AHC1G04DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G04DBVTG4 SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G04DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AHC1G04DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
SN74AHC1G04DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G04DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G04DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 7-Feb-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC1G04DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74AHC1G04DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G04DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G04DBVTG4 SOT-23 DBV 5 250 180.0 180.0 18.0
SN74AHC1G04DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G04DCKR SC70 DCK 5 3000 202.0 201.0 28.0
SN74AHC1G04DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G04DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74AHC1G04DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0

Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90
0 -10

0.25
GAGE PLANE 0.22
TYP
0.08 0 -10

8
TYP 0.6
0 TYP SEATING PLANE
0.3

0 -10

0 -10

ALTERNATIVE PACKAGE SINGULATION VIEW

4214839/H 09/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/H 09/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/H 09/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.15
0.1
0.1 C A B (0.9) TYP
0.0
NOTE 5

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE

4214834/D 07/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.

www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/D 07/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/D 07/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DRL0005A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
5

2X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3 0.3 0.05

B 5X TYP
1.1 0.1 0.00

0.6 MAX
C

SEATING PLANE
0.18
5X 0.05 C
0.08
SYMM

SYMM

0.27
5X
0.15
0.1 C A B
0.4
5X 0.05
0.2
4220753/B 12/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1

www.ti.com
EXAMPLE BOARD LAYOUT
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67) SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4220753/B 12/2020

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67)
SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4220753/B 12/2020

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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