SN74AHC1G00

SCLS313Q – MARCH 1996 – REVISED JANUARY 2024

SN74AHC1G00 Single 2-Input Positive-NAND Gate

1 Features 3 Description
• Operating range: 2 V to 5.5 V The SN74AHC1G00 performs the Boolean function
• Maximum tpd of 6.5 ns at 5 V Y = A • B or Y = A + B in positive logic.
• Low power consumption: maximum ICC of 10 μA
Package Information
• ±8-mA output drive at 5 V PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(2)
• Schmitt trigger action at all inputs makes the circuit DBV (SOT-23, 5) 2.9 mm x 2.8 mm 2.9 mm x 1.6 mm
tolerant for slower input rise and fall time SN74AHC1G00 DCK (SC-70, 5) 2 mm x 2.1 mm 2 mm × 1.25 mm
• Latch-up performance exceeds 250 mA per JESD DRL (SOT, 5) 1.6 mm × 1.6 mm 1.6 mm × 1.2 mm
17
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.
(2) The package size (length × width) is a nominal value and
• Enable or disable a digital signal includes pins, where applicable.
• Controlling an indicator LED
• Translation between communication modules and
system controllers
1
A 4
2 Y
B

Logic Diagram (Positive Logic)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1G00
SCLS313Q – MARCH 1996 – REVISED JANUARY 2024 www.ti.com

Table of Contents
1 Features............................................................................1 7.2 Functional Block Diagram........................................... 9
2 Applications..................................................................... 1 7.3 Feature Description.....................................................9
3 Description.......................................................................1 7.4 Device Functional Modes............................................9
4 Pin Configuration and Functions...................................3 8 Application and Implementation.................................. 10
5 Specifications.................................................................. 4 8.1 Typical Application.................................................... 10
5.1 Absolute Maximum Ratings........................................ 4 8.2 Power Supply Recommendations............................. 11
5.2 ESD Ratings............................................................... 4 8.3 Layout....................................................................... 12
5.3 Recommended Operating Conditions.........................4 9 Device and Documentation Support............................13
5.4 Thermal Information....................................................5 9.1 Documentation Support............................................ 13
5.5 Electrical Characteristics.............................................5 9.2 Receiving Notification of Documentation Updates....13
5.6 Switching Characteristics: VCC = 3.3 V ± 0.3 V...........6 9.3 Support Resources................................................... 13
5.7 Switching Characteristics: VCC = 5 V ± 0.5 V..............7 9.4 Trademarks............................................................... 13
5.8 Operating Characteristics........................................... 7 9.5 Electrostatic Discharge Caution................................13
5.9 Typical Characteristics................................................ 7 9.6 Glossary....................................................................13
6 Parameter Measurement information............................ 8 10 Revision History.......................................................... 13
7 Detailed Description........................................................9 11 Mechanical, Packaging, and Orderable
7.1 Overview..................................................................... 9 Information.................................................................... 14

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4 Pin Configuration and Functions

A 1 5 VCC
A 1 5 VCC
B 2

B 2
GND 3 4 Y

GND 3 4 Y

Figure 4-2. DCK Package 5-Pin SC70 Top View

Figure 4-1. DBV Package 5-Pin SOT-23 Top View

A 1 5 VCC

B 2

GND 3 4 Y

Figure 4-3. DRL Package 5-Pin SOT Top View

Table 4-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NO. NAME
1 A I A input
2 B I B input
3 GND — Ground
4 Y O Output
5 VCC — Power

(1) Signal Types: I = Input, O = Output, I/O = Input or Output

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VI (2) Input voltage –0.5 7 V
VO (2) Output voltage –0.5 VCC + 0.5 V
IIK Input clamp current (VI < 0) –20 mA
IOK Output clamp current (VO < 0 or VO > VCC) ±20 mA
IO Continuous output current (VO = 0 to VCC) ±25 mA
Continuous current through VCC or GND ±50 mA
TJ Maximum junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1000
C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage 2 5.5 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 3 V 2.1 V
VCC = 5.5 V 3.85
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 3 V 0.9 V
VCC = 5.5 V 1.65
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 2 V –50 µA
IOH High-level output current VCC = 3.3 V ± 0.3 V –4
mA
VCC = 5 V ± 0.5 V –8
VCC = 2 V 50 µA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4
mA
VCC = 5 V ± 0.5 V 8
VCC = 3.3 V ± 0.3 V 100
Δt/Δv Input transition rise or fall rate ns/V
VCC = 5 V ± 0.5 V 20

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5.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
TA Operating free-air temperature –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.

5.4 Thermal Information

SN74AHC1G00
THERMAL METRIC(1) DBV (SOT-23) DCK (SC70) DRL (SOT) UNIT
5 PINS 5 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 278 289.2 256 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 180.5 205.8 130 °C/W
RθJB Junction-to-board thermal resistance 184.4 176.2 152 °C/W
ψJT Junction-to-top characterization parameter 115.4 117.6 9.9 °C/W
ψJB Junction-to-board characterization parameter 183.4 175.1 152 °C/W
RθJC(bot) Junction-to-case (bot) thermal resistance N/A N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS VCC MIN TYP MAX UNIT
TA = 25°C 1.9 2
TA = –40°C to +85°C 2V 1.9
TA = –40°C to +125°C 1.9
TA = 25°C 2.9 3
IOH = –50 µA TA = –40°C to +85°C 3V 2.9
TA = –40°C to +125°C 2.9
TA = 25°C 4.4 4.5
VOH High level output voltage TA = –40°C to +85°C 4.5 V 4.4 V
TA = –40°C to +125°C 4.4
TA = 25°C 2.58
IOH = –4 mA TA = –40°C to +85°C 3V 2.48
TA = –40°C to +125°C 2.48
TA = 25°C 3.94
IOH = –8 mA TA = –40°C to +85°C 4.5 V 3.8
TA = –40°C to +125°C 3.8

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5.5 Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS VCC MIN TYP MAX UNIT
TA = 25°C 0.1
TA = –40°C to +85°C 2V 0.1
TA = –40°C to +125°C 0.1
TA = 25°C 0.1
IOL = 50 µA TA = –40°C to +85°C 3V 0.1
TA = –40°C to +125°C 0.1
TA = 25°C 0.1
VOL Low level output voltage TA = –40°C to +85°C 4.5 V 0.1 V
TA = –40°C to +125°C 0.1
TA = 25°C 0.36
IOL = 4 mA TA = –40°C to +85°C 3V 0.44
TA = –40°C to +125°C 0.44
TA = 25°C 0.36
IOL = 8 mA TA = –40°C to +85°C 4.5 V 0.44
TA = –40°C to +125°C 0.44
TA = 25°C ±0.1
0 V to
II Input leakage current VI = 5.5 V or GND TA = –40°C to +85°C ±1 µA
5.5 V
TA = –40°C to +125°C ±1
TA = 25°C 1
ICC Supply current VI = VCC or GND, IO = 0 TA = –40°C to +85°C 5.5 V 10 µA
TA = –40°C to +125°C 10
TA = 25°C 2 10
Ci Input Capacitance VI = VCC or GND TA = –40°C to +85°C 5V 10 pF
TA = –40°C to +125°C 10

(1) Recommended TA = –40°C to +125°C

5.6 Switching Characteristics: VCC = 3.3 V ± 0.3 V

over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
FROM TO OUTPUT
PARAMETER TA (1) MIN TYP MAX UNIT
(INPUT) (OUTPUT) CAPACITANCE
25°C 5.5 7.9
tPLH –40°C to +85°C 1 9.5
–40°C to +125°C 1 10.5
A or B Y CL = 15 pF ns
25°C 5.5 7.9
tPHL –40°C to +85°C 1 9.5
–40°C to +125°C 1 10.5
25°C 8 11.4
tPLH –40°C to +85°C 1 13
–40°C to +125°C 1 14
A or B Y CL = 50 pF ns
25°C 8 11.4
tPHL –40°C to +85°C 1 13
–40°C to +125°C 1 14

(1) Recommended TA = –40°C to +125°C

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5.7 Switching Characteristics: VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Load Circuit and
Voltage Waveforms)
FROM TO OUTPUT
PARAMETER TA (1) MIN TYP MAX UNIT
(INPUT) (OUTPUT) CAPACITANCE
25°C 3.7 5.5
tPLH –40°C to +85°C 1 6.5
–40°C to +125°C 1 7
A or B Y CL = 15 pF ns
25°C 3.7 5.5
tPHL –40°C to +85°C 1 6.5
–40°C to +125°C 1 7
25°C 5.2 7.5
tPLH –40°C to +85°C 1 6.5
–40°C to +125°C 1 9
A or B Y CL = 50 pF ns
25°C 5.2 7.5
tPHL –40°C to +85°C 1 6.5
–40°C to +125°C 1 9

(1) Recommended TA = –40°C to +125°C

5.8 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 9.5 pF

5.9 Typical Characteristics

14

12 Vcc=3.3 +/-0.3 V
A/B to Y
CL = 50 pF
tPLH/HL(max) (ns)

10

8 Vcc=5 +/-0.5 V
A/B to Y
CL = 50 pF
6

0 25 50 85 125
Temperature (°C)
CL = 50 pF
Figure 5-1. Propagation Delay vs Temperature

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6 Parameter Measurement information

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

VCC
Timing Input 50% VCC
tw 0V
th
VCC tsu
VCC
Input 50% VCC 50% VCC
Data Input 50% VCC 50% VCC
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VCC VCC
Output
Input 50% VCC 50% VCC 50% VCC 50% VCC
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈VCC
In-Phase 50% VCC 50% VCC 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2
50% VCC 50% VCC 50% VCC VOH − 0.3 V
Output S1 at GND
VOL (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 6-1. Load Circuit and Voltage Waveforms

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7 Detailed Description
7.1 Overview
The SN74AHC1G00 device performs the NAND Boolean function Y = A × B or Y = A + B in positive logic. The
device has a wide operating range of VCC from 2 V to 5 V.
7.2 Functional Block Diagram
1
A 4
2 Y
B

Figure 7-1. Logic Diagram (Positive Logic)

7.3 Feature Description

The SN74AHC1G00 device has wide operating voltage range for logic system from 2 V to 5 V. The low
propagation delay allows fast switching and higher speeds of operation. In addition, the low power consumption
of 10-uA (maximum) makes this device a good choice for portable and battery power-sensitive applications. The
Schmitt trigger action on all inputs have noise rejection capabilities.
7.4 Device Functional Modes
Table 7-1. Function Table
INPUTS(1) OUTPUT(2)
A B Y
H H L
L X H
X L H

(1) H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

(2) H = Driving High, L = Driving Low, Z = High Impedance State

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Typical Application

S Q

Q
R

Figure 8-1. Typical Application

8.1.1 Design Requirements

This SN74AHC1G00 device uses CMOS technology and has balanced output drive. Take care to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive also creates fast
edges into light loads. Routing and load conditions must be considered to prevent ringing.
8.1.2 Detailed Design Procedure
• Recommended input conditions:
– Specified high and low levels. See VIH and VIL in Section 5.3.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
• Recommended output conditions:
– Load currents must not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.

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8.1.3 Application Curve

12

10 Vcc=3.3 +/-0.3 V
A/B to Y
CL = 15 pF
tPLH/HL(max) (ns)

6 Vcc=5 +/-0.5 V
A/B to Y
CL = 15 pF
4

0 25 50 85 125
Temperature (°C)
CL = 15 pF

Figure 8-2. Propagation Delay vs Temperature

8.2 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Section 5.3.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-μF capacitor; if there are multiple VCC terminals, then TI recommends a 0.01-μF
or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different
frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must
be installed as close as possible to the power terminal for best results.

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8.3 Layout
8.3.1 Layout Guidelines
When using multiple bit logic devices inputs must not ever float.
In many cases, functions or parts of functions of digital logic devices are unused. For example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins
must not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. The following are the rules must be observed under all circumstances.
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
The logic level that should be applied to any particular unused input depends on the function of the device.
Generally they will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is
generally acceptable, unless the part is a transceiver. If the transceiver has an output enable pin, it disables the
outputs section of the part when asserted. This does not disable the input section of the input and output, so they
also cannot float when disabled.
8.3.2 Layout Example

VCC Input
Unused Input Output Unused Input Output
Input

Figure 8-3. Layout Recommendation

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9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Introduction to Logic application report
• Texas Instruments, Implications of Slow or Floating CMOS Inputsapplication note
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision P (October 2023) to Revision Q (January 2024) Page

• Updated thermal values for DBV package from RθJA = 240 to 278, RθJC(top) = 174.5 to 180.5, RθJB = 73.7
to 184.4, ΨJT = 54.9 to 115.4, ΨJB = 60.1 to 183.4, RθJC(bot) = N/A, all values in °C/W .............................. 5

Changes from Revision O (April 2016) to Revision P (October 2023) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document................. 1
• Updated thermal values for DCK package from RθJA = 276.53 to 289.2, RθJC(top) = 118.5 to 205.8, RθJB =
62.8 to 176.2, ΨJT = 6.7 to 117.6, ΨJB = 62.1 to 175.1, RθJC(bot) = N/A, all values in °C/W ........................ 5

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11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74AHC1G00DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (A003, A00G, A00J, Samples
A00L, A00S)
SN74AHC1G00DBVRG4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 A00G Samples

SN74AHC1G00DCK3 ACTIVE SC70 DCK 5 3000 RoHS & SNBI Level-1-260C-UNLIM -40 to 125 AAY Samples
Non-Green
SN74AHC1G00DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (1QP, AA3, AAG, AA Samples
J, AAL, AAS)
SN74AHC1G00DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AA3 Samples

SN74AHC1G00DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AA3 Samples

SN74AHC1G00DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AA3 Samples

SN74AHC1G00DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 (AAB, AAS) Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

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(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74AHC1G00 :

• Automotive : SN74AHC1G00-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jan-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHC1G00DBVR SOT-23 DBV 5 3000 180.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G00DBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3
SN74AHC1G00DBVRG4 SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
SN74AHC1G00DCKR SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G00DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3
SN74AHC1G00DCKRG4 SC70 DCK 5 3000 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G00DCKTG4 SC70 DCK 5 250 178.0 9.2 2.4 2.4 1.22 4.0 8.0 Q3
SN74AHC1G00DRLR SOT-5X3 DRL 5 4000 180.0 8.4 1.98 1.78 0.69 4.0 8.0 Q3

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jan-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC1G00DBVR SOT-23 DBV 5 3000 202.0 201.0 28.0
SN74AHC1G00DBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G00DBVRG4 SOT-23 DBV 5 3000 180.0 180.0 18.0
SN74AHC1G00DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G00DCKR SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G00DCKRG4 SC70 DCK 5 3000 180.0 180.0 18.0
SN74AHC1G00DCKTG4 SC70 DCK 5 250 180.0 180.0 18.0
SN74AHC1G00DRLR SOT-5X3 DRL 5 4000 202.0 201.0 28.0

Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

ALTERNATIVE PACKAGE SINGULATION VIEW

4214839/J 02/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/J 02/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/J 02/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DRL0005A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

1.7
1.5
PIN 1 A
ID AREA

1
5

2X 0.5
1.7
1.5
2X 1 NOTE 3

4
3

1.3
B 0.3 0.05
1.1 5X TYP
0.1 0.00

0.6 MAX C

SEATING PLANE
0.18
5X 0.05 C
0.08
SYMM

SYMM

0.27 ALTERNATIVE PACKAGE

5X
0.15 SINGULATION VIEW
0.4 0.1 C A B
5X
0.2 0.05 C
4220753/C 04/2024
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1

www.ti.com
EXAMPLE BOARD LAYOUT
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67) SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

LAND PATTERN EXAMPLE

SCALE:30X

0.05 MAX 0.05 MIN

AROUND AROUND

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDERMASK DETAILS

4220753/C 04/2024

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE

5X (0.67)
SYMM
1
5
5X (0.3)

SYMM
(1)

2X (0.5)

3 4

(R0.05) TYP
(1.48)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:30X

4220753/C 04/2024

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA

1 5

2X 0.65 NOTE 4

2.15
1.3 (0.15) 1.3
2 1.85

(0.1)

4
0.33 3
5X
0.15
0.1 C A B 0.1
(0.9) TYP
NOTE 5 0.0

0.15
GAGE PLANE 0.22
TYP
0.08

8 0.46
TYP TYP
0 0.26
SEATING PLANE
ALTERNATIVE PACKAGE
SINGULATION VIEW

4214834/E 06/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.
6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.25mm per side

www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)

1
5
5X (0.4)

SYMM
(1.3)
2
2X (0.65)

3 4

(R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:18X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214834/E 06/2024

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR

PKG
5X (0.95)
1
5
5X (0.4)

SYMM
(1.3)
2
2X(0.65)

3 4

(R0.05) TYP
(2.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:18X

4214834/E 06/2024

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
10. Board assembly site may have different recommendations for stencil design.

www.ti.com
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