Digital Test

1) The logic function implemented by the circuit below is

P Q
a) F =AND ( P, Q )
b) F = OR (P, Q)
c) F =XNOR ( P, Q)
d) F =XOR ( P, Q)

2) For the output F to be 1 in the logic circuit shown, the input

combination should be

a) A =1,B =1, C=0

b) A =1,B =0, C=0
c) A =0,B =1, C=0
d) A =0,B =0, C=1

3) The Boolean function realized by the logic circuit shown is

a) F=∑m (0,1, 3, 5, 9,10,14)

b) F =∑m ( 2 ,3 ,5 ,7 ,8 ,12 ,13)

c) F =∑m( 1, 2, 4, 5, 11, 14, 15)

d) F=∑m(2 ,3 ,5 ,7 ,8 ,9 ,12)

4) The circuit shown below has clock frequency 12 KHz. What is the
frequency of the signal at Q2?

a) 1.2KHz b) 2.5KHz c) 4KHz d) 8KHz

5) The output of the combinational circuit given below is

a) A+B+C b) A(B+C) c) B(C+A) d) C(A+B)

6) The Boolean function f implemented in the figure using two input

multiplexes is

0
a) AB’C+ ABC’

b) ABC +A(BC )’

c) A’BC+(ABC)’

d) (AB)’C+A’BC’

7) A 4 bit SISO register is used with feedback as shown below. The

shifting sequence is Qa -> Qb-> Qc-> Qd. If the initial output is
0000 after how many cycles it repeats?

a) 4 b) 6 c) 15 d) 16

8) If the input to the digital circuit consisting of a cascade of 20

XOR - gates is X , then the output Y is equal to

a) 0 b) 1 c) x’ d) x

9) What is the addition of 22 base (10) and 67 base (8). Output should be
in terms of decimal number.

a) 76 b) 55 c) 87 d) 77

10) Find the number of 8 x 1 MUX required to implement 256 x 1.

a) 34
b) 35
c) 36
d) 37
11) In a J–K flip-flop given below,we have J=1 and K = 1. Assuming the
flip flop was initially cleared and then clocked for 6 pulses, the sequence
at the Q output will be

a) 010000 b) 011001 c) 010010 d) 010101

12) In 2’s complement representation the number 11100101 represents

the decimal number?

a) -30
b) -27
c) +27
d) -31

13) The number of full and half adders are required to add 16-bit number
is _________

a) 8 half adders, 8 full adders

b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders

14) What Boolean expression is implemented by the circuit shown below?

a) W s1’ s2’
b) W’ s1 s2
c) W s1 + W s2 + s1 s2
d) W xor s1 xor s2

15) For the circuit shown below. Choose the right output waveform y.

a) W1 b) W2 c) W3 d) W4

16) The MSB priority, 8:3 priority encoder has inputs 0101_1001. What is
the encoded output?
a) 000
b) 110
c) 011
d) 100
17)What Boolean expression is implemented by the circuit shown below?

(a) A’B’C+A’BD+AB’C’+ABC’D’
(b) AB’C+A’BD+ABC’+ABC’D’
(c)A’B’C+A’BD+AB’C’+ (ABCD)’
(d) ABC+A’BD+AB'C'+A’B’C’D

18) The initial values of flip flops shown below are set to 0. What is the
sequence generated by Q1 on the application of clock pulses?

a) 01010..
b) 01110
c) 01100
d) 00110

19) What is the output (Q0 Q1 Q2) of the following circuit after 14 cycles?

a) 000
b) 001
c) 110
d) 100
20) The circuit shown below is

a. Mod-3
b. Mod-4
c. Mod- 6
d. Mod- 12

21) The correction to be applied in BCD adder to the generated sum is

(a) 00101
(b) 00110
(c) 01101
(d) 01010

22) The logic gate realized by the circuit shown below is

(a) xnor gate

(b) xor gate
(c) nand gate
(d) nor gate

23) A Glitch is __________

a) Unwanted short pulse produced at the input

b) Unwanted short pulse produced at the output

c) Wanted short pulse produced at the input

d) Wanted short pulse produced at the output

24) What does the below circuit represent?

(a)Parity generator
(b) 2 bit ripple adder
(c) 2-bit multiplier
(d) 2 bit comparator

25) Implementing the expression AB+CDE using NAND logic, we get:

26) Grey code of 1010 is ----

a) 0110
b) 1111
c) 1001
d) 1100

27) The Boolean function A+BC is a reduced form of

a) AB +BC
b) (A+ B)(A+C)
c) A’B+ AB’C
d) (A+ C) B
28) Determine the output frequency for a frequency division circuit
that contains 12 flip-flops with an input clock frequency of 20.48
MHz

a) 21.6 Khz
b) 5 Khz
c) 10.24 Khz
d) 15 Khz

29) For the circuit shown in the following, There are inputs to the 4:1
multiplexers, R(MSB) and S are control bits. The output x can be
represented by

a) PQ +PQ’S +(QRS)’

e) PQ’+ PQR’+( PQS)’

f) P(QR)’+ P’QR+ PARS+( QRS) ‘

g) PQR’+PQRS’+P(QR)’S+( QRS)’

30) The state transition diagram for the logic circuit shown is

a)
b)

c)

d)
31) The octal equivalent of the decimal number (417)10 is

a) (619)8
b) (641)8
c) (598)8
d) (621)8

32) The functionality implemented by the circuit below is

a) 2-to-1 multiplexer
b) 4-to-1 multiplexer
c) 7-to-1 multiplexer
d) 6-to-1 multiplexer

33) Calculate (326.15)10 - (456.71)8

a) (27.205)8
b) (27.205)10
c) (23.26)10
d) Both A & C
34) As the number of flip flops are increased, the total propagation delay
of

a) Ripple counter remains the same but that of synchronous counter

increases
b) Ripple counter increases but that of synchronous counter remains the
same
c) Both ripple and synchronous counters increase
d) Both ripple and synchronous counters increase

35) For the truth table of the given, Y =

a) A + B+ C
b) A
c) Ā +BC
d) B’

36) Look-ahead carry circuits found in most 4-bit full-adder circuits which
___________
a) Determine sign and magnitude

b) Reduce propagation delay

c) Add a 1 to complemented inputs

d) Increase ripple delay

37) How many D flipflop is required to make divide by 5 counter

circuit.
a) 2 b)3 c) 4 d) 5
38) The binary numbers A = 1100 and B = 1001 are applied to the
inputs of a comparator. What are the output levels?
a) A > B = 1, A < B = 0, A < B = 1

b) A > B = 0, A < B = 1, A = B = 0

c) A > B = 1, A < B = 0, A = B = 0

d) A > B = 0, A < B = 1, A = B = 1

39)_________ are the methods used to represent negative integer

numbers
a) 1’s complement
b) Sign magnitude
c) 2’s complement
d) All of the above

40) FIFO is used for ________

a) Non synchronization Purpose

b) Synchronization Purpose

c) Both Non synchronization Purpose and Synchronization Purpose

d) Non simultaneous

41) What type of sequence will the below circuit produce? Consider the
initial value as 0, and Q3 is msb, Q0 is lsb.

a) 0,1,3,7,15,14,12,8
b) 0,1,3,7,15,
c) 0,1,3,7,15,14
d) 0,1,3,7
42) In the sequential circuit shown below,if the initial value of
the output Q1Q0 is 00,what are the next four values of Q1Q0?

a) 11,10,01,00
b) 10,11,01,00
c) 10,00,01,11
d) 11,10,00,01

43) The sequence detected by the state diagram shown below is

0/0

a) 1110 sequence detector without overlap

b) 1110 sequence detector with overlap

c) 1101 sequence detector without overlap

d) 1101 sequence detector with overlap

44) Four J-K flip-flops are cascaded with their J-K inputs tied
HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz,
the output frequency (fout) is
a) 1KHZ
b) 2KHZ
c) 4KHZ
d) 8KHZ

45) Assuming that all flip-flops are in reset condition initially,

the count sequence observed at QA in the circuit shown is?

a) 00010111….
b) 0001011….
c) 0101111….
d) 0110100…