Google Women in Silicon Hardware (WISH) program

Module 1 – Digital Systems and Microcontrollers – 2024

Key Answers

1. Which of the following is equivalent to the Boolean expression A+ AB + ABC + ABCD +

ABCDE + ABCDEF?
a. ABCDEF b. AB c. A+AD d. A + B + C + D + E + F

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
2. What is the most simplified form of this Boolean equation: ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 ̅𝐵𝐶𝐷 ̅ + 𝐵𝐶𝐷)(𝐴 ∙ 𝐵̅ )
a. 𝐴 + 𝐵̅ ̅+𝑩
b. 𝑨 c. 𝐵 • 𝐶 d.𝐵 • 𝐶 • 𝐷

3. Which of the following equations is an example of the Associative Property?

a. A•(B+C)=AB+AC b. A•1=A c. A+(B+C)=(A+B)+C d. A+B=B+A

4. In binary Boolean algebra, multiplicative inverse of 𝑎 is:

a. 0 b. 1 c. a’ d. Not defined

5. In Boolean algebra 0 is a:
a. commutative property b. additive identity
c. associative identity d. multiplicative inverse

6. Complement of a function expressed as a sum of minterms will be:

a. sum of minterms b. product of minterms
c. sum of maxterms d. product of maxterms

7. Which of these will always be a perfect square in any base b (> 2)?
a. (16)b b. (64)b c. (121)b d. (1000)b

8. What is the hexadecimal equivalent of the unsigned binary number: (100111011000111010001)2

a. (13B1D1)16 b. (9D8EA1)16 c. (9E7DA1)16 d. (9D8FA1)16

9. What is the hexadecimal equivalent of the octal number: (763276327632)8

a. (B23B23B23)16 b. (68987BAE1)16 c. (F9AF9AF9A)16 d. (ED315134B)16

10. Solve: (2D3B)16 – (1FED)16:

a. (13E)16 b. (D4E)16 c. (1372)16 d. (144E)16

11. What is the decimal value of the recurring binary number: (0.111111…..)2 ?
a. (1)10 b. (0.5)10 c. (0.5555….)10 d. (0.99)10

12. In 4-bit signed 2’s complement notation, the number (100)2 is interpreted in decimal as:
a. -4 b. +4 c. -8 d. 0

13. In signed magnitude BCD, the number (100110011001)2 is interpreted in decimal as:
a. +999 b. +99 c. -99 d. -999

14. For two-input binary functions, what function does 𝑥𝑦 + 𝑥′𝑦′ represent:
a. XOR b. Implication c. Inhibition d. Equivalence

15. Which of the following signed representations has one representation for zero:
a. 2’s complement b. 1’s complement c. signed-magnitude d. Both b. & c.

16. The AND of the two implication functions, (x implies y) AND (y implies x), gives:
a. Always 1 b. XOR of x, y c. XNOR of x, y d. Always 0

17. Which of the following functions does not follow the commutative law:
a. AND b. NAND c. Implication d. XOR

18. Which of the following functions does not follow the associative law:
a. OR b. NAND c. XNOR d. NOR

19. Which of the following gates can be used to make all other logic functions:
a. NAND b. AND c. OR d. NOT

20. The simplified expression of full adder carry for inputs x, y and z is
a) c = xy+xz+yz b) c = xy+xz c) c = xy+yz d) c = x+y+z

21. A sequential circuit has 𝑛 inputs, 𝑚 D-flip-flops and 𝑘 outputs. How many columns and rows
(respectively) does its state table have?
a) n+m+k, 2m b) 2n, 2(m+k) c) n+2m+k, 2(n+m) d) n+m+k, 2(n+m)

22. A 2-input XOR gate is implemented using NAND gates, assuming we only have A and B (and not
their complements), how many transistors are needed to implement it?
a) 16 b) 20 c)12 d) 10

23. Which of the following combinations of logic gates can decode binary 1101?
a) One 4-input AND gate b) One 4-input AND gate, one inverter
c) One 4-input AND gate, one 2-input OR gate d) One 4-input NAND gate

24. How many NOT gates are required for the construction of an 8-to-1 multiplexer using an AND-OR
implementation?
a) 3 b) 4 c) 2 d) 5

25. In a NAND based latch (𝑆̅𝑅̅), if both inputs are 1 then the state of the latch is
a) No change b) Set c) Reset d) Forbidden

26. The unsigned binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What
are the output levels?
a) (A > B) = 0, (A < B) = 0, (A = B) = 1 b) (A > B) = 1, (A < B) = 0, (A = B) = 1
c) (A > B) = 1, (A < B) = 0, (A = B) = 0 d) (A > B) = 0, (A < B) = 1, (A = B) = 0

27. Two 4-bit binary numbers (1011 and 1111) are applied to a 4-bit parallel adder. The carry input is 1.
What are the values for the sum and carry output?
a) S = 0111, C = 0 b) S = 1111, C = 1
c) S = 1011, C = 1 d) S = 1100, C = 1

28. If A is a positive number and B is a negative number, which of these operations might result in an
overflow:
a) A+B b) A-B c) -A-B d) A-1
29. In the design of a single digit BCD multiplier, what is the size of the output?
a) 6-bit b) 8-bit c) 2-bit d) 4-bit

30. In case of an n-bit binary multiplier, the number of AND gates and the size of the output (respectively)
are:
a) n2, 2n b) 2n, 2n c) n2, n d) 2n, n

31. A combinational circuit is to be designed which takes a single 4-bit BCD digit as input and outputs 1
if the digit ≥ 4, and 0 otherwise. Using only basic gates, what is the minimum number of gates
required?
a) 4 b) 6 c) 3 d) 0

32. Consider a multiplexer with X and Y as data inputs and Z as select input. Z = 0 selects input X, and Z
= 1 selects input Y. What are the connections required to realize the OR Boolean function f = T + R,
without using any additional hardware?
a) R to X, 1 to Y, T to Z b) T to X, R to Y, T to Z
c) T to X, R to Y, 0 to Z d) R to X, 0 to Y, T to Z

33. How many 2-to-1 MUXes are required to create a 4-to-1 MUX, without any additional gates?
a) 4 b) 2 c) 3 d) 5

34. Using a 4-bit 2’s complement arithmetic, which of the following additions will result in an overflow?
(i) 1100 + 1100 (ii) 0011 + 0111 (iii) 1111 + 0111
a) (i) only b) (ii) only c) (i) and(iii) d) All

35. The characteristic equation of NOR SR latch is

a) Q(t+1) = (S + Q(t))R’ b) Q(t+1) = SR + Q(t)R’
c) Q(t+1) = S’R + Q(t)R d) Q(t+1) = S’R + Q’(t)R’

36. A Toggle flip-flop with T = 1 has a 20 kHz clock input. The Q output is:
a) Constantly LOW b) A 40 kHz square wave
c) A 20 kHz square wave d) A 10 kHz square wave

37. Which of the following binary number looks the same as its 2's complement?
a) 1010 b) 0101 c) 1000 d) 1001

38. The output of a tristate buffer when the enable input is 0 (deactivated) is
a) Always 0 b) Always 1 c) Last input d) Floating

39. If we wish to assign a code to all the 52 playing cards, what is the minimum number of bits
required?
a. 3 b. 4 c. 6 d. 7

40. The state of a 12‐bit register is 100110010111. What is its content if it represents a 3-digit
decimal number in 9’s complement BCD?
a. -3 b. -997 c. +997 d. -4

41. The complement of the function 𝐹 = 𝑥𝑦 + 𝑤𝑧 is:

a. 𝑥 ′ 𝑦 ′ + 𝑤′𝑧′ b. (𝑥 ′ + 𝑦 ′ )𝑤′𝑧′
c. (𝒙′ + 𝒚′ )(𝒘′ + 𝒛′ ) d. 𝑥 ′ + 𝑦 ′ + 𝑤 ′ + 𝑧′
42. Given two eight‐bit strings A = 10110001 and B = 10101100, we go through the following
operations: 1. C=A+B; 2. D = A AND C; E = B EXOR D. What are the last two bits of E?
a. 00 b. 01 c. 10 d. 11

43. Express the function: 𝐹(𝑥, 𝑦, 𝑧) = ∑(1,3,5) in its simplest algebraic form:
a. 𝒛(𝒙′ + 𝒚′ ) b. a. 𝑧(𝑥 ′ + 𝑥𝑦 ′ ) c. a. 𝑧(𝑥 ′ 𝑦 + 𝑦 ′ ) d. a. 𝑥 ′ + 𝑦 ′ 𝑧

44. Assume that the exclusive-OR gate has a propagation delay of 10 ns and that the AND or OR
gates have a propagation delay of 5 ns. What is the total propagation delay time in a 4-bit
binary adder without carry propagate circuit?
a. 10 ns b. 20 ns c. 40 ns d. 60 ns

45. Assume that an exclusive-OR gate has a propagation delay of 10 ns and that AND or OR gates
have a propagation delay of 5 ns. What is the total propagation delay time in a full adder?
a. 10 ns b. 20 ns c. 15 ns d. 5 ns

46. What is the purpose of the carry propagation circuit in a binary adder?
a. To reduce calculation time b. To decrease circuit complexity
c. To make the design scalable d. All of the above

47. The characteristic equation for the complement output of a JK flip-flop is:
a. 𝐽𝑄 ′ + 𝐾𝑄 b. 𝐽𝑄 ′ + 𝐾′𝑄′ c. 𝐽𝑄 ′ + 𝐾′𝑄 d. 𝑱′𝑸′ + 𝑲𝑸

48. The characteristic equation for the output of a T flip-flop is:

a. 𝑇 + 𝑄 b. 𝑻 ⊕ 𝑸 c. 𝑇 + 𝑄′ d. 𝑇 ⊕ 𝑄′

49. The advantage of a serial adder over a parallel n-bit binary adder is:
a. Power required is lower b. Circuit is simpler
c. Silicon area required is lower d. All of the above

50. How many minimum flip flops are required to create a sequential circuit to detect a sequence
of 𝑛 consecutive 1s?
a. log2(n) b. n c. 2n d. log2(n+1)

51. The contents of a four‐bit register is initially 0110. The register is shifted six times to the right
with the serial input being 1011100 (LSB input first). What is the content of the register?
a. 1011 b. 1101 c. 0110 d. 0100

52. How many flip‐flops will be complemented in a 10‐bit binary ripple counter to reach the next
count after 100110011?
a. 3 b. 4 c. 2 d. 1

53. A flip‐flops has a 4 ns delay from the time the clock edge occurs to the time the output is
complemented. What is the maximum frequency at which a 10‐bit binary ripple counter that
uses these flip‐flops can operate reliably?
a. 20 MHz b. 250 MHz c. 25 MHz d. 10 MHz

54. A memory has 8-bit data line and 16-bit address line. What is the size of the memory?
a. 64 kB b. 32 kB c. 512 kB d. 1 MB
55. Given the 8‐bit data word 01011011, generate the 13‐bit composite word for the Hamming
code that corrects single errors and detects double errors.
a. 0101101110011 b. 0011101110101 c. 0000101010111 d. 0000101110110

56. How many parity check bits must be included with the data word to achieve single‐error
correction and double‐error detection when the data word contains 64 bits?
a. 7 b. 6 c. 5 d. 8

57. What is the reduction in the transistor count of the address decoder if we use row/column
coincident decoding for an 8-bit address?
a. 3872 b. 2752 c. 5132 d. 3124