5.

82

EXEROCISE Digital Creuty

MCQTYPE QUESTIONS 7. The dual of the Boolean theorem
1. Boolean expression for the output of the logic A. (B + C) = A.B + A.C is
circuit shown in the figure is (a)A + (B +C) = A.B + A.C
(b)A. (B +C) =(A + B) (A+C)
(c) A + B.C = (A + B) (A +C)
(d) None of these
8. Boolean expression for the
outputAof XNOR
(Equivalent) logic gate with inputs
(a)Y = AB+ AB +C (b) Y =A B + AB + C
(a) AB+ AB (b) AB+ AB
and B, is
(c) Y =AB + A B+C(d) Y = AB + AB+ C
2. A combinational circuit has inputs A, B and C (c) (A + B)(A + B) (d) (A + B)(A+B)
and its Karnaugh Map is as shown. The output 9. The output ofa logic gate is"T
of the circuit is given by when all its innuts
are at logic »0°. The gate is either
AB
(a) (AB+AB}C 00 01 11 10
(a)NAND or EX-OR gate
(b) NOR or EX-NOR gate
(b) (AB+AB)C 1 1
(c) OR or EX-NOR gate
(c) ABC 1 1
(d)AND or EX-0R gate
(d)A BC 10. The gate shown in the figure is
3. For the identity AB+ BC= AB + A C.the Voc
dual form is
(a) (A + B) (A +C)(B+C)=(A+B)(A +C)
(b) (A +B) (A +C) (B+C)=(A+B) (A +C) V
(c) (A + B) (A +C)(B+C)=(A+ B) (A +C)
(d) AB+ AC+BC=AB+AC
4. The logical expression Y=A+ A Bis equivalent (a) AND gate (6)NAND gate
to
(c) NOT gate (d) OR gate
(a)Y = AB (6) Y =AB 11. When signed numbers are used in binary
(c) Y= A +B arithmetic, then which of the following notations
(d) Y = A + B would have unique representation for zero?
5. Minterms coresponding to decimal number (a) Sign-magnitude
15 is
(6) 1's complement
(a) ABCD (b) ABCD (c) 2's complement
(c) A+B+C+ D (d) 9's complement
(d) A+ B+C+D
6.
12. The logic circuit given below converts a binary
Minimized expression for the K-map shown code Y, Y, Y, into
below is
Y Y
00
01

10

(a) AB C D+ A CD
(b) AB CD+A CD+ABC X. X
(c) BC D +CD+ A BC (a) Excess-3 code (6) Gray code
(c) BCD code
(d)Hamming code
(d)B C D +CD+ BC
Digital Circuits
5.83
minimum Boolean expression for the
The
13. circuit is given 19. Boolean expression for shaded area is
B

(a)AB + AC + BC (6) A + BC C

(c) A + B (d) A+B +C

Venn diagram representing the Boolean (a)ABC + ABC (6) AB+ BC + CA
expression A+(A .B) is
(c) ABC+ABC+ ABC (d) ABC + A BC+ ABC
(a)| 20. Boolean expression for shaded area is

A
(6)|

(c
A
(a) AB + BC
(6) ABC+AB C
(c) ABC+A BC+A BC
(d) ABC+ AB
15. Complement of the Boolean expression 21. In the circuit shown in figure, value of input p
goes from 0 ’ 1and that of goes from 1 ’ 0.
AB.(BC+Ac) is Which output forms shown in figure represents
(a)(A + B)+ (B+ C). (A + C) the output under a statichazard conditions ?
(b)( B)+ (BC + A C) pO

Q
(c) ( + B).(B+ C). (A + C)
(a)
(d)(A +B).(B + C). (A +C)
16. The logicfunctionf= (x. )+x. v) 1S the Same as
(6)
(a)f= (x + y) (x+ y) (6) f= y+ xy
(c)
(e)f=(x.y). (xy) (d) none of these
17. The minimal product-of-sums function described
by the K-map given in the figure is, don't care (d)
L
22. The maximized expression for the
00 01 11 10 K-map is (X: don't care) given
AF
1 1 0 00 11 10

1 00 1 1

(a)A'C' (b) A' C' 01 1

(c) A+ C (d) AC
18, Boolean expression 11 1 1 X

XYZ +
can be XÝZ+XY7,+XÝZ
+ XYZ 10 1 X

(a) xZ+simplified
to
(6) XZ + YZ+ YZ (a)C B + BD + CD (b) AB + CB + BC
XZ+ YZ
(c) XY + (d) xY+ YZ +XZ
(c)CB + AC + BC (d) CB+ CD +CB
YZ+ XZ
5.84
be I's 27. It is desired to generate the
Digital Circuits
23. In figure shown below, r, r, x, will
complement of A, A, A, if
A
Boolean functions:
f = abc + abe + bc
fol owing three
f= abc + ab + abc
A,
f,= abe + abc + c
by using an OR gate array as shown
where P, and P, are product terms in in figure,
one or more
of the variable a, a, b, b, c andc
P,
(a)Y= 0 (b) Y = 1 P
P.
(c) Y= A= A.= A,d) Y=A, =A, =A, P,
24. The circuit of a gate in the resistor transistor
logic (RTL) family shown in the given figure is Ps
a/an
F,
The terms P,, P,, P, P, and P, are
(a) ab, ac, b, bc, ab
(b) ab, bc, ac, ab be
(c) ac,ab, bc, ab, bc
(d)all of these
(a) AND gate (6) OR gate 28. The circuit shown in the figure converts
(c) NAND gate (d) NOR gate
MSB
25. K-map for a Boolean function is shown in the
figure. The function would be
yz
00 01 11 10
00
01 1
1
1
1
1
D
11
MSB
10
(a) BCD to binary code
(a)(r +)(w+ y) (6) (x + z) (w + y) (6) Binary to excess
(c) ( +Z) (w + ) (d) none of these (c) Excess-3 to Gray Code
26. For the K-map shown in figure, the minimized (d) Gray to Binary code
function in SOP form is 29. The switching circuit given in the figure can be
YZ expressed in binary logic notation as
00 01 11 10 L
00 1 1 1
01
WX 11 B

10 1

(a) WXY+ WY +XYZ+ WXZ

(b) W X Y + X Z + W Y (a)L= (A + B) (C+ D) E
(b)L= AB + CD + E
(c) WXY+WY +WXYZ+WXYZ (c) L= E + (A + B) (C+ D)
(d) WXY+ WY + WXZ (d)L= (AB + CD)E
DigitalClircuits
5.85
30. Ifnegative logic is used, diode gate shown in the
gven figure will represent a/an 34. In the given network of AND and OR gates,
fcan be written as

O 0V
X
BO V=-5V
-5V

(a) ORgate (b) AND gate

(c) NOR gate (d)) NAND gate (a)x, x,, ..x, + x, x,... x, + x, X,-.. , ... X,
o1 Which of the following is the truth table of the (6)x, x, +x, x, +... + *
given logic is true ? (C) x, + x, + X, +.. + x,
+ +x,_,,t,
yO z
35. Output Y of the circuit shown in the figure is
B

(a) (6) yz
0 ( 0
0 1
D
0
E
1 1|1 (a)(A + B)C + DE (6) AB +C(D + E)
(c) (A + B) C + D + E (d) (AB + C) . DE
(c) (d)
36. The figure given below shows the circuit of which
0 one of the following is
1|0 1 1

00 +VpD
10 10
R
Voi C
32. For a binary half-subtractor having two inputs
Aand B, correct set of logical expression for the
outputs D (=Aminimum B) and X(=borrow) are
Vino
(a)D= AB + AB, X= AB
(a) Bi-stable multi-vibrator
(b)D = A B+ AB,X= AB (6) Schmitt trigger
(c) D= AB+ AB,X = AB (c) Mon0-stable multi-vibrator
(d) Astable multi-vibrator
(d)D = AB + AB.X=AB 37. A full-adder can be implemented with half
33. The circuit shown in the given figure is alan adders and OR gates. A4-bit parallel full adder
without any initial carry requires
(a) 8 half-adders,4-OR gates
(6)8 half-adders, 3-0R gates
(c) 7 half-adders, 4-0R gates
(d) 7 half-adders, 3-0R gates
38, Afour-variable switching function has minterms
and m,. If literals in these minterms are
complemented,
numbers are
then corresponding minterm
(a)m, and m, (6) m, and m,
(a)adder (6) subtractor
(c) m, and m, (d) m, and m,
parity generator (d) comparator
5.86
the figure below,
S9. For the gate network shownisinredundant?
43. The output of the circuit willbe Digital Clrcuts
which of the following gate

(a) Gate No-1 (6) Gate No-2

(d) Gate No-4 (a)ABCD + A BCD + A BCD + A
(c) Gate No-3
40. In the logic circuit shown in the figure, output
X is
(6)ABCD + ABCD + ABCD + ÁX BCDD
(c) ABCD +A BCD + A BCD + A BAR
(d)AB CD+ ABCD + ABCD +ABCD
44. The type of gate shown in the given fgure i.

Co

(a)A B+BC+CA
(6)A + B +C (a)NOR (b) OR
(c) AB + BC + CA (c) NAND (d) EX-OR
45. The input pulses to the different stages of the
(d) AB + BC + CA
41. Consider the following expressions circuits shown in the following figure must
be of
1. Y=f(A, B, C, D) =E (1, 2, 4, 7,8, 11, 13, 14)
2. Y=fA,B, C, D)= E(3, 5,7,10, 11, 12, 13, 14)
3. Y=fA, B,C, D) = n (0, 3, 5, 6, 9, 10, 12, 15) T. 0.

4. Y =fA, B, C, D) = n (0, 1, 2, 4, 5, 8, 9, 15) CK CK CK

Which of these expressions are equivalent to the input
expression Y =ABOCD?
(a)2 and 3 (6) 1 and 4 Output
(c) 2 and 4 (d) 1 and 3 (a)constant frequency and constant width
42. For the circuit shown in figure
(b) constant frequency bit variable width
A B (c) variable frequency bit constant width
(d)variable frequency as well as variable widh
46. The output y for the logic circuit shown in the
given figure is
Ao

Bo
(a) F=A + B (6) F = AB (a)AB (b) A + B
(c) F = A + B (d) F = AB (c) A + B (d) A + B
DigitalCircuits 6.87
47. The half adder circuit, in the given figure has used to
inputs AB= 11. The logic level of P and
51. The circuit given in the figure is to be
will be Qoutputs implement the function
A
Z= f(A, B) = + B.
J?
what values should be selected for I and
J

i)P= 0 and Q = 0 (6) P= 0 and Q=1

(c) P= 1 and Q = 0 (d) P= 1 and Q = 1
(b) I = 1 J= B
(a)I = 0 JB
48 Forthe digital circuit shown in figure, the output (d) I= B J= 0
Q.Q,Q,Qo = 0001 initially. After a clock pulse (c) I= B J=1
appear, the output Q,,Q,Qo will be
52. In a JK flip-flop we have J = Q and K = 1.
Assuming the flip-flop was initially cleared and
then clocked for 6 pulses, the sequence at the Q.
0o Q J, Q, then clock for 6 pulses, the sequence at the Q
output will be

(a)0001 (b) 0011 Ck

(c) 0100 (d) 1100 A

49. The output Q, of a J-K flip-flop is zero. It change

to l when a clock pulse is applied. The input J.
and K, are respectively (a)010000 (6) 011001
(c) 010010 (d) 010101
(a)l and X (b) 0 and X
(c) X and 0 (d) X and 1 53. The Q output of a J-K flip-flop is '1'. The output
does not change when a clock-pulse is
50. To realise the given truth table from the circuit applied.The inputs J and K will be respectively
shown in the figure, the input to J in terms of A X-denotes don'tcare state)
and B would have to be
(a)0 and X (b) X and 0
(c) 1 ando (d) O and 1.
Ao J
Combinational 54. The block diagram shown below represents
Bo logic
J
J

Clock Clear Clear

Truth Table
A BQ.1J
0 (a)modulo - 3 ripple counter
1
(6) modulo - 5 ripple counter
1 1
(c) modulo -7 ripple counter
(d)modulo -7 synchronous counter
X 55. The characteristic equation of the T-FF is given
by
(a) AB
(b) A (a)Q = TQ+ TÍ (6) Q = TQ + QT
(c) B (c) Q= TQ (d) Q= TQ
(d)AB