eG e 2022/2023 Digital Logic Design Model Exam ; terms igre FOR THE FOLLOWING QUESTIONS, Wee 2 LEITER WITH BEST ALTERNATIVE. ER WT “J Which one ofthe etosng statement sincere about analog and digital systems? - A. Analogue r presentation ives a continuous output B. Digital representation produces sda F © Physica quamtes sch ree a iy certo & taped are analogue innate CPD Analogue variables ‘are digitized at the input with the help of an analogue-to-digital converter E. None of th above @ Which one of the following is not advantages of digital systems? A Availability of digital Signals in nature C. Reliability 2B. Flexibility De Cost Q Typical Voltage range assignment/represeniction for binaiy bits is known as A. Quantization QD Logic level ™ B. Sampling D. Timing diagram @ One of the following statement isnot true ‘bout integrated circuit fabrication technologies. single small chip of D, nidite#-fanction lopic IC the lope fnetions are set by the manufacturer and cannot be altered. D. NONE (S> One of the fottowin, ‘A: The number of independent digits used in the Q Given that hexadecimal number sequence as 445, 446, 487, 4A8,.. which one of the following sequence shows the next three numbers? 1A9, 4AA, 4AB; D) 489, 4BA, 4BB t 7, B) B99A, B99B, B99C E) NONE C) $A9,5A6,5A7,5A8 (8) Choose the different ‘one among the given binary codes ~~ _A) BCD code ©) Gray code B) Excess 3 code D) NONE | © Logie diagram is composed of graphic symbols fo logic gates. i | 22) LL OF THE anovE \ AB NONE OF THE ABOVE iBee | - * : € Z y 2022/2023 Digial Lose Design Model Exam tp Gay Which of fie following ways caunat be used (or representing logis HincUous rte» pesent te gates Doz alt B) Truth tables NON — At) Fortwo Boolean \ociables X and ¥ with X=1, VSG; whatis funaion (KY) (XY? A) FOGY)=0 OFKY=2 = 7, RO ties Xn tx yon Peete ee é Boolean \ariables X and Y with X=1, Y=0, what is function F(X, ¥) =REK+Y ics Ora Pao Ls aay Feesimplied foxy oF Boo iyi : ied form of Boolean expression (X+¥'+) - AL XAYAZ 7 CO . nro 3 BL XY+¥Z J = Referring to 4 variables K-map given in the rellowing table answer question 14 aad question 15 fable t eh yo9 ne | 00 AN (14) Which one of the following Boolean function can be represented in the above table A) T1M(@O2, vais) | B Dm(1,3,4,6,9,11,12) .7,8,10,13,15) E) None of the above B) Emo, ©) 11M(13.4,6,9,11,12) (15) The simplified form of Boolean expression given in the K-map will be A) A'R) 4 BD’ + BD! D) B'C' + BC G xe) Gath) B) A‘B’C’ + BCD’ + BD’ E) A'D'+ AC ete 7 C) B'D'+ BD (16) ‘he éaponieal form of topical expresion(A-G=BY) 5 ©. ABYA'BHAB EX yentt BBLABSAB ‘B, A'B'+AB+AB! D. A'B+AB'+AB. (17) The canonical form of logical expression (AB!) (BYC) is C. (A#B+C)) (A+B'+C) (AMB'C) ‘A. (AtB44C) (AFB4C) (ABO) B. (A+B'C) (A*B4C) (ABC) D. (A#B4C) (A¥B'+C) (ABC) (18) A half adder adds. .....bits. AL 16 c.8 xt W B.3 QD J 419) Parallel binary adders are A ‘Combinational logic circuits C. Both of the above © Sequential logic circuits D. none of the above (20) A combinational circuit which is used to change a decimal number into an equivalent BCD ren C. Multiplexer 7 D. Demultiplexer (BeEreoser a wre) ‘0 ror rene qor pe FAS Ke rer i9 digs) + HB Meas M6 i i.\v 2022/2025 Digital Loge Design Model Exams | i “Qi Aconbisayiaiah dea ei number into an equivalen, @1) A combinational ci uit which is used to change a BCD umber is C. Multiplexer _-<€APDecoder D. Demultiplexer B. Encoder (22) Multiplexer is also Lnown as C. Multiplexer D. Encoder i Ice t0 tWO OF more fata coming from a single sour A> Data selectae B. Data distribyior> @3) A combinational ciscuit which is used to sen Separate destinations is called as: A. Decoder B. Encoder 6 4) Find the base X if 202(x) = [df08i66; Oe Be ee De E, NONE ida third state that is called high impedance, ‘. Multiplexer B,-Demuliplexer 25) A Tristate buffer has 3 states: logic 0, logic which je A) Behaves like a closed circuit b ibe | B) Behaves like a buffer oS On Be ©) Behaves like an inverter oS Ih D) Behaves like a i So ars 26) How many fall adders are required to build a 7-6 ripple carry adder? cs Be om D8 27)-Which ofthe following combinational logic cincuits can be used to check for errors in @ communication system? < A parity checker v B. A multiplexer a) C. A magnitude comparator D. An inverter checker (28) Why is a N-bit binary ripple carry adder extremely stow? A. Because it is implemented with half adders B. Because itis implemented with full adders C. Because each stage must wait for the next one to D. Because each stage must wait forthe previcy (29) Digital iogic circuits in which the logic sister determine the state of the outputare called ‘A) Combinational logic circuits Wo Regueatad logic circuits B) Reasonable logic circuits D) Automated logic circuits (30) How many different fut cons wil produce a HIGH ouput ona three-Gout OB gate? A)3 co) 8 B) s or G1) The combinational circuits can be specified in ne oF the folfowing whys except: A) A set of statements inite Sta in B) Boolean expression E) None of the above C) Truth table, Ofs+ Be Se ey Cy 4 “Be =) Hypyh a _ le S tH wee eto&. P 2022/2023 Digital Logic Design Modit Exam (82) With shorthand nutations logical functions 9 three variables Peer ia Zm( 0, 1, 3,6) can be WBC FAB + A'BC+ ABC’ © BB OYA BOW ) ABC +A'B'C+A'BC+A'BC D) NONE OF Hit Saou SBaquase sey 33) What is the simplest Boolean expression for the circuit shown below A) ABT +BC* x” B) ABC’ +ABC (AYB")(B+C") (ONE 7 A) BAC B) BA +BC C) B.@B + BC) D)ALL |ONE (35) What function F(x, ¥, 2) is ‘© implemented in the figure to the right? c Gr A) XOYR! eKYT ar axa 2B) (KTHYERT) . OREYTHZND pox : cy xrya" sxyr ar exyra D) (xr sv42"). (KEYTART) GY? #2) F) NONE Figuretee? i ‘ re Kye) A900) if lm Exam £2 2022/2023 Digital Logic. a ee Bale mene 9 ‘fe. ae # itgiveninfigureg © FS Far questions 36. 37 and 38 refer to the following cireult gine =. ee ey é é | J \ 1 aagbt Figaie 4 Taplenstatlon of logic functions using Multiplexers pe *£© (36) Which one of he given alternative shows output A as functions of inputs x, yand 2. j A) 2+ (X@Y) ©) Z-(K@Y)+xY 2) 240K) J -—O DA ZK G7) Which one of the given altemative shows output B as funions of inputs x, y and z. A) Z+ (XY) Z- (XBY) + XY B) 2+ (X®Y) D) Z@(X®Y) What device is implemented using the multiplexers as shown in Figure 4 A) Full adder subtractor COP subtractor Sharam TD) None oe | 89) One of the following statement is incorrect about Flip-flops and latches, A) Flipsops nd ltches are gta memory circuits ee B) Latches are a memory device that does not require cay extemal timing signals. ss Epps always require a special clock ignite simee tema ee ce CH=8 fling edge gered Mip-ops samples inputs depending on a LOWso-HIGH tation on he tage se le, te catiaole HS, 0 (40) Consider the following cross-coupled NOR RS latch. given in figure 5. Which state about the ereuit? Line 9 gfete ov A) The RS latch can be-forced to hold a 1 when the Set line is G8) am tement is false / asserted. ~ B) The RS latch can be forced to hold a 0 when the Reset line is asserted, ©) The RS latch will hold its current value (state) if the Set and Reset lines are not asserted, D) The RS latch will Disallowed Condition when both its input is ed (gotta) Sopoeorricnion xu f; Figure \Cross-coupled NOR RS latch gen #Lee\, ov wot 5 fomeeet eA™2022/2025 Digital Logi: Design Model Exam (41) The symbols for the active high and active low RS latches are shown below in figure, Which statement is false about the two circuits?) — * |A) Active High indicates that « high (1) will activate the line. B) Active Low indicates that a low (0) will activate the line. "9 Y : ft value (state) D) Agsive high RS latch can be impletnented by Cross-coupled ‘ | DegOglnd active tow RS Late inleentd coseeonpled Actively Aree fone ofthe above ho cn | BK + (42) What is the minimum number of SK Seded to build a mod 2sunchrasous-counter Gounts rom Ot0 11)? GR Geouns omot0 1"? Rtas fy, ° D1 omy “W Qs py2 Oe at . (43) Which is incogrect aBott a counter oo 'A) Ina syngkFhous counter, all the flip-flops inthe counter change state athe same time a Asynchronous counters egmnfgon clock signal is simultaneously applied tothe elock inputs ' GRAN i pp aa fall the flip-flops Th gfhchronous counter or parallel counter, th ptk Be is applied only to the first flip-flop. nous counters are slower than their Asynchronous counters ») x Consider the following 3:bit ripple counter given in figure below, with initially all flip-flops is reset to zero. Assuming the clock signal input to FEO As shown on the right, Then Answer the following, questions pun (44) What will be the binary sequence of 20100 After fifth clock Transition? Oa ci @ B) 110 pn (45) Atwhich clock transition do the first change in state of Q2 occurs 1 ©" clock transition C) 8" clock transition, B) 4 clock transition D) St clock transition (46) How long in terms of clock eyele it takes forthe counter shown above to reset to intial state GAY ye BF SE ER BS bate fh. | ay ie Ke vy 4 (> 5 Sesh) L pave arb vorny = Bea 0. What willbe the next value of Q2Q1Q0 of the Het Ts © 0 D. 100 44% DT ak aaesene domain AC oy in al shift registers is the flip- flop, mainly a D-type flip-flop.” *squals the total number of Fi flops used to i OT Me feo Mas aot _ Vga uw i cK = seve pL < Reset _ am A, g, Ta Serial-in serial out (SISO) Shift registers B) Serial. 5) Parallel in parallel out (PIPO) shit registers Parallel out (SIPO) shift registers D) Parallel in Serial out (PISO) shif registers, (0) Digital logic circuits in which the loge states of the Current inputs at any given instant and ite ay Previous state output determine the state ofthe cursese output are called A) Combinational logic circuits ©) Sequential logic circuits B) Reasonable Idgic circuits £0 | _D) Automated logic circuits 4 ya ys asad igh De Hes =] Is