2 Digital Logic

Practice Questions

Number System
Q.1 4-bit 2's complement representation of a Q.6 Consider the equation (123)5 ( x 8) y
decimal number is 1000. The number is with x and y as unknown. The number of
(A) +8 (B) 0 possible solutions are ________.
(C) – 7 (D) – 8 Q.7 If (101)b ( D2)16 (467)10 . Then the
Q.2 Decimal 43 in Hexadecimal and BCD
value of radix ‘b’ is _______.
number system is respectively
(A) 13 (B) 14
(A) B2, 01000011
(C) 18 (D) 16
(B) 2B, 01000011
Q.8 The number ( A72E )16 is equivalent to
(C) 2B, 0011 0100
(D) B2, 01000100 (A) (1010001100101110)2 and
Q.3 X = 01110 and Y = 11001 are two 5-bit (123456)8
binary numbers represented in two's (B) (1010011100111111) 2 and
complement format. The sum of X and Y
(123456)8
represented in 2's complement format
using 6 bits is (C) (1010011100101110)2 and
(A) 100111 (B) 001000 (123456)8
(C) 000111 (D) 101001 (D) None of these
Q.4 The two numbers represented in signed
Boolean Algebra
2's complement form are
P = 11101101 and Q = 11100110 Q.9 The K-map for a Boolean function is
If Q is subtracted from P, the value shown below. The number of essential
obtained in signed 2's complement form prime implicants for this function is
is
(A) 100000111 (B) 00000111
(C) 11111001 (D) 111111001
Q.5 What is the gray code word for the
binary number 101011?
(A) 110101 (B) 111110
(C) 101011 (D) 011111

Digital Logic 1
(A) 4 (B) 5 Q.16 Consider the Boolean function,
(C) 6 (D) 8 F ( w, x, y, z ) w y x y w x y z
Q.10 The logical expression y A A B is w x y x z x y z
equivalent to Which one of the following is the
(A) y AB (B) y AB complete set of essential prime
implicants?
(C) y AB (D) y A B
(A) w, y, x z, x z (B) w, y, x z
Q.11 The minimized form of the logical
(C) y, x y z (D) y, x z, x z
expression
Q.17 Find how many number of literals are
( A B C A BC A BC A BC ) is
there in given K-map by using all
(A) AC BC A B possible type K-map?
(B) AC B C A B CD
AB
(C) AC B C A B 1

(D) AC B C A B 1 1 1
1 1 1
Q.12 The number of distinct Boolean
expression of 4 variables is 1 1
(A) 16 (B) 256 (A) 4 (B) 14
(C) 1024 (D) 65536 (C) 17 (D) 8
Q.13 The Boolean expression Y ABC D Q.18 A function of Boolean variables X, Y and
A B C D A B C D A BC D can be Z is expressed in terms of the minterms
minimized to as F ( X , Y , Z ) ¦ m(1, 2, 5, 6, 7)

(A) Y A B C D A BC AC D Which one of the product of sums given

below is equal to the function
(B) Y A B C D BC D A B C D F ( X , Y , Z )?
(C) Y A BC D B C D A B C D (A) ( X Y Z )( X Y Z )( X Y Z )
(D) Y A BC D B C D A BC D
(B) ( X Y Z )( X Y Z )( X Y Z )
Q.14 The number of essential prime
(C) ( X Y Z )( X Y Z )
implicates in the function
f (a, b, c, d ) 6 (1, 2, 4, 5, 6, 7, ( X Y Z ) ( X Y Z )( X Y Z )
8, 9, 10, 11, 12, 15) (D) ( X Y Z )( X Y Z )
is ________. ( X Y Z ) ( X Y Z )( X Y Z )
Q.15 The Boolean expression Q.19 Consider the following expression :
(X Y) (X Y ) (X Y ) X f ( A, B, C, D) AD ABCD ACD
simplifies to AB ACD AB A( B A)
(A) X (B) Y The minimized expression of f ( A, B,
(C) XY (D) X+Y C, D) is equal to

2 Digital Logic
(A) AD (B) A D
(C) A BC (D) AD BC
Q.20 Consider the function
f ( A, B, C, D) 6m (1,5,7,12,13,14)
d (0, 3,11,15)
After implementing the given function
in minimal SOP form, what is the output (A) A BC
for the inputs ABCD 0011, 1011 and
(B) A B C
1111 respectively?
(C) AB BC A C
(A) 0, 0 and 1 (B) 0, 1 and 0
(C) 1, 0 and 1 (D) 1, 1 and 1 (D) AB BC
Q.24 The output of a logic gate is ‘1’ when all
Logic Gates
its inputs are at logic ‘0’. The gate is
Q.21 Consider the Karnaugh map given either
below, where X represents “don’t care” (A) a NAND or an EX-OR gate.
and blank represents 0. (B) a NOR or an EX-NOR gate.
ba (C) an OR or an EX-NOR gate.
dc 00 01 11 10 (D) an AND or an EX-OR gate.
00 x x Q.25 The minimum number of NAND gates
required to implement the Boolean
01 1 x
function A A B A B C is equal to
11 1 1 (A) Zero (B) 1
(C) 4 (D) 7
10 x x
Q.26 The output of the logic gate in figure is
Assume for all input (a, b, c, d), the
respective complements a , b, c , d
are also available. The above logic is
implemented using 2-input NOR gates (A) 0 (B) 1
only. (C) A (D) A
The minimum number of gates required Q.27 The minimum number of 2-input NAND
is _______. gates required to implement the Boolean
Q.22 Minimum number of 2-input NAND function Z A B C , assuming that A, B
gates required to implement the
and C are available is
function, F ( X Y )(Z W ) is (A) two (B) three
(A) 3 (B) 4 (C) five (D) six
(C) 5 (D) 6 Q.28 For the logic circuit shown in figure, the
Q.23 For the logic circuit shown in figure, the simplified Boolean expression for the
output is equal to [MSQ] output Y is

Digital Logie 3
If the decimal input is 92 then Yout
corresponds to lgv then value of m is___.
Q.33 The logic realized by the circuit shown
in figure is
(A) A + B + C (B) A
(C) B (D) C
Q.29 If the input to the digital circuit
consisting of a cascade of 20 X-OR
gates is X, then the output Y is equal to

(A) F A C (B) F A † C
(C) F B C (D) F B † C
(A) 0 (B) 1 Q.34 The output of the circuit shown in figure
(C) X (D) X is equal to
Q.30 The Boolean function Y = AB + CD is to
be realized using only 2-input NAND
gates. The minimum number of gates
required is
(A) 2 (B) 3
(C) 4 (D) 5 (A) 0
Q.31 For the output F to be 1 in the logic (B) 1
circuit shown, the input combination (C) A B A B
should be
(D) ( A † B) † ( A † B)
Q.35 A 2-bit binary multiplier can be
implemented using
(A) 2 input AND gates only.
(B) Six 2-input AND gates and two
XOR gates.
(A) A = 1, B = 1, C = 0 (C) Two 2-input NORs and one XNOR
(B) A = 1, B = 0, C = 0 gate.
(C) A = 0, B = 1, C = 0 (D) XOR gates and shift registers.
(D) A = 0, B = 0, C = 1 Q.36 The minimum number of 2 to 1
Combinational Circuits multiplexers required to realize a 4 to 1
Q.32 Consider the circuit given below : multiplexer is
I 21
2 * 1
(A) 1 (B) 2
MSB MSB
Decimal BCD
Gray
Code 2*×1 (C) 3 (D) 4
input Encoder Yout
Converter
LSB LSB I S 1
MUX Q.37 The Boolean function ‘f’ implemented
IS 0 S n1 S0
in the figure using two input
multiplexers is

4 Digital Logic
Q.40 The output Y of a 2-bit comparator is
logic 1 whenever the 2-bit input A is
greater than the 2-bit input B. The
number of combinations for which the
output is logic 1, is
(A) 4 (B) 6
(A) A B C A BC
(C) 8 (D) 10
(B) A BC A B C Q.41 Consider the multiplexer based logic
(C) A BC A B C circuit shown in the figure.
(D) A B C A BC
Q.38 For the circuit shown in the following
figure, I 0 - I 3 are inputs to the 4 : 1
multiplexer. R (MSB) and S are control
bits.
Which one of the following Boolean
functions is realized by the circuit?
(A) F W S1S2
(B) F W S1 W S2 S1S2
(C) F W S1 S2
(D) F W † S1 † S2
The output Z can be represented by,
Q.42 An 8 to 1 multiplexer is used to
(A) PQ P S Q R S
implement a logical function Y as shown
(B) PQ PQ R P Q S in the figure. The output Y is given by
(C) PQ R P Q R PQ R S Q R S
(D) PQ R PQ R S PQ R S Q R S
Q.39 The Boolean function realized by the
logic circuit shown is

(A) F 6m (0,1,3,5,9,10,14) (A) Y A B C AC D

(B) F 6m (2,3,5,7,8,12,13) (B) Y A BC AB D
(C) F 6m (1, 2, 4,5,11,14,15) (C) Y A B C AC D
(D) F 6m (2,3,5,7,8,9,12) (D) Y A BC ABC

Digital Logie 5
Q.43 Consider the given circuit (D)

The logic circuit above is used to

compare two unsigned 2-bit number.
Where A A1 A0 and B B1B0 , where Q.45 In the following circuit, X is given by
A1 and B1 represent MSB and A0 and
B0 represent LSB. Which of the
following will make output X 1
always.
(A) A ! B (B) A B
(A) X A B C A BC A B C A BC
(C) A r B (D) A t B
Q.44 If X and Y are inputs and the Difference (B) X A BC A B C A BC A B C
(D = X–Y) and the Borrow (B) are the (C) X A B B C AC
outputs, which one of the following
diagrams implements a half-subtractor? (D) X A B B C AC
(A) Q.46 Consider the combinational circuit
below :
0 0
1 1 4u 2 MSB
0
Priority MSB
1 2 encoder 1 4u2 Binary
Priority seven
0 3 segment Display
encoder
2 LED
display
I0 2 u1 3

MUX
(B) 0 I1 S 0

x 1

What is the output of the combinational

circuit?
(A) 1 (B) 2
(C) 3 (D) 4
Sequential Circuit
(C) Q.47 A-S-R flip flop with a clock input can be
converted to a ‘D’ flip flop using :
(A) Two inverters
(B) The flip flop outputs (Q & Q)
connected to its inputs (S & R)
(C) One inverter
(D) Not possible

6 Digital Logic
Q.48 For one of the following conditions, counter built with J-K flip flops. For
clocked JK flip-flop can be used as proper operation of the counter, the
divided by 2 circuit where the pulse train maximum permissible propagation
to be divided is applied at clock input : delay per flip flop stage is_______ nsec.
(A) J = 1, K = 1 and the flip-flop should Q.53 Consider the following J-K flip-flop
have active HIGH inputs.
(B) J = 1, K = 1 and the flip-flop should
have active LOW inputs.
(C) J = 0, K = 0 and the flip-flop should
have active HIGH inputs.
(D) J = 1, K = 1 and the flip-flop should
be a negative edge triggered one.
In the above J-K flip-flop, J Q and
Q.49 The mod number of a Johnson counter
will be always equal to the number of K 1. Assume that the flip-flop was
flip flops used : initially cleared and then clocked for 6
(A) Same pulses. What is the sequence at the Q
(B) Twice output?
(C) 2N where N is the number of flip (A) 010000 (B) 011001
flops. (C) 010010 (D) 010101
(D) None of the these Q.54 The ripple counter shown in the given
Q.50 A 4-bit presentable UP counter has figure is works as a
preset input 0101. The preset operation
takes place as soon as the counter
reaches 1111. The modulus of the
counter is
(A) 5 (B) 10 (A) MOD-3 up counter.
(C) 11 (D) 15 (B) MOD-5 up counter.
Q.51 The initial contents of the 4-bit serial-in- (C) MOD-3 down counter.
parallel-out, right-shift, Shift Register (D) MOD-5 down counter.
shown in the figure is 0110. After three Q.55 The given figure shows a ripple counter
clock pulses are applied, the contents of using positive edge triggered Flip-Flops.
the Shift Register will be If the present state of the counter is
Q2Q1Q0 011 then its next state Q2Q1Q0
will be

(A) 0000 (B) 0101

(C) 1010 (D) 1111
Q.52 A pulse train with a frequency of 1 MHz (A) 010 (B) 100
is counted using a modulo-1024 ripple- (C) 111 (D) 101

Digital Logie 7
Q.56 Two D flip-flops, as shown below, are to Q.59 The circuit shown consists of J-K flip-
be connected as a synchronous counter flops, each with an active low
that goes through the following Q1 Q0 asynchronous reset ( Rd input). The
sequence 00 o 01 o 11 o 10 o 00 counter corresponding to this circuit is
o…

(A) a modulo-5 binary up counter.

The inputs D0 and D1 respectively (B) a modulo-6 binary down counter.
should be connected as (C) a modulo-5 binary down counter.
(A) Q1 and Q0 (D) a modulo-6 binary up counter.
Q.60 Consider the following circuit :
(B) Q0 and Q1
(C) Q1Q0 and Q1Q0
(D) Q1Q0 and Q1Q0
Q.57 What are the counting state (Q1 , Q2 ) for
the counter shown in the figure below?
Each state of output is designated as a
two bit strings Q0Q1 . If the initial state
of flip-flops is 00, then the state
transition sequence is
(A)
(A) 11, 10, 00, 11, 10,…
(B) 01, 10, 11, 00, 01,…
(C) 00, 11, 01, 10, 00,… (B)
(D) 01, 10, 00, 01, 10,…
Q.58 Assuming that all flip-flops are in reset (C)
condition initially, the count sequence
observed at QA in the circuit shown is
(D)

Q.61 Which of the following functions are

self dual? [MSQ]
(A) F ( A, B, C ) 6{0, 2,3}
(B) F ( A, B, C ) 6{0,1,6,7}
(A) 0010111… (B) 0001011… (C) F ( A, B, C ) 6{0,1, 2, 4}
(C) 0101111… (D) 0110100… (D) F ( A, B, C ) 6{3,5,6,7}

8 Digital Logic
Q.62 A is a 9 bit singed integer the 2’s (A) 100 (B) 110
complement representation of A is (C) 101 (D) 010
(765)8 the 2’s complement Q.65 The 4 to 1 multiplexer shown below
representation of 6 u A is? implements the Boolean expression
(A) (202)8 (B) (676)8 I3
z I2
(C) (457)8 (D) (675)8 I1 F
O I 0 S1 S 0
Q.63 Consider the equation (57)X=(Y7)10
where X&Y are unknown then find the
number of possible solution. w x
Q.64 For the circuit shown in figure below If F (w, x, y, z ) 6m (4,5,7,8,10,12,15)
what is the output Q2Q1Q0 as per four The input to I1 & I 3 will be
clock pulse. Initially all flip flop are (A) yz, y ' z ' (B) y z ', y † z
reset.
(C) y’+z, yٖz (D) y ' z, y † z
Q0 Q1
D0 Q0 D1 Q1 D2 Q2
RC
Q2

CLK

Answers Digital Logic

1. D 2. B 3. C 4. B 5. B

6. 3 7. D 8. C 9. A 10. D

11. A 12. D 13. D 14. 2 15. A

16. D 17. B 18. B 19. B 20. C

21. 1 22. B 23. B, C 24. B 25. A

26. C 27. C 28. C 29. B 30 B

31. D 32. 219 33. B 34. B 35. B

36. C 37. A 38. A 39. D 40 B

41. D 42. C 43. A 44. A 45. A

46. B 47. C 48. D 49. C 50. B

51. C 52. 100 53. D 54. D 55. B

56. A 57. A 58. D 59. A 60. C

61. C,D 62. B 63. 6 64. B 65. C

Digital Logie 9
Q.62 A is a 9 bit singed integer the 2’s (A) 100 (B) 110
complement representation of A is (C) 101 (D) 010
(765)8 the 2’s complement Q.65 The 4 to 1 multiplexer shown below
representation of 6 u A is? implements the Boolean expression
(A) (202)8 (B) (676)8 I3
z I2
(C) (457)8 (D) (675)8 I1 F
O I 0 S1 S 0
Q.63 Consider the equation (57)X=(Y7)10
where X&Y are unknown then find the
number of possible solution. w x
Q.64 For the circuit shown in figure below If F (w, x, y, z ) 6m (4,5,7,8,10,12,15)
what is the output Q2Q1Q0 as per four The input to I1 & I 3 will be
clock pulse. Initially all flip flop are (A) yz, y ' z ' (B) y z ', y † z
reset.
(C) y’+z, yٖz (D) y ' z, y † z
Q0 Q1
D0 Q0 D1 Q1 D2 Q2
RC
Q2

CLK

Answers Digital Logic

1. D 2. B 3. C 4. B 5. B

6. 3 7. D 8. C 9. A 10. D

11. A 12. D 13. D 14. 2 15. A

16. D 17. B 18. B 19. B 20. C

21. 1 22. B 23. B, C 24. B 25. A

26. C 27. C 28. C 29. B 30 B

31. D 32. 219 33. B 34. B 35. B

36. C 37. A 38. A 39. D 40 B

41. D 42. C 43. A 44. A 45. A

46. B 47. C 48. D 49. C 50. B

51. C 52. 100 53. D 54. D 55. B

56. A 57. A 58. D 59. A 60. C

61. C,D 62. B 63. 6 64. B 65. C

Digital Logie 9
Explanations Digital Logic

1. (D) 4. (B)
The given number 1000 comes under special Given : P = 11101101, Q = 11100110
case of 2’s complement which has single ‘1’ Both P and Q are in signed 2's complement
followed by zeros. form.
Decimal equivalent number of 2’s complement The MSB denotes sign of given number i.e. if
representation with single ‘1’ followed by ‘n’ MSB is 0 then given number is positive and if
number of zeros (2)n . MSB is 1 then given number is negative.
Given 2's complement number contain 3 zeros P = 11101101
after ‘1’, so the decimal number is (2)3 8 . Since MSB of P is 1, hence it is a negative
Hence, the correct option is (D). number.
Original number P = 2's complement of P
2. (B)
Thus, the 2's complement of P will be
(i) Decimal to Hexadecimal : = 10010011
= – 19
Similarly, the 2's complement of Q will be
Hence, (43)10 o (2B)16
(ii) Decimal to BCD :
(43)10 (01000011)BCD
Hence, the correct option is (B). Thus, P Q 19 (26) 7
Now, 7 00000111
3. (C)
The signed 2’s complement of a positive
Given : X 01110 and Y 11001
number is identical to the sign magnitude form
MSB of both numbers represent sign bit. Since of the positive number.
MSB of X is 0, hence it is positive number and
7 00000111
since MSB of Y is 1, hence it is negative
number. Hence, the correct option is (B).
5. (B)
Given number
101011 (In Binary)

Since carry is discarded in the addition of two

number represented in 2's complement, hence
X Y 00111
X Y , in 6 - bit representation =
000111 For four bit binary (b3b2b1b0 ) to four bit gray
Hence, the correct option is (C). code ( g3 g2 g1 g0 )

Digital Logic 10
8. (C)
Given : ( A72E )16
Each hexadecimal bit is represented by 4 bit.
(1010011100101110)2
For octal representation grouping of 3 bit is
done.
001010011100101110
5 4 3 2 1 0
Circuit for Binary to Gray (123456)8
Hence, answer is option (B).
Hence, the correct option is (C).
6. 3
9. (A)
( x 8) y (123)5
Given K-map is shown below,
y ! x, y ! 8
xy 8 1u 52 2 u 5 3
xy 8 25 10 3
xy 30
As we have,
y ! x and y ! 8
xy 8 38
To find the number of essential prime
xy 30
implicants, follow the procedures listed below :
x 1, y 30 valid
(i) Make all possible pairs in decreasing
x 2, y 15 valid order i.e. from Oct o Quad o Pair o
x 3, y 10 valid Single.
Hence, 3 possible values exists. (ii) For every group, find the number of 1’s
that are only one time circled i.e. the
7. (D)
number of Essential Prime Implicants
(101)b (467)10 ( D2)16 …(i) (EPI). Hence, the number of Essential
Converting into equivalent decimal numbers, Prime Implicants (EPI) = 4.
(D2)16 (2 u160 ) (13u161 ) 210 Hence, the correct option is (A).
(101)b (1u b0 ) (0 u b1 ) (1u b2 ) b2 1 10. (D)
From equation (i),
Given y in SOP form as,
b2 1 467 210
y A AB
b2 1 257
Converted above equation into standard
b 2 256
canonical SOP form as,
b 16
Hence, the correct option is (D). y A( B B ) AB

Digital Logie 11
y AB AB AB 13. (D)
(10) (11) (01)

So, y can be written in the form of minterms as, Given Y in SOP form as,
y 6m(01, 10, 11) Y A B C D A BC D AB C D ABC D
y 6m(1, 2, 3) Minimization using K-map :
Apply K-map for minimization of y, Y A B C D A BC D AB C D ABC D
(0001) (0110) (1001) (1100)

Y can be written in minterms as,

Y ¦ m (1, 6, 9, 12)
K-map for Y in SOP form as,

So, minimized form of y from K-map is,

y A B
Hence, the correct option is (D).
11. (A)
Minimization using K-map,
y A BC A BC A BC ABC
(000) (010) (011) (110)

So, y can be written in minterm form as, Therefore, minimized Y from above K-map,
y 6m(000, 010, 011, 110) Y A BC D B C D ABC D
y 6m(0, 2, 3, 6) Hence, the correct option is (D).
y can be minimized using K-map in SOP form
14. 2
as, shown below,
Given :
f ( A, B, C, D) 6 (1, 2, 4, 5, 6, 7,
8, 9, 10, 11, 12, 15)
CD
AB
Minimized expression of y is given below,
1 1
y AC A B BC
Hence, the correct option is (A). 1 1 1 1

12. (D)
1 1
The number of distinct Boolean expression for
n
n variables (N) 22 1 1 1 1
Here, n 4
4
Hence, N 22 216 65536 There is only 2 essential prime implicants.
Hence, the correct option is (D). Hence, the correct answer is 2.

12 Digital Logic
15. (A) ­ wxyz 5 m5
° wxyz 7 m7
Given : °
xz o ®
F ( X Y )( X Y ) ( X Y ) X ° wxyz 13 m13
°¯wxyz 15 m15
F ( X Y Y ) ( X Y ) X ª¬ Y Y 0º¼
­ wx y z 8 m8
x y z o®
F X (X Y ) X ¯w x y z 0 m0
Applying De-Morgan’s Rule So, function F (w, x, y, z ) is in SOP form,
F X XY X F (w, x, y, z ) 6m (0, 2, 3, 5, 6, 7,
Again, apply De-Morgan rule, 8, 10, 11, 13, 14, 15)
F X (X Y)X K-map for F is shown below,
F X X X Y X ª¬ X X 0º¼
F X Y X
F X (1 Y ) > 1 Y 1@
F X (1) X
Hence, the correct option is (A).
16. (D)
Given 4-variable function ( F ) in SOP form is,
F ( w, x, y, z ) w y x y w x y z Essential prime implicants : Number of prime
w x y x z x y z implicants in which any of “1” is one time
grouped is called Essential Prime implicant.
Converting each product term of ( F ) into
Hence, essential prime implicants are
standard canonic minterms as, y, x z, x z .
­wxyz 10 m10 Hence, the correct option is (D).
° wxyz 11 m11
°
wy o ® 17. (B)
°wxyz 14 m14
°¯ wxyz CD
15 m15 AB 00 01
11 10
00 1
­ wxyz 6 m6
° wxyz 7 m7 01 1 1 1
°
xy o ® 1
°wxyz 14 m14 11 1 1
°¯ wxyz 15 m15 10 1 1

wxyz o 7 m7 SOP ACD ABC ABC ABC BD

­w xyz 2 m2 ePI
w xy o ®
¯ w xyz 3 m3 Total literals = 14.
Hence, the correct option is (B).

Digital Logie 13
18. (B) f ( A, B, C, D) AD AB
Given : Output for A, B, C, D 0011, 1011 and 1111
F ( X , Y , Z ) 6m(1, 2,5,6,7) o SOP form is,
Expression is given in SOP formd but options f (0, 0, 1, 1) 1 0 1
are given in POS form. Hence, convert it into f (1, 0, 1, 1) 0 0 0
POS form. f (1, 1, 1, 1) 0 1 1
Maxterm of given function is shown below, Hence, the correct option is (C).
F ( X , Y , Z ) 3M (0, 3, 4) o POS form
21. 1
F ( X , Y , Z ) 3M (000, 011, 100)
AB
F ( X , Y , Z ) ( X Y Z )( X Y Z ) CD 00 01 11 10
(X Y Z) 00 d d

Hence, the correct option is (B). 01 1 d

19. (B) 11 1 1

The given expression is, 10 d d

f ( A, B, C, D) AD ABCD ACD B .D
AB ACD AB AB AA Here clearly says that complement of input is
CD also present.
AB CD CD CD CD B
1 BD B. D B. D
AB 1 1 1
A
AB 1 1 1 1 D

AB 1 1
Only 1 NOR gate is required.

AB 1 1 22. (B)

D Given 4-variable function ( F ) is,

The minimized expression of f ( A, B, C , D) is F ( X Y )(Z W )
A D. Apply De-Morgan law,
Hence, the correct option is (B). F ( X Y )(Z W )
20. (C) F ( X Y )Z ( X Y )W
Given : Again, apply De-Morgan law,
f ( A, B, C, D) 6m (1,5,7,12,13,14)
F X Y Z ˜ X YW
d (0, 3,11,15)
This function can be implemented using only 2-
input NAND gates:

14 Digital Logic
Thus, minimum number of 2-input NAND gate 25. (A)
required to realize the given function are 4.
Given : F A AB ABC
Hence, the correct option is (B).
F A (1 B B C )
23. B,C
( 1 Any literal 1)
Givenlogic circuit is shown below, F A
To implement A, zero NAND gates are required,
we can use a connecting wire to produce A.

Hence, the correct option is (A).

26. (C)
Given logic gate is shown below,
Output Y can be written as given below,
Y A AB BC C o Option (C)
Apply De-Morgan rule,
Y A ( A B) (B C ) C This is an EX-NOR gate, output of an EX-NOR
gate is given by,
( A A A, B B B, C C C)
F A B
Y A B C o Option (B)
F AB AB
Hence, the correct options are (B) and (C).
Here, A A and B 0
24. (B) Hence, F A 0 A 0
Given : Output of a logic gate is “1”, when all F 0 A
its inputs are at logic “0”. F A
There are only three gates i.e., NOR, NAND and Hence, the correct option is (C).
EX-NOR which will produce logic 1 at its
output, when all of its input is at logic 0. 27. (C)
NOR gate : Given : Z ABC
Z can also be written as,
Y0 1, when X Y 0 Z A B C AC B
NAND gate : Realization of Z using two input NAND gate is
shown below,

Y0 1 when X Y 0
EX-NOR gate :

Thus, minimum number of 2-input NAND gates

Y0 1 when X Y 0
required to realize the given function are 5.
Hence, the correct option is (B). Hence, the correct option is (C).

Digital Logie 15
28. (C) 29. (B)
Given logic circuit is shown below, Digital circuit is shown below,

From above circuit,

Output of 1st EX-OR gate X † 1 X
Given circuit is shown below, Output of 2nd EX-OR gate X † X 1
Hence, it can be concluded that output will be
‘1’ for even numbers of EX-OR gates and
output will be X for odd number of EX-OR
gates.
i.e. output after 20th EX-OR gate = 1.
Hence, the correct option is (B)
30. (B)
Shifting bubbles as shown by dotted lines then
circuit becomes as, Given : Y AB C D
Y can also be written as,
Y AB C D
Y AB C D
Now realize the function Y, using 2-input
NAND gate.

Replace bubble AND by OR gate and bubbled

NOR by AND gate so circuit becomes as,

Hence, the correct option is (B).

31. (D)
Logic circuit is shown below,

So, Y B ˜ (B C )
Y B ˜ B BC ( BB B)
Y B(1 C ) ( 1 C 1
1)
Y B Output F can be written as
Hence, the correct option is (C). F ( A † B) ( A B) C

16 Digital Logic
For even number of inputs XOR is equal to
34. (B)
complement of XNOR
Given : Logic circuit as shown below,
i.e. A† B A B
and XNOR is equality detector
So, ( A † B) ( A B) C 1
Now, F ( A † B) ( A B) C
We Know that XNOR hate output are high when
number of one’s are appeared even time. If we From above logic circuit,
perform XOR and XNOR for two variables only X A B and Y A B
one output are high. Output F is given by,
Because they both are complement of each F X Y
other, and if we want F = 1 then C must be 1. F (A B) (A B)
Ÿ C 1 is the required input condition
F (A A) (B B)
Hence, the correct options are (D).
F 0 0 [ X X 0]
32. 219
F 1
1. Convert 92 to bcd 10010010 Hence, the correct option is (B).
2. Convert to grey cod 11011011
3. Values of select lines set are 11011011, 35. (B)
where leftmost digit is MSB. So decimal
2-bit multiplication can be represented as given
equivalent of 11011011 will be the
selected input line Ÿ m 219 below,

33. (B)
Given : A 4 u1 MUX as shown below,

The above expression can be represented by

logic circuit as shown below,
Output F can be written as,
F S1S0 I0 S1S0 I1 S1S0 I2 S1S0 I3
Here, selection lines : S1 A , S0 B
Inputs : I 0 I1 C and I 2 I3 C
Thus, F A B C A BC A B C A BC
F AC ( B B) AC ( B B)
( B B 1)
F AC AC
F A†C Thus, 2 EX-OR and 6 AND gates are used.
Hence, the correct option is (B). Hence, the correct option is (B).

Digital Logie 17
36. (C) Output Z can be written as,
Z S1S0 I0 S1S0 I1 S1S0 I 2 S1S0 I3
The number of multiplexer required to
implement nu1 MUX using m u 1 MUX is Inputs : I0 P Q , I1 P , I2 PQ , I 3 P
given below, Selection lines : S1 R, S0 S
n n n Thus Z becomes as,
2 3 ..... so on until ratio d 1
m m m Z R S I0 R S I1 R S I 2 R S I3
Since, n 4 and m 2 Z R S ( P Q) R S P R S PQ R S P
Hence, number of 2 u1 MUX required to realize
Z P R S Q R S P R S PQ R S P R S
4 4
4 u1 MUX 2 1 3 (8, 12) (0, 8) (9, 13) (14) (11,15)
(11
2 22
Z 6m(0, 8, 9, 11, 12, 13, 14, 15)
37. (A) K-map for Z is shown below,
Given logic circuit is shown below,

Output of the 1st stage E is given by, Hence, Z PQ P S Q R S

E B C BC Hence, the correct option is (A).
nd
Output of the 2 stage f is given by,
39. (D)
f E ˜0 E ˜ A
Given logic circuit is shown below,
Hence, f EA
f ( B C BC ) A
f AB C ABC
Hence, the correct option is (A).
38. (A)

Given logic circuit is shown below,

Output F, of the above circuit is given by,

F S1 S0 I0 S1S0 I1 S1S0 I 2 S1S0 I3
…(i)
Selection line : S1 A , S0 B
Inputs : I 0 C , I1 D , I2 C , I3 CD
Put all the above values in equation (i),

18 Digital Logic
F A B C A B D A B C A BC D 1 0 1 1 0 m11
Converting above equation standard canonical m12
1 1 0 0 1
SOP form,
F A B C ( D D) A B D(C C ) 1 1 0 1 1 m13
A B C ( D D) A BC D 1 1 1 0 1 m14
F A B C D A B C D A BC D A BC D 1 1 1 1 0 m15
(3) (2) (7) (5)
Now, the truth table for ( A ! B) is shown below,
AB C D AB C D ABC D
(9) (8) (12)
A1 A0 B1 B0 Y Min-term
Thus, F 6m(2, 3, 5, 7, 8, 9, 12) 0 1 0 0 1 m4
Hence, the correct option is (D).
1 0 0 0 1 m8
40. (B)
1 0 0 1 1 m9
Let, 2-bit input binary number A and B as,
A A1 A0 ½ 1 1 0 0 1 m12
¾ 2-bit input binary number
B B1B0 ¿ 1 1 0 1 1 m13
According to question,
1 1 1 0 1 m14
Y 1 , if A ! B
Y 0 otherwise Thus, the number of combinations for which the
Based on above condition we can form truth output is logic “1” = 6.
table is shown below, Hence, the correct option is (B).
Y 41. (D)
A1 A0 B1 B0 Min-term
A! B
Given multiplexer circuit is shown below,
0 0 0 0 0 m0
0 0 0 1 0 m1
0 0 1 0 0 m2
0 0 1 1 0 m3
0 1 0 0 1 m4
Output of MUX 1 is given by,
0 1 0 1 0 m5 M S1W S1W
0 1 1 0 0 m6 M S1 † W
0 1 1 1 0 m7 Output of MUX 2 is given by,
1 0 0 0 1 m8 F S2 M S2 M

1 0 0 1 1 m9 F S2 (S1 † W ) S2 (S1 † W )
F S2 † S1 † W
1 0 1 0 0 m10
Hence, the correct option is (D).

Digital Logie 19
42. (C) B o Borrow
Thus, circuit diagram and expression of
Given 8 u1 MUX shown below,
difference (D) and borrow (B) of half subtractor
is shown below,

Choosing from options,

From option (A) :
Here, A, B, C are the selection lines.
Output Y for 8 u1 MUX is given by,
Y A B C I0 A B C I1 A BC I 2
A BC I3 ABC I 4 ABC I5
ABC I6 ABC I 7
…(i)
For upper MUX,
From figure,
I0 I2 I4 I5 I7 0 D SI0 SI1
I1 I3 D Here, S X , I0 Y , I1 Y
I6 1 D XY XY
D X †Y
Put the above values in equation (i),
For lower MUX,
Y A B C D A BC D A BC
B SI0 SI1
Y AC D( B B) A BC
Here, S X , I0 Y , I1 0
Y AC D A B C
B XY X 0
Hence, the correct option is (C).
B XY
43. (A) So, D shows expression of difference and B
X A1B1 ( A1 B1 )( A0 B0 ) (output) shows expression of borrow of half-subtractor.
Thus, option (A) is correct.
A1 1, B1 0 then X 1
From option (B) :
If A1 B1 (when MSB are equal)
A0 1, B0 0 then X 1
It is equal to 1 when A ! B.
Hence, (A) is correct.
44. (A)
Given : X and Y o Input
D X Y o Difference

20 Digital Logic
For upper MUX,
D SI0 SI1
Here, S Y , I0 X , I1 X
D YX YX
D X †Y
For lower MUX,
B SI0 SI1
For upper MUX,
Here, S Y , I0 X , I1 0
B SI0 SI1
B YX Y (0)
Here, S Y , I0 X , I1 X
B YX
B YX YX (X †Y )
So, D shows expression of difference of half
subtractor but B does not shows expression of For lower MUX,
borrow of half-subtractor. D SI0 SI1
Thus, option (B) is incorrect. Here, S Y , I0 X , I1 0
From option (C) : D YX Y (0)
D YX
So, D does not shows expression of difference
of half subtractor and B does not shows
expression of borrow of half-subtractor.
Thus, option (D) is incorrect.
Hence, the correct option is (A).

For upper MUX, 45. (A)

B SI0 SI1 Given MUX circuit is shown below,
Here, S X , I0 Y , I1 Y
B XY XY
B X †Y
For lower MUX,
D SI0 SI1
Output S1 of the 1st stage is given by,
Here, S X , I0 Y , I1 0
S1 A B I0 A B I1 AB I 2 AB I3
D XY X (0)
Here, I 0 I3 0
D XY
So, D does not shows expression of difference and I1 I2 1
of half subtractor and B does not shows Hence, S1 A B ˜ 0 A B ˜1 AB ˜1 AB ˜ 0
expression of borrow of half-subtractor.
S1 A B AB
Thus, option (C) is incorrect.
From option (D) : S1 A† B

Digital Logie 21
Output X of the 2nd stage is given by III. I/P of Binary to seven segment display
X S1S0 I0 S1S0 I1 S1S0 I 2 S1S0 I3 = 10
Which display ‘2’
Here, I 0 I3 0
Hence, the correct option is (B).
I1 I 2 1 and S1 A † B , S0 C
47. (C)
Hence, X ( A † B)C ˜ 0 ( A † B) ˜ C ˜1
One inverter
( A † B)C ˜1 ( A † B)C ˜ 0 SR flip flop
X ( A † B)C ( A † B)C
S
X A† B †C 6m(1, 2, 4, 7)
X A B C A BC A B C A BC Q

Hence, the correct option is (A).

CK
46. (B)
0 0 I
Q
1 1 4u 2 MSB
0 II III
Priority MSB R
1 2 encoder 1 4u2 Binary
Priority seven
segment Display
0 3
2
encoder
LED D flip flop from SR flip flop
display S
I0 2 u1 3
S
MUX
0 I1 S 0 Q
x 1

I. Priority Encoder CK

B1B0 o O /Ps having B1 as MSB. Q

B1 I1I 0 ( I 2 † I3 )
R
0.1( I † 0) 0 R

B0 I 0 ' I 2 '( I1 † I3 )
48. (D)
1.0(1 † 0)
MSB( B1 ) 0 o I 0 of IInd P. Encode Dividing pulse train by 2 means making period
of pulse double or making frequency as half.
B0 0 o I1 of II P. Encode
This can be done if JK flip flop works in toggle
MUX mode (J = 1 and K = l) and flip flop should be
y S0 I0 S1I1 negative edge triggered so output changes only
0.1 1.0 0 on negative transition of pulse.
y 0 o I3 of IInd P. Encode So, option (D) is answer.
I 0 1.7 MUX o I 2 of IInd P. Encode 49. (C)
II. P. Encoder
In Johnson counter if you have n number of flip
P1 I1 ' I 0 ' ( I 2 † I3 ) 1.1(1 † 0) 1
flop then we have 2N state. So it is also known
P0 I1 ' I 2 '( I1 † I3 ) 0 as mod 2N counter.

22 Digital Logic
QA QB QC QD A3 A2 A1 A0 1010.
0 0 0 0 Hence, the correct option is (C).
1 0 0 0 52. 100
1 1 0 0
1 1 1 0 Given : Modulo, M = 1024
1 1 1 1 fclock 1 MHz
0 1 1 1 For Ripple counter, M 2n
0 0 1 1 where, M Modulo of counter
0 0 0 1 n Number of flip flops
Repeat Hence, n log 2 M
Qa Qb Qc Qd n log 2 (1024)
D Q D Q D Q D Q n log2 210
n 10
Propagation delay of a ripple counter is given
RESET
by,
CLK
1
Johnson counter t pd
n fclock
50. (B)
1
The count goes from 5 to 14 and then as soon as t pd 107 sec
10 u106
we get 15 preset occurs so 15 will not be t pd 100ns
considered as output as preset occurs and output
Hence, the maximum permissible propagation
becomes 5 and then again it goes from 5 to 14.
delay per flip flop stage is 100 nsec.
So, it is mod 10 counter (option B).
53. (D)
51. (C)
J-K flip flop is shown below,
Given : 4 bit serial in parallel out right shift,
shift register is shown below,

Stat table for input and output of above J-K flip-

flop are shown below,
Input Output
CLK
J Q K 1 Q
0 - - 0 [initially]
1 1 1 1
2 0 1 0
Content of shift register after 3-clock pulse

Digital Logie 23
3 1 1 1 55. (B)
4 0 1 0
Given ripple counter is shown below,
5 1 1 1
6 0 1 0
7 1 1 1
Thus, the sequence is 010101 .... and output
waveform is shown below, Given : Q2 Q1 Q0 011 o Initial state
It is a ripple counter with positive edge triggered
Hence, the correct option is (D). and output of Q is connected to clock of next
(The arrangement of JK-flip-flop given in Q flip-flop. Hence, it is an up-counter.
question work as alternate 1 and 0 generator.)
Q2 Q1 Q0 Nextstate Q2 Q1 Q0
54. (D)  o
0 1 1 1 0 0
Given logic circuit is shown below, (3) (4)
Hence, the correct option is (B).
56. (A)

Count sequence for synchronous counter is

given by,
From the above circuit we can observe :
(1) The flip flops are positive edge State table for above sequence is shown below,
triggered, and the output Q of one flip Present state Next state Inputs
flop acts as clock input for next flip flop Q1 Q0 Q1 Q0 D1 D0
hence, it is a down counter.
0 0 0 1 0 1
(2) The output of the AND gate is connected
0 1 1 1 1 1
to preset input,
1 1 1 0 1 0
Preset is 1 only when C B A 1 (i.e.
1 0 0 0 0 0
C 0, B 1, A 0 )
(Inputs D1 and D0 are sets according to the
excitation table of D-flip-flop).
K-map for D1 is shown below,

Hence, the given circuit is a MOD-5 down Hence, D1 Q0

counter.
K-map for D0 is shown below,
Hence, the correct option is (D).

24 Digital Logic
Given circuit is a 3-bit synchronous sequential
circuit, with D-flip-flop are connected in
cascaded manner so circuit can be reduced into
shift register format as,

Thus, D0 Q1
Hence, the correct option is (A).
57. (A)
(Initially QAQBQC 000 )
Given circuit is 2-bit synchronous sequential
So, state table formed as,
circuit as shown below,

State table for the given counter is shown below,

Present Next
Inputs
state states
J1 K1 J2 CP
K2 So, count of (QA ) o 01101000 …..
Q1 Q2 Q1 Q2
Q2 Q2 Q1 1
Hence, the correct option is (D).
0 0 1 1 1 1 n 1 1
59. (A)
1 1 0 0 0 1 n 1 0
Given counter is asynchronous counter with
1 0 1 1 0 1 n 0 0
negative edge triggering.
0 0 1 1 1 1 n 1 1 Q is applied as negative edge triggering clock.
Thus, the count sequence (Q1 Q2 ) is Hence it is an up counter.
11, 10, 00, 11, 10… Reset signal Q2Q0
Hence, the correct option is (A).
Q2 Q1 Q0 Reset Q2Q0
58. (D)
0 0 0 1
Given logic circuit is shown below, 0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
0 0 0

Digital Logie 25
Counter resets at 101 hence, it is a MOD-5 X t 8& Y d 9
counter. Because if number is 7 then minimum possible
Hence, the correct option is (A). base is 8
60. (C) Similarly if base is 10 then maximum possible
number is 9
61. (C,D) So we solve these two equations.
Any function is self dual function if it (57)X=(Y7)10
complement is always self dual. 5 u X 1 7 u X 0 Y u101 7 u100
(0.7)(1,6)(2,5)(3,4) are the pairs for self dual 5 X 7 10Y 7
Option (A) is false because here no element for 5 X 10Y
pair (1, 6) X 2Y …(i)
Option (B) (0,7) and (1,6) are both are appeared is Y 1, X 2 - False because ( X t 8)
in a single pair so it is also false 4 - False because ( X t 8)
is Y 2, X
Option (C) Ture :- Because {0, 1, 2, 4} all are
is Y 3, X 6 - False because ( X t 8)
appeared in a different pair
Option (D) True: Because {3, 5, 6,7} all are is Y 4, X 8 - True
appeared in different pair is Y 5, X 10 - True

62. (B) is Y 6, X 12 - True

is Y 7, X 14 - True
A (765)8 is 111110101 in binary note that
is Y 8, X 16 - True
most significant bit in the binary representation
is 1, which implies that the number is negative. is Y 9, X 18 - True
To get the actual value of the number perform is Y 10, X 20 -
the 2’s complement of the number we get A as False because (Y d 9)
–11
So total 6 cases are possible
(765)8 1111110101
64. (B)
p
2’s complement 000001011= –11 In the above diagram,
We know that initially all flip flop are reset and
And 6 u A is 11u 6 66
Qn+1=D that means if D is one than Q is also 1
Since 6 A is also negative we need to find 2’s
in below table.
compliment of it (–66) binary representation of
66 = 001000010 2’s compliment of 66 = –66 = Q2 is MSB & Q0 is LSB
110111110 (676)8 D2 Q1
So the correct option is B D1 Q0
63. 6 & D0 Q1.Q2 or Q1 NAND Q2 we know that
(57)X=(Y7)10 Qn1 D that means is D is one then Q1 is
According to the number system concept initially all flip flop are reset

26 Digital Logic
Clock Output states Inputs
status
Q2 Q1 Q0 D2 D1 D0

0 0 0
I1 y ' z
After 1st 0 0 1 0 0 1 I2 z ' (Given in question)
clock
I3 y ' z ' yz y z
pulse
Present Next
After 2nd 0 1 1 0 1 1 Flip flop Inputs
state states
clock
pulse D1 Q0 † Q1
Q0 Q1 D0 Q0 Q0 Q1
Q0 Q1
After 3rd 1 1 1 1 1 1
clock 0 0 1 1 1 1
pulse 1 1 0 1 0 1
0 1 1 0 1 0
After 4th 1 1 0 1 1 0
1 0 0 0 0 0
clock pulse
00 11 01 10
Correct option is B
65. (C) Hence, the correct option is (C).
™™™™
We have 4 variables (w, x, y, z ) here w & x are
selection line so y & z are inputs and the
function is 6m (4,5,7,8,,10,12,15)
So 4:1 mux table are

I0 0 (Given in question)
Solution for I1
Using k-map I1 y ' z ' y ' z yz
Solution for I1
Using k-map I1 y ' z ' y ' z yz

Digital Logie 27