9/8/2016

DIGITAL ELECTRONICS
(Flip Flop and Counter)
Prof. S.K. Patra
Electronics & Communication

FLIP-FLOPS
• A flip-flop is a circuit that has two stable states and can be used to
store state information
• Can keep a binary state until an input signal to switch the state is
received
• There are different types of flip-flops depending on the number of
inputs and how the inputs affect the binary state

SR FLIP-FLOP
• Using NOR Implementation (Positive Logic)

1
9/8/2016

SR FLIP-FLOP
• Using NAND Implementation (Negative Logic)

SR FLIP-FLOP With Timing Diagram

SR FLIP-FLOP With Clock Input

2
9/8/2016

SR Flip-Flop With Positive Edge Triggered

D Flip-Flop
• It is triggered every time the pulse goes to the logic level 1
• As long as the pulse remains at the logic level 1, the change in the data (D)
directly affects the output (Q)

Level Triggering v/s Edge Triggering

• Level Triggered

3
9/8/2016

Level Triggering v/s Edge Triggering

• Edge Triggered

D Flip-Flop As Buffer

JK FLIP-FLOP
• The JK flip-flop augments the behavior of the SR flip-flop (J=Set,
K=Reset) by interpreting the J = K = 1 condition as a "flip" or toggle
command.

4
9/8/2016

JK Flip-Flop From SR Flip-Flop

Master-Slave JK Flip-Flops
• The outputs from Q and Q from the “Slave” flip-flop are fed back to the inputs of the “Master”
with the outputs of the “Master” flip flop being connected to the two inputs of the “Slave” flip-
flop.
• When the clock is “LOW”, the outputs from the “master” flip flop are latched and any additional
changes to its inputs are ignored.
• Then on the “Low-to-High” transition of the clock pulse the inputs of the “master” flip flop are
fed through to the gated inputs of the “slave” flip flop and on the “High-to-Low” transition the
same inputs are reflected on the output of the “slave” making this type of flip flop edge or pulse-
triggered.
• the Master-Slave JK Flip flop is a “Synchronous” device as it only passes data with the timing of
the clock signal.

Timing Diagram (Positive Edge Triggered)

5
9/8/2016

T Flip-Flop
• It has one input, named T.
• If the T input is high, the T flip-flop changes state ("toggles")
whenever the clock input is strobed, giving an output which is half the
frequency of the signal to the T input.
• If the T input is low, the flip-flop holds the previous value.

Clk

Timing Diagram T Flip-Flop

Counters

• Counters are a specific type of sequential circuit.

• The output value increases by one on each clock cycle.
• After the largest value, the output “wraps around” back to 0.
• Asynchronous (ripple) counter – changing state bits are used as clocks
to subsequent state flip-flops
• Synchronous counter – In synchronous counters, the clock inputs of
all the flip-flops are connected together and are triggered by the
input pulses. Thus, all the flip-flops change state simultaneously (in
parallel).

6
9/8/2016

Asynchronous Counter

• Modulo - 4 Counter
• If the clock has period T. Q0 has period 2T. Q1 period is 4T
• With n flip flops the period is 2n.

Asynchronous Counter
• Modulo - 8 Counter
• This is called as a ripple counter due to the way the FFs respond one
after another in a kind of rippling effect.

Asynchronous Counter
• Modulo-16 Counter

7
9/8/2016

Asynchronous Counter
• Modulo – 10 Counter:

Divide-by-n (Modulo n) Counter

Count is remainder of division by n which n may not be a power of 2 or Count is arbitrary sequence
of n states specifically designed state-by-state

• The following techniques use an n-bit binary counter with asynchronous or synchronous clear and/or
parallel load:
• Detect a terminal count of N in a Modulo-N count sequence to asynchronously Clear the count to 0 or
asynchronously Load in value 0 (These lead to counts which are present for only a very short time and can
fail to work for some timing conditions!)
• Detect a terminal count of N - 1 in a Modulo-N count sequence to Clear the count synchronously to 0
• Detect a terminal count of N - 1 in a Modulo-N count sequence to synchronously Load in value 0
• Detect a terminal count and use Load to preset a count of the terminal count value minus (N - 1)

Synchronous counter
• Modulo-4 Synchronous Counter

8
9/8/2016

Synchronous counter
• Modulo-8 Synchronous Up Counter

Synchronous counter
• Modulo-16 Synchronous Up Counter

Synchronous counter
• Modulo-10 Synchronous Up Counter