0% found this document useful (0 votes)
51 views

Pic Micro Controllers

PIC microcontrollers have the following key features: 1. They can execute most instructions in 0.2 microseconds and have an instruction set of only 35 simple instructions. 2. They integrate features like power-on reset, brown-out protection, and watchdog timers to ensure reliable operation. 3. They use a Harvard architecture with separate memory for program and data, allowing instructions to be fetched and executed in single clock cycles for high performance.

Uploaded by

Satya Krishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
51 views

Pic Micro Controllers

PIC microcontrollers have the following key features: 1. They can execute most instructions in 0.2 microseconds and have an instruction set of only 35 simple instructions. 2. They integrate features like power-on reset, brown-out protection, and watchdog timers to ensure reliable operation. 3. They use a Harvard architecture with separate memory for program and data, allowing instructions to be fetched and executed in single clock cycles for high performance.

Uploaded by

Satya Krishna
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

PIC MICRO CONTROLLERS

SALIENT FEATURES
 Speed :
When operated at its maximum clock rate a PIC executes most of its instructions in 0.2
s or five instructions per microsecond.
 Instruction set Simplicity:
The instruction set is so simple that it consists of only just 35 instructions
 Integration of operational features:
Power-on-reset (POR) and brown-out protection ensure that the chip operates only
when the supply voltage is within specifications. A watch dog timer resets the PIC if the chip
malfunctions or deviates from its normal operation at any time.
 Programmable timer options:
Three timers can characterize inputs, control outputs and provide internal timing for
the program execution.
 Interrupt control:
Up to 12 independent interrupt sources can control when the CPU deal with each
sources.
 Powerful output pin control:
A single instruction can select and drive a single output pin high or low in its 0.2 s
instruction execution time. The PIC can drive a load of up to 25A.
 I/O port expansion:
With the help of built in serial peripheral interface the number of I/O ports can be
expanded. EPROM/DIP/ROM options are provided.
 High performance RISC CPU

1
 Operating speed: DC – 20 MHz clock input DC – 200 ns instruction cycle
 Eight level deep hardware stack
 Direct, indirect and relative addressing modes
 Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
 Three Timers Timer0, Timer 1 and Timer 2.
 Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation
 Programmable code-protection
 Power saving SLEEP mode
 10-bit multi-channel Analog-to-Digital converter
 Selectable oscillator options
 One USART /SCI port with 9-bit address detection.
 Low-power, high-speed CMOS EPROM/ROM technology
 Fully static design
 Wide operating voltage range: 2.5V to 6.0V
 Commercial, Industrial and Extended temperature ranges
 Low-power consumption: <2mA @5V, 4MHz, 15 A typical @ 3V, 32 kHz, <1 A
typical standby current

ARCHITECTURE
The PIC16FXX is a family of low-cost, high-performance, CMOS, fully-static, 8-bit
microcontrollers.
All PIC microcontrollers employ an advanced RISC architecture. The PIC16FXX
microcontroller family has enhanced core features, eight-level deep stack, and multiple
internal and external interrupt sources. The two-stage instruction pipeline allows all
instructions to execute in a single cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction set) are available. Also, a large register
set helps to achieve a very high performance.
. The PIC 16FXX uses Harvard architecture, in which, program and data are accessed
from separate memories using separate buses. This improves bandwidth over traditional Von

2
Neumann architecture where program and data may be fetched from the same memory using
the same bus. Separating program and data buses further allows instructions to be sized
differently than 8-bit wide data words. Instruction opcodes are 14-bits wide making it possible
to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-
bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of
instructions. Consequently, all instructions execute in a single cycle (200 ns@ 20MHz) except
for program branches.

3
Block diagram of PIC 16F87X Microcontroller

The PIC 16F87X devices have a 13-bit program counter capable of addressing an 8KX14
program memory space.The PIC 16FF876/877 devices have 8Kx 14 words of Flash program
memory .The RESET vector is at 0000h and the Interrupt vector is at 0004h.

You might also like