Not Recommended For New Designs

CC2420

2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver

Applications

 2.4 GHz IEEE 802.15.4 systems  Wireless sensor networks

 ZigBee systems  PC peripherals
 Home/building automation  Consumer Electronics
 Industrial Control

Product Description

The CC2420 is a true single-chip 2.4 GHz features reduce the load on the host
IEEE 802.15.4 compliant RF transceiver controller and allow CC2420 to interface
designed for low power and low voltage low-cost microcontrollers.
wireless applications. CC2420 includes a
digital direct sequence spread spectrum The configuration interface and transmit /
baseband modem providing a spreading receive FIFOs of CC2420 are accessed via
gain of 9 dB and an effective data rate of an SPI interface. In a typical application
250 kbps. CC2420 will be used together with a
microcontroller and a few external passive
The CC2420 is a low-cost, highly integrated components.
solution for robust wireless communication
in the 2.4 GHz unlicensed ISM band. It CC2420 is based on Chipcon’s SmartRF-
complies with worldwide regulations 03 technology in 0.18 m CMOS.
covered by ETSI EN 300 328 and EN 300
440 class 2 (Europe), FCC CFR47 Part 15
(US) and ARIB STD-T66 (Japan).

The CC2420 provides extensive hardware

support for packet handling, data
buffering, burst transmissions, data
encryption, data authentication, clear
channel assessment, link quality indication
and packet timing information. These

Key Features

 True single-chip 2.4 GHz IEEE  Programmable output power

802.15.4 compliant RF transceiver  No external RF switch / filter needed
with baseband modem and MAC  I/Q low-IF receiver
support  I/Q direct upconversion transmitter
 DSSS baseband modem with 2  Very few external components
MChips/s and 250 kbps effective data  128(RX) + 128(TX) byte data buffering
rate.  Digital RSSI / LQI support
 Suitable for both RFD and FFD  Hardware MAC encryption (AES-128)
operation  Battery monitor
 Low current consumption (RX: 18.8  QLP-48 package, 7x7 mm
mA, TX: 17.4 mA)  Complies with ETSI EN 300 328, EN
 Low supply voltage (2.1 – 3.6 V) with 300 440 class 2, FCC CFR-47 part 15
integrated voltage regulator and ARIB STD-T66
 Low supply voltage (1.6 – 2.0 V) with  Powerful and flexible development
external voltage regulator tools available

SWRS041c Page 1 of 85
Not Recommended For New Designs
CC2420

Table of contents

1 Abbreviations _________________________________________________________________ 5
2 References ___________________________________________________________________ 6
3 Features _____________________________________________________________________ 7
4 Absolute Maximum Ratings _____________________________________________________ 8
5 Operating Conditions __________________________________________________________ 8
6 Electrical Specifications ________________________________________________________ 9
6.1 Overall ___________________________________________________________________ 9
6.2 Transmit Section ___________________________________________________________ 9
6.3 Receive Section ___________________________________________________________ 10
6.4 RSSI / Carrier Sense _______________________________________________________ 11
6.5 IF Section ________________________________________________________________ 11
6.6 Frequency Synthesizer Section _______________________________________________ 11
6.7 Digital Inputs/Outputs ______________________________________________________ 12
6.8 Voltage Regulator _________________________________________________________ 13
6.9 Battery Monitor ___________________________________________________________ 13
6.10 Power Supply _____________________________________________________________ 13
7 Pin Assignment ______________________________________________________________ 15
8 Circuit Description ___________________________________________________________ 17
9 Application Circuit ___________________________________________________________ 19
9.1 Input / output matching _____________________________________________________ 19
9.2 Bias resistor ______________________________________________________________ 19
9.3 Crystal __________________________________________________________________ 19
9.4 Voltage regulator __________________________________________________________ 19
9.5 Power supply decoupling and filtering _________________________________________ 19
10 IEEE 802.15.4 Modulation Format ____________________________________________ 24
11 Configuration Overview _____________________________________________________ 25
12 Evaluation Software ________________________________________________________ 26
13 4-wire Serial Configuration and Data Interface __________________________________ 27
13.1 Pin configuration __________________________________________________________ 27
13.2 Register access ____________________________________________________________ 27
13.3 Status byte _______________________________________________________________ 28
13.4 Command strobes _________________________________________________________ 29
13.5 RAM access ______________________________________________________________ 29
13.6 FIFO access ______________________________________________________________ 31
13.7 Multiple SPI access ________________________________________________________ 31
14 Microcontroller Interface and Pin Description ___________________________________ 32
14.1 Configuration interface _____________________________________________________ 32
14.2 Receive mode_____________________________________________________________ 33
14.3 RXFIFO overflow _________________________________________________________ 33
14.4 Transmit mode ____________________________________________________________ 34
14.5 General control and status pins _______________________________________________ 35
15 Demodulator, Symbol Synchroniser and Data Decision ___________________________ 35
16 Frame Format _____________________________________________________________ 36
16.1 Synchronisation header _____________________________________________________ 36
16.2 Length field ______________________________________________________________ 37
16.3 MAC protocol data unit _____________________________________________________ 37
16.4 Frame check sequence ______________________________________________________ 38

SWRS041c Page 2 of 85
Not Recommended For New Designs
CC2420
17 RF Data Buffering __________________________________________________________ 39
17.1 Buffered transmit mode _____________________________________________________ 39
17.2 Buffered receive mode ______________________________________________________ 39
17.3 Unbuffered, serial mode ____________________________________________________ 40
18 Address Recognition ________________________________________________________ 41
19 Acknowledge Frames _______________________________________________________ 41
20 Radio control state machine __________________________________________________ 43
21 MAC Security Operations (Encryption and Authentication) _______________________ 45
21.1 Keys ____________________________________________________________________ 45
21.2 Nonce / counter ___________________________________________________________ 45
21.3 Stand-alone encryption _____________________________________________________ 46
21.4 In-line security operations ___________________________________________________ 46
21.5 CTR mode encryption / decryption ____________________________________________ 47
21.6 CBC-MAC_______________________________________________________________ 47
21.7 CCM ___________________________________________________________________ 47
21.8 Timing __________________________________________________________________ 48
22 Linear IF and AGC Settings __________________________________________________ 48
23 RSSI / Energy Detection _____________________________________________________ 48
24 Link Quality Indication______________________________________________________ 49
25 Clear Channel Assessment ___________________________________________________ 50
26 Frequency and Channel Programming _________________________________________ 50
27 VCO and PLL Self-Calibration _______________________________________________ 51
27.1 VCO____________________________________________________________________ 51
27.2 PLL self-calibration ________________________________________________________ 51
28 Output Power Programming _________________________________________________ 51
29 Voltage Regulator __________________________________________________________ 51
30 Battery Monitor ____________________________________________________________ 52
31 Crystal Oscillator___________________________________________________________ 53
32 Input / Output Matching _____________________________________________________ 54
33 Transmitter Test Modes _____________________________________________________ 55
33.1 Unmodulated carrier _______________________________________________________ 55
33.2 Modulated spectrum _______________________________________________________ 56
34 System Considerations and Guidelines _________________________________________ 57
34.1 Frequency hopping and multi-channel systems ___________________________________ 57
34.2 Data burst transmissions ____________________________________________________ 57
34.3 Crystal accuracy and drift ___________________________________________________ 57
34.4 Communication robustness __________________________________________________ 57
34.5 Communication security ____________________________________________________ 57
34.6 Low-cost systems __________________________________________________________ 58
34.7 Battery operated systems ____________________________________________________ 58
34.8 BER / PER measurements ___________________________________________________ 58
35 PCB Layout Recommendations _______________________________________________ 59
36 Antenna Considerations _____________________________________________________ 59
37 Configuration Registers _____________________________________________________ 61
38 Test Output Signals _________________________________________________________ 81
39 Package Description (QLP 48) __________________________ Error! Bookmark not defined.
40 Recommended layout for package (QLP 48) ______________ Error! Bookmark not defined.

SWRS041c Page 3 of 85
Not Recommended For New Designs
CC2420
40.1 Package thermal properties __________________________ Error! Bookmark not defined.
40.2 Soldering information ______________________________________________________ 83
40.3 Plastic tube specification ____________________________ Error! Bookmark not defined.
40.4 Carrier tape and reel specification _____________________ Error! Bookmark not defined.
41 Ordering Information _________________________________ Error! Bookmark not defined.
42 General Information ________________________________________________________ 84
42.1 Document History _________________________________________________________ 84
42.2 Product Status Definitions ___________________________ Error! Bookmark not defined.
43 Address Information __________________________________ Error! Bookmark not defined.
44 TI Worldwide Technical Support _______________________ Error! Bookmark not defined.
Important Notice ___________________________________________ Error! Bookmark not defined.

SWRS041c Page 4 of 85
Not Recommended For New Designs
CC2420

1 Abbreviations

ADC - Analog to Digital Converter

AES - Advanced Encryption Standard
AGC - Automatic Gain Control
ARIB - Association of Radio Industries and Businesses
BER - Bit Error Rate
CBC-MAC - Cipher Block Chaining Message Authentication Code
CCA - Clear Channel Assessment
CCM - Counter mode + CBC-MAC
CFR - Code of Federal Regulations
CSMA-CA - Carrier Sense Multiple Access with Collision Avoidance
CTR - Counter mode (encryption)
CW - Continuous Wave
DAC - Digital to Analog Converter
DSSS - Direct Sequence Spread Spectrum
ESD - Electro Static Discharge
ESR - Equivalent Series Resistance
EVM - Error Vector Magnitude
FCC - Federal Communications Commission
FCF - Frame Control Field
FIFO - First In First Out
FFCTRL - FIFO and Frame Control
HSSD - High Speed Serial Debug
IEEE - Institute of Electrical and Electronics Engineers
IF - Intermediate Frequency
ISM - Industrial, Scientific and Medical
ITU-T - International Telecommunication Union – Telecommunication
Standardization Sector
I/O - Input / Output
I/Q - In-phase / Quadrature-phase
kbps - kilo bits per second
LNA - Low-Noise Amplifier
LO - Local Oscillator
LQI - Link Quality Indication
LSB - Least Significant Bit / Byte
MAC - Medium Access Control
MFR - MAC Footer
MHR - MAC Header
MIC - Message Integrity Code
MPDU - MAC Protocol Data Unit
MSDU - MAC Service Data Unit
NA - Not Available
NC - Not Connected
O-QPSK - Offset - Quadrature Phase Shift Keying
PA - Power Amplifier
PCB - Printed Circuit Board
PER - Packet Error Rate
PHY - Physical Layer
PHR - PHY Header
PLL - Phase Locked Loop
PSDU - PHY Service Data Unit
QLP - Quad Leadless Package
RAM - Random Access Memory
RBW - Resolution BandWidth
RF - Radio Frequency
RSSI - Receive Signal Strength Indicator

SWRS041c Page 5 of 85
Not Recommended For New Designs
CC2420
RX - Receive
SHR - Synchronisation Header
SPI - Serial Peripheral Interface
TBD - To Be Decided / To Be Defined
T/R - Transmit / Receive
TX - Transmit
VCO - Voltage Controlled Oscillator
VGA - Variable Gain Amplifier

2 References

[1] IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and
Physical Layer (PHY) specifications for Low Rate Wireless Personal Area
Networks (LR-WPANs)

http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf

[2] NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal
Information Processing Standards Publication 197, US Department of
Commerce/N.I.S.T., November 26, 2001. Available from the NIST website.

http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf

[3] R. Housley, D. Whiting, N. Ferguson, Counter with CBC-MAC (CCM),

submitted to NIST, June 3, 2002. Available from the NIST website.

http://csrc.nist.gov/CryptoToolkit/modes/proposedmodes/ProposedModesPag
e.html

SWRS041c Page 6 of 85
Not Recommended For New Designs
CC2420

3 Features

 2400 – 2483.5 MHz RF Transceiver  802.15.4 MAC hardware support:

 Direct Sequence Spread  Automatic preamble generator
Spectrum (DSSS) transceiver  Synchronisation word
 250 kbps data rate, 2 MChip/s insertion/detection
chip rate  CRC-16 computation and
 O-QPSK with half sine pulse checking over the MAC payload
shaping modulation  Clear Channel Assessment
 Very low current consumption  Energy detection / digital RSSI
(RX: 18.8 mA, TX: 17.4 mA)  Link Quality Indication
 High sensitivity (-95 dBm)  Full automatic MAC security (CTR,
 High adjacent channel rejection CBC-MAC, CCM)
(30/45 dB)
 High alternate channel rejection
(53/54 dB)  802.15.4 MAC hardware security:
 On-chip VCO, LNA and PA  Automated security operations
 Low supply voltage (2.1 – 3.6 V) within the receive and transmit
with on-chip voltage regulator FIFOs.
 Programmable output power  CTR mode encryption / decryption
 I/Q low-IF soft decision receiver  CBC-MAC authentication
 I/Q direct up-conversion  CCM encryption / decryption and
transmitter authentication
 Stand-alone AES encryption

 Separate transmit and receive FIFOs

 128 byte transmit data FIFO  Development tools available
 128 byte receive data FIFO  Fully equipped development kit
 Demonstration board reference
design with microcontroller code
 Very few external components  Easy-to-use software for
 Only reference crystal and a generating the CC2420 configu-
minimised number of passives ration data
 No external filters needed

 Small size QLP-48 package, 7 x 7 mm

 Easy configuration interface  Complies with EN 300 328, EN 300
 4-wire SPI interface 440 class 2, FCC CFR47 part 15 and
 Serial clock up to 10 MHz ARIB STD-T66

SWRS041c Page 7 of 85
Not Recommended For New Designs
CC2420

4 Absolute Maximum Ratings

Parameter Min. Max. Units Condition

Supply voltage for on-chip voltage regulator, -0.3 3.6 V

VREG_IN pin 43.

Supply voltage (VDDIO) for digital I/Os, DVDD3.3, -0.3 3.6 V

pin 25.
Supply voltage (VDD) on AVDD_VCO, DVDD1.8, −0.3 2.0 V
etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35,
37, 44 and 48)

Voltage on any digital I/O pin, (pin no. 21, 27-34 -0.3 VDDIO+0.3, max 3.6 V
and 41)
Voltage on any other pin, (pin no. 6, 7, 8, 11, 12, -0.3 VDD+0.3, max 2.0 V
13, 16, 36, 38, 39, 40, 45, 46 and 47)

Input RF level 10 dBm

Storage temperature range −50 150 C

Reflow solder temperature 260 C T = 10 s

The absolute maximum ratings given the limiting values may cause permanent
above should under no circumstances be damage to the device.
violated. Stress exceeding one or more of

Caution! ESD sensitive device.

Precaution should be used when handling
the device in order to prevent permanent
damage.

5 Operating Conditions

Parameter Min. Typ. Max. Units Condition

Supply voltage for on-chip voltage regulator, 2.1 3.6 V

VREG_IN pin 43.

Supply voltage (VDDIO) for digital I/Os, DVDD3.3, 1.6 3.6 V The digital I/O voltage (DVDD3.3 pin)
pin 25 . must match the external interfacing
circuit (e.g. microcontroller).

Supply voltage (VDD) on AVDD_VCO, DVDD1.8, 1.6 1.8 2.0 V The typical application uses regulated
etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35, 1.8 V supply generated by the on-chip
37, 44 and 48) voltage regulator.

Operating ambient temperature range, T A −40 85 C

SWRS041c Page 8 of 85
Not Recommended For New Designs
CC2420

6 Electrical Specifications
Measured on CC2420 EM with transmission line balun, T A = 25 C, DVDD3.3 and VREG_IN = 3.3 V, internal
voltage regulator used if nothing else stated.

6.1 Overall
Parameter Min. Typ. Max. Unit Condition / Note

RF Frequency Range 2400 2483.5 MHz Programmable in 1 MHz steps, 5

MHz steps for compliance with
[1]

6.2 Transmit Section

Parameter Min. Typ. Max. Unit Condition / Note

Transmit bit rate 250 250 kbps As defined by [1]

Transmit chip rate 2000 2000 kChips/s As defined by [1]

Nominal output power -3 0 dBm Delivered to a single ended 50 

load through a balun.
[1] requires minimum –3 dBm

Programmable output power range 24 dB The output power is

programmable in 8 steps from
approximately –24 to 0 dBm.

Harmonics
2nd harmonic -44 dBm Measured conducted with 1 MHz
rd resolution bandwidth on
3 harmonic -64 dBm spectrum analyser. At max output
power delivered to a single
ended 50  load through a balun.
See page 54.

Spurious emission Maximum output power.

30 - 1000 MHz -56 dBm Complies with EN 300 328, EN
1– 12.75 GHz -44 dBm 300 440, FCC CFR47 Part 15
1.8 – 1.9 GHz -56 dBm and ARIB STD-T-66
5.15 – 5.3 GHz -51 dBm

Error Vector Magnitude (EVM) 11 % Measured as defined by [1]

[1] requires max. 35 %

Optimum load impedance 95  Differential impedance as seen

+ j187 from the RF-port (RF_P and
RF_N) towards the antenna. For
matching details see the Input /
Output Matching section on page
54.

SWRS041c Page 9 of 85
Not Recommended For New Designs
CC2420
6.3 Receive Section
Parameter Min. Typ. Max. Unit Condition / Note

Receiver Sensitivity
-90 -95 dBm PER = 1%, as specified by [1]
Measured in a 50 single-ended
load through a balun.
[1] requires –85 dBm
Saturation (maximum input level) 0 10 dBm PER = 1%, as specified by [1]
Measured in a 50 single–ended
load through a balun.
[1] requires –20 dBm

Adjacent channel rejection Wanted signal @ -82 dBm,

adjacent modulated channel at
+ 5 MHz channel spacing 45 dB +5 MHz, PER = 1 %, as specified
by [1].
[1] requires 0 dB
Adjacent channel rejection Wanted signal @ -82 dBm,
adjacent modulated channel at
- 5 MHz channel spacing 30 dB -5 MHz, PER = 1 %, as specified
by [1].
[1] requires 0 dB

Alternate channel rejection Wanted signal @ -82 dBm,

adjacent modulated channel at
+ 10 MHz channel spacing 54 dB +10 MHz, PER = 1 %, as
specified by [1]
[1] requires 30 dB
Alternate channel rejection Wanted signal @ -82 dBm,
adjacent modulated channel at
- 10 MHz channel spacing 53 dB -10 MHz, PER = 1 %, as
specified by [1]
[1] requires 30 dB

Channel rejection Wanted signal @ -82 dBm.

Undesired signal is an IEEE
≥ + 15 MHz 62 dB 802.15.4 modulated channel,
≤ - 15 MHz 62 dB stepped through all channels
from 2405 to 2480 MHz. Signal
level for PER = 1%.

Co-channel rejection Wanted signal @ -82 dBm.

Undesired signal is an IEEE
-3 dB 802.15.4 modulated at the same
frequency as the desired signal.
Signal level for PER = 1%.

Blocking / Desensitisation
+/- 5 MHz from band edge -28 dBm Wanted signal 3 dB above the
+/- 20 MHz from band edge -28 dBm sensitivity level, CW jammer,
+/- 30 MHz from band edge -27 dBm PER = 1%. Complies with EN
+/- 50 MHz from band edge -28 dBm 300 440 class 2.

Spurious emission
30 – 1000 MHz -73 dBm Conducted measurement in a 50
1 – 12.75 GHz -58 dBm  single ended load. Measured
according to EN 300 328, EN
300 440 class 2, FCC CFR47,
Part 15 and ARIB STD-T-66

SWRS041c Page 10 of 85
Not Recommended For New Designs
CC2420
Parameter Min. Typ. Max. Unit Condition / Note

Frequency error tolerance -300 300 kHz Difference between centre

frequency of the received RF
signal and local oscillator
frequency
[1] requires 200 kHz
Symbol rate error tolerance 120 ppm Difference between incoming
symbol rate and the internally
generated symbol rate
[1] requires 80 ppm
Data latency 3 s Processing delay in receiver.
Time from complete transmission
of SFD until complete reception
of SFD, i.e. from SFD goes
active on transmitter until active
on receiver.

6.4 RSSI / Carrier Sense

Parameter Min. Typ. Max. Unit Condition / Note

Carrier sense level − 77 dBm Programmable in

RSSI.CCA_THR

RSSI dynamic range 100 dB The range is approximately from

–100 dBm to 0 dBm

RSSI accuracy 6 dB See page 48 for details

RSSI linearity 3 dB

RSSI average time 128 s 8 symbol periods, as specified by

[1]

6.5 IF Section
Parameter Min. Typ. Max. Unit Condition / Note

Intermediate frequency (IF) 2 MHz

6.6 Frequency Synthesizer Section

Parameter Min. Typ. Max. Unit Condition / Note

Crystal oscillator frequency 16 MHz See page 53 for details.

Crystal frequency accuracy - 40 40 ppm Including aging and temperature

requirement dependency, as specified by [1]

Crystal operation Parallel C381 and C391 are loading

capacitors, see page 53

SWRS041c Page 11 of 85
Not Recommended For New Designs
CC2420
Parameter Min. Typ. Max. Unit Condition / Note

Crystal load capacitance 12 16 20 pF 16 pF recommended

Crystal ESR 60 

Crystal oscillator start-up time 1.0 ms 16 pF load

Phase noise Unmodulated carrier

−109 dBc/Hz At ±1 MHz offset from carrier
−117 dBc/Hz At ±2 MHz offset from carrier
−117 dBc/Hz At ±3 MHz offset from carrier
−117 dBc/Hz At ±5 MHz offset from carrier

PLL loop bandwidth 100 kHz

PLL lock time 192 s The startup time from the crystal
oscillator is running and RX / TX
turnaround time

6.7 Digital Inputs/Outputs

Parameter Min. Typ. Max. Unit Condition / Note

General Signal levels are referred to the

voltage level at pin DVDD3.3

Logic "0" input voltage 0 0.3* V

DVDD

Logic "1" input voltage 0.7* DVDD V

DVDD

Logic "0" output voltage 0 0.4 V Output current −8 mA,

3.3 V supply voltage

Logic "1" output voltage 2.5 VDD V Output current 8 mA,

3.3 V supply voltage

Logic "0" input current NA −1 A Input signal equals GND

Logic "1" input current NA 1 A Input signal equals VDD

FIFO setup time 20 ns TX unbuffered mode, minimum

time FIFO must be ready before
the positive edge of FIFOP
FIFO hold time 10 ns TX unbuffered mode, minimum
time FIFO must be held after the
positive edge of FIFOP

Serial interface pins (SCLK, SI, SO See Table 4 on page 28

and CSn) timing specification

SWRS041c Page 12 of 85
Not Recommended For New Designs
CC2420

6.8 Voltage Regulator

Parameter Min. Typ. Max. Unit Condition / Note

General Note that the internal voltage

regulator can only supply
CC2420 and no external circuitry.

Input Voltage 2.1 3.0 3.6 V On the VREG_IN pin

Output Voltage 1.7 1.8 1.9 V On the VREG_OUT pin

Quiescent current 13 20 29 A No current drawn from the

VREG_OUT pin. Min and max
numbers include 2.1 through 3.6
V input voltage

Start-up time 0.3 0.6 ms

6.9 Battery Monitor

Parameter Min. Typ. Max. Unit Condition / Note

Current consumption 6 30 90 A When enabled

Start-up time 100 s Voltage regulator already

enabled

Settling time 2 s New toggle voltage programmed

Step size 50 mV

Hysteresis 10 mV

Absolute accuracy -80 80 mV May be software calibrated for

known reference voltage

Relative accuracy -50 50 mV

6.10 Power Supply

Parameter Min. Typ. Max. Unit Condition / Note

Current consumption in different Current drawn from VREG_IN,

modes (see Figure 25, page 44) through voltage regulator
Voltage regulator off (OFF) 0.02 1 A Voltage regulator off
Power Down mode (PD) 20 A Voltage regulator on
Idle mode (IDLE) 426 A Including crystal oscillator and
voltage regulator
Current Consumption, 18.8 mA
receive mode

SWRS041c Page 13 of 85
Not Recommended For New Designs
CC2420
Parameter Min. Typ. Max. Unit Condition / Note

Current Consumption,
transmit mode:
P = -25 dBm 8.5 mA The output power is delivered
P = -15 dBm 9.9 mA differentially to a 50  singled
P = -10 dBm 11 mA ended load through a balun, see
P = −5 dBm 14 mA also page 54.
P = 0 dBm 17.4 mA

SWRS041c Page 14 of 85
Not Recommended For New Designs
CC2420

7 Pin Assignment

AVDD_XOSC16
XOSC16_Q1

XOSC16_Q2
VREG_OUT
AVDD_CHP

VREG_EN
AVDD_IF1

VREG_IN
ATEST1

ATEST2

R_BIAS

NC

37
48

47

46

45

44

43

42

41

40

39

38
VCO_GUARD 1 36 NC

AVDD_VCO 2 35 DVDD_RAM

AVDD_PRE 3 34 SO

AVDD_RF1 4 33 SI

GND 5 32 SCLK

RF_P

TXRX_SWITCH
6

7 CC2420 QLP48
7x7
31

30
CSn

FIFO

RF_N 8 29 FIFOP

GND 9 28 CCA

AVDD_SW 10 27 SFD

NC 11 26 DVDD1.8

NC 12 25 DVDD3.3
13

24
14

18

20

21

22

23
15

16

17

19
NC

DVDD_ADC

DGND_GUARD

DGND

DSUB_PADS

DSUB_CORE
AVDD_ADC

DGUARD
AVDD_IF2

RESETn
AVDD_RF2

NC

AGND
Exposed die
attach pad

Figure 1. CC2420 Pinout – Top View

Pin Pin Name Pin type Pin Description

- AGND Ground (analog) Exposed die attach pad. Must be connected to solid ground
plane
1 VCO_GUARD Power (analog) Connection of guard ring for VCO (to AVDD) shielding
2 AVDD_VCO Power (analog) 1.8 V Power supply for VCO
3 AVDD_PRE Power (analog) 1.8 V Power supply for Prescaler
4 AVDD_RF1 Power (analog) 1.8 V Power supply for RF front-end
5 GND Ground (analog) Grounded pin for RF shielding
6 RF_P RF I/O Positive RF input/output signal to LNA/from PA in
receive/transmit mode
7 TXRX_SWITCH Power (analog) Common supply connection for integrated RF front-end. Must
be connected to RF_P and RF_N externally through a DC
path
8 RF_N RF I/O Negative RF input/output signal to LNA/from PA in
receive/transmit mode
9 GND Ground (analog) Grounded pin for RF shielding
10 AVDD_SW Power (analog) 1.8 V Power supply for LNA / PA switch
11 NC - Not Connected
12 NC - Not Connected
13 NC - Not Connected
14 AVDD_RF2 Power (analog) 1.8 V Power supply for receive and transmit mixers

SWRS041c Page 15 of 85
Not Recommended For New Designs
CC2420
Pin Pin Name Pin type Pin Description
15 AVDD_IF2 Power (analog) 1.8 V Power supply for transmit / receive IF chain
16 NC - Not Connected
17 AVDD_ADC Power (analog) 1.8 V Power supply for analog parts of ADCs and DACs
18 DVDD_ADC Power (digital) 1.8 V Power supply for digital parts of receive ADCs
19 DGND_GUARD Ground (digital) Ground connection for digital noise isolation
20 DGUARD Power (digital) 1.8 V Power supply connection for digital noise isolation
21 RESETn Digital Input Asynchronous, active low digital reset
22 DGND Ground (digital) Ground connection for digital core and pads
23 DSUB_PADS Ground (digital) Substrate connection for digital pads
24 DSUB_CORE Ground (digital) Substrate connection for digital modules
25 DVDD3.3 Power (digital) 3.3 V Power supply for digital I/Os
26 DVDD1.8 Power (digital) 1.8 V Power supply for digital core
27 SFD Digital output SFD (Start of Frame Delimiter) / digital mux output
28 CCA Digital output CCA (Clear Channel Assessment) / digital mux output
29 FIFOP Digital output Active when number of bytes in FIFO exceeds threshold /
serial RF clock output in test mode
30 FIFO Digital I/O Active when data in FIFO /
serial RF data input / output in test mode
31 CSn Digital input SPI Chip select, active low
32 SCLK Digital input SPI Clock input, up to 10 MHz
33 SI Digital input SPI Slave Input. Sampled on the positive edge of SCLK
34 SO Digital output SPI Slave Output. Updated on the negative edge of SCLK.
(tristate) Tristate when CSn high.
35 DVDD_RAM Power (digital) 1.8 V Power supply for digital RAM
36 NC - Not Connected
37 AVDD_XOSC16 Power (analog) 1.8 V crystal oscillator power supply
38 XOSC16_Q2 Analog I/O 16 MHz Crystal oscillator pin 2
39 XOSC16_Q1 Analog I/O 16 MHz Crystal oscillator pin 1 or external clock input
40 NC - Not Connected
41 VREG_EN Digital input Voltage regulator enable, active high, held at VREG_IN
voltage level when active. Note that VREG_EN is relative
VREG_IN, not DVDD3.3.
42 VREG_OUT Power output Voltage regulator 1.8 V power supply output
43 VREG_IN Power (analog) Voltage regulator 2.1 to 3.6 V power supply input
44 AVDD_IF1 Power (analog) 1.8 V Power supply for transmit / receive IF chain
45 R_BIAS Analog output External precision resistor, 43 k,  1 %
46 ATEST2 Analog I/O Analog test I/O for prototype and production testing
47 ATEST1 Analog I/O Analog test I/O for prototype and production testing
48 AVDD_CHP Power (analog) 1.8 V Power supply for phase detector and charge pump

NOTES:
The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the
chip.

SWRS041c Page 16 of 85
Not Recommended For New Designs
CC2420

8 Circuit Description

AUTOMATIC GAIN CONTROL

DIGITAL
ADC DEMODULATOR

- Digital RSSI Serial

- Gain Control
LNA - Image Suppression voltage
- Channel Filtering regulator
- Demodulation
- Frame
ADC synchronization

TX/RX CONTROL

CONTROL LOGIC
SmartRF 

microcontroller
DIGITAL
INTERFACE

interface
0 FREQ

CC2420

Serial
WITH FIFO
90 SYNTH BUFFERS,
CRC AND
ENCRYPTION

TX POWER CONTROL

DAC DIGITAL
Power MODULATOR
Control Digital and
PA  - Data spreading
- Modulation
Analog test
interface

XOSC DAC
On-chip
BIAS

16 MHz

Figure 2. CC2420 simplified block diagram

A simplified block diagram of CC2420 is The CC2420 transmitter is based on direct
shown in Figure 2. up-conversion. The data is buffered in a
128 byte transmit FIFO (separate from the
CC2420 features a low-IF receiver. The receive FIFO). The preamble and start of
received RF signal is amplified by the low- frame delimiter are generated by
noise amplifier (LNA) and down-converted hardware. Each symbol (4 bits) is spread
in quadrature (I and Q) to the intermediate using the IEEE 802.15.4 spreading
frequency (IF). At IF (2 MHz), the complex sequence to 32 chips and output to the
I/Q signal is filtered and amplified, and digital-to-analog converters (DACs).
then digitized by the ADCs. Automatic
gain control, final channel filtering, de- An analog low pass filter passes the signal
spreading, symbol correlation and byte to the quadrature (I and Q) upconversion
synchronisation are performed digitally. mixers. The RF signal is amplified in the
power amplifier (PA) and fed to the
When the SFD pin goes active, this antenna.
indicates that a start of frame delimiter has
been detected. CC2420 buffers the The internal T/R switch circuitry makes the
received data in a 128 byte receive FIFO. antenna interface and matching easy. The
The user may read the FIFO through an RF connection is differential. A balun may
SPI interface. CRC is verified in hardware. be used for single-ended antennas. The
RSSI and correlation values are appended biasing of the PA and LNA is done by
to the frame. CCA is available on a pin in connecting TXRX_SWITCH to RF_P and
receive mode. Serial (unbuffered) data RF_N through an external DC path.
modes are also available for test
purposes. The frequency synthesizer includes a
completely on-chip LC VCO and a 90

SWRS041c Page 17 of 85
Not Recommended For New Designs
CC2420
degrees phase splitter for generating the I The digital baseband includes support for
and Q LO signals to the down-conversion frame handling, address recognition, data
mixers in receive mode and up-conversion buffering and MAC security.
mixers in transmit mode. The VCO
operates in the frequency range 4800 – The 4-wire SPI serial interface is used for
4966 MHz, and the frequency is divided by configuration and data buffering.
two when split in I and Q.
An on-chip voltage regulator delivers the
A crystal must be connected to regulated 1.8 V supply voltage. The
XOSC16_Q1 and XOSC16_Q2 and voltage regulator may be enabled /
provides the reference frequency for the disabled through a separate pin.
synthesizer. A digital lock signal is
available from the PLL. A battery monitor may optionally be used
to monitor the unregulated power supply
voltage. The battery monitor is
configurable through the SPI interface.

SWRS041c Page 18 of 85
Not Recommended For New Designs
CC2420

9 Application Circuit

Few external components are required for If a balanced antenna such as a folded
the operation of CC2420. A typical dipole is used, the balun can be omitted. If
application circuit is shown in Figure 4. the antenna also provides a DC path from
The external components shown are the TXRX_SWITCH pin to the RF pins,
described in Table 1 and typical values are inductors are not needed for DC bias.
given in Table 2. Note that most
decoupling capacitors are not shown on Figure 5 shows a suggested application
the application circuits. For the complete circuit using a differential antenna. The
reference design please refer to Texas antenna type is a standard folded dipole.
Instrument’s web site: http://www.ti.com. The dipole has a virtual ground point;
hence bias is provided without degradation
in antenna performance.
9.1 Input / output matching
The RF input/output is high impedance
9.2 Bias resistor
and differential. The optimum differential
load for the RF port is 95+j187 . The bias resistor R451 is used to set an
accurate bias current.
When using an unbalanced antenna such
as a monopole, a balun should be used in
9.3 Crystal
order to optimise performance. The balun
can be implemented using low-cost An external crystal with two loading
discrete inductors and capacitors only or in capacitors (C381 and C391) is used for
combination with transmission lines. the crystal oscillator. See page 53 for
details.
Figure 3 shows the balun implemented in a
two-layer reference design. It consists of a
half wave transmission line, C81, L61, L71 9.4 Voltage regulator
and L81. The circuit will present the The on chip voltage regulator supplies all
optimum RF termination to CC2420 with a 1.8 V power supply inputs. C42 is required
50  load on the antenna connection. This for stability of the regulator. A series
circuit has improved EVM performance, resistor may be used to comply with the
sensitivity and harmonic suppression ESR requirement.
compared to the design in Figure 4.
Please refer to the input/output matching
9.5 Power supply decoupling and
section on page 54 for more details.
filtering
The balun in Figure 4 consists of C61, Proper power supply decoupling must be
C62, C71, C81, L61, L62 and L81, and will used for optimum performance. The
present the optimum RF termination to placement and size of the decoupling
CC2420 with a 50  load on the antenna capacitors and the power supply filtering
connection. A low pass filter may be added are very important to achieve the best
to add margin to the FCC requirement on performance in an application. Texas
second harmonic level. Instruments provides a compact reference
design that should be followed very
closely..

SWRS041c Page 19 of 85
Not Recommended For New Designs
CC2420
Ref Description

C42 Voltage regulator load capacitance

C61 Balun and match

C62 DC block to antenna and match

C71 Front-end bias decoupling and match

C81 Balun and match

C381 16MHz crystal load capacitor, see page 53

C391 16MHz crystal load capacitor, see page 53

L61 DC bias and match

L62 DC bias and match

L71 DC bias and match
L81 Balun and match

R451 Precision resistor for current reference generator

XTAL 16MHz crystal, see page 53

Table 1. Overview of external components

3.3 V
Power
supply
C391 C381

C42
R451
XTAL
AVDD_XOSC16 37
AVDD_CHP 48

ATEST1 47

ATEST2 46

R_BIAS 45

AVDD_IF1 44

VREG_IN 43

VREG_OUT 42

VREG_EN 41

NC 40

XOSC16_Q1 39

XOSC16_Q2 38

1 VCO_GUARD NC 36

2 AVDD_VCO DVDD_RAM 35

Antenna 3 AVDD_PRE SO 34
(50 Ohm) 4 AVDD_RF1 SI 33
 
5 GND
CC2420 SCLK 32

L71 6 RF_P QLP48 CSn 31

C81 L81
L61 RF
7x7
7 TXRX_SWITCH FIFO 30
Transceiver
Digital Interface

8 RF_N FIFOP 29

9 GND CCA 28

10 AVDD_SW SFD 27

11 NC DVDD1.8 26
DGND_GUARD 19

DSUB_PADS 23

DSUB_CORE 24
AVDD_RF2 14

AVDD_IF2 15

AVDD_ADC 17

DVDD_ADC 18

12 NC DVDD3.3 25
RESETn 21
DGUARD 20

DGND 22
NC 13

NC 16

Figure 3. Typical application circuit with transmission line balun for single-ended
operation

SWRS041c Page 20 of 85
Not Recommended For New Designs
CC2420
3.3 V
Power
supply

C391 C381
R451
C42 XTAL

AVDD_XOSC16 37
AVDD_CHP 48

ATEST1 47

ATEST2 46

R_BIAS 45

AVDD_IF1 44

VREG_IN 43

VREG_OUT 42

VREG_EN 41

NC 40

XOSC16_Q1 39

XOSC16_Q2 38
1 VCO_GUARD NC 36

2 AVDD_VCO DVDD_RAM 35

3 AVDD_PRE SO 34
Antenna
(50 Ohm) 4 AVDD_RF1 SI 33
C61
5 GND
CC2420 SCLK 32

L62 6 RF_P QLP48 CSn 31

C62 C71 L61 RF
7x7
7 TXRX_SWITCH FIFO 30
Transceiver

Digital Interface
8 RF_N FIFOP 29

L81 9 GND CCA 28

10 AVDD_SW SFD 27
C81
11 NC DVDD1.8 26
DGND_GUARD 19

DSUB_PADS 23

DSUB_CORE 24
AVDD_RF2 14

AVDD_IF2 15

AVDD_ADC 17

DVDD_ADC 18

12 NC DVDD3.3 25
RESETn 21
DGUARD 20

DGND 22
NC 13

NC 16

Figure 4. Typical application circuit with discrete balun for single-ended operation

SWRS041c Page 21 of 85
Not Recommended For New Designs
CC2420
3.3 V
Power
supply

C391 C381
R451
C42 XTAL

AVDD_XOSC16 37
AVDD_CHP 48

ATEST1 47

ATEST2 46

R_BIAS 45

AVDD_IF1 44

VREG_IN 43

VREG_OUT 42

VREG_EN 41

NC 40

XOSC16_Q1 39

XOSC16_Q2 38
1 VCO_GUARD NC 36

2 AVDD_VCO DVDD_RAM 35

3 AVDD_PRE SO 34

4 AVDD_RF1 SI 33

5 GND
CC2420 SCLK 32

6 RF_P QLP48 CSn 31

Folded L61 RF
7x7
dipole 7 TXRX_SWITCH FIFO 30
antenna L71 Transceiver

Digital Interface
8 RF_N FIFOP 29

9 GND CCA 28

10 AVDD_SW SFD 27

11 NC DVDD1.8 26
DGND_GUARD 19

DSUB_PADS 23

DSUB_CORE 24
AVDD_RF2 14

AVDD_IF2 15

AVDD_ADC 17

DVDD_ADC 18

12 NC DVDD3.3 25
RESETn 21
DGUARD 20

DGND 22
NC 13

NC 16

Figure 5. Suggested application circuit with differential antenna (folded dipole)

SWRS041c Page 22 of 85
Not Recommended For New Designs
CC2420

Item Single ended output, Single ended output, Differential antenna

transmission line balun discrete balun

C42 10 μF, 0.5 < ESR < 5 10 μF, 0.5 < ESR < 5 10 μF, 0.5 < ESR < 5
C61 Not used 0.5 pF, +/- 0.25pF, NP0, 0402 Not used

C62 Not used 5.6 pF, +/- 0.25pF, NP0, 0402 Not used

C71 Not used 5.6 pF, 10%, X5R, 0402 Not used

C81 5.6 pF, +/- 0.25pF, NP0, 0402 0.5 pF, +/- 0.25pF, NP0, 0402 Not used

C381 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402
C391 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402

L61 8.2 nH, 5%, 7.5 nH, 5%, 27 nH, 5%, Monolithic/multilayer,
Monolithic/multilayer, 0402 Monolithic/multilayer, 0402 0402
L62 Not used 5.6 nH, 5%, Not used
Monolithic/multilayer, 0402
L71 22 nH, 5%, Not used 12 nH, 5%, Monolithic/multilayer,
Monolithic/multilayer, 0402 0402

L81 1.8 nH, +/- 0.3nH, 7.5 nH, 5%, Not used
Monolithic/multilayer, 0402 Monolithic/multilayer, 0402
R451 43 k, 1%, 0402 43 k, 1%, 0402 43 k, 1%, 0402
XTAL 16 MHz crystal, 16 pF load 16 MHz crystal, 16 pF load 16 MHz crystal, 16 pF load (CL),
(CL), (CL), ESR < 60 
ESR < 60  ESR < 60 
Table 2. Bill of materials for the application circuits

SWRS041c Page 23 of 85
Not Recommended For New Designs
CC2420

10 IEEE 802.15.4 Modulation Format

This section is meant as an introduction to least significant byte is transmitted first,

the 2.4 GHz direct sequence spread except for security related fields where the
spectrum (DSSS) RF modulation format most significant byte it transmitted first.
defined in IEEE 802.15.4. For a complete
description, please refer to [1]. Each symbol is mapped to one out of 16
pseudo-random sequences, 32 chips
The modulation and spreading functions each. The symbol to chip mapping is
are illustrated at block level in Figure 6 [1]. shown in Table 3. The chip sequence is
Each byte is divided into two symbols, 4 then transmitted at 2 MChips/s, with the
bits each. The least significant symbol is least significant chip (C0) transmitted first
transmitted first. For multi-byte fields, the for each symbol.

Transmitted
Bit-to- Symbol- O-QPSK Modulated
bit-stream
Symbol to-Chip Modulator Signal
(LSB first)

Figure 6. Modulation and spreading functions [1]

Symbol Chip sequence (C0, C1, C2, … , C31)

0 11011001110000110101001000101110
1 11101101100111000011010100100010
2 00101110110110011100001101010010
3 00100010111011011001110000110101
4 01010010001011101101100111000011
5 00110101001000101110110110011100
6 11000011010100100010111011011001
7 10011100001101010010001011101101
8 10001100100101100000011101111011
9 10111000110010010110000001110111
10 01111011100011001001011000000111
11 01110111101110001100100101100000
12 00000111011110111000110010010110
13 01100000011101111011100011001001
14 10010110000001110111101110001100
15 11001001011000000111011110111000
Table 3. IEEE 802.15.4 symbol-to-chip mapping [1]
The modulation format is Offset – is shaped as a half-sine, transmitted
Quadrature Phase Shift Keying (O-QPSK) alternately in the I and Q channels with
with half-sine chip shaping. This is one half chip period offset. This is
equivalent to MSK modulation. Each chip illustrated for the zero-symbol in Figure 7.

SWRS041c Page 24 of 85
Not Recommended For New Designs
CC2420
TC

I-phase 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1

Q-phase 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 0

2TC

Figure 7. I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 μs

11 Configuration Overview

CC2420 can be configured to achieve the  Power-down / power-up mode

best performance for different applications.  Crystal oscillator power-up / power
Through the programmable configuration down
registers the following key parameters can  Clear Channel Assessment mode
be programmed:  Packet handling hardware support
 Encryption / Authentication modes
 Receive / transmit mode
 RF channel selection
 RF output power

SWRS041c Page 25 of 85
Not Recommended For New Designs
CC2420

12 Evaluation Software

Texas Instruments (TI) provides users of Studio can be downloaded from TI’s web
CC2420 with a software program, page: http://www.ti.com. Figure 8 shows
the user interface of the CC2420
®
SmartRF Studio (Windows interface)
which may be used for radio performance configuration software.
and functionality evaluation. SmartRF®

Figure 8. SmartRF Studio user interface

SWRS041c Page 26 of 85
Not Recommended For New Designs
CC2420

13 4-wire Serial Configuration and Data Interface

CC2420 is configured via a simple 4-wire RAM/Register bit (set to 0 for register
SPI-compatible interface (pins SI, SO, access), followed by the R/W bit (0 for
SCLK and CSn) where CC2420 is the slave. write, 1 for read). The following 6 bits are
This interface is also used to read and the address-bits (A5:0). A5 is the most
write buffered data (see page 39). All significant bit of the address and is sent
address and data transfer on the SPI first. The 16 data-bits are then transferred
interface is done most significant bit first. (D15:0), also MSB first. See Figure 9 for
an illustration.

13.1 Pin configuration The configuration registers can also be

The digital inputs SCLK, SI and CSn are read by the microcontroller via the same
high-impedance inputs (no internal pull-up) configuration interface. The R/W bit must
and should have external pull-ups if not be set high to initiate the data read-back.
driven. SO is high-impedance when CSn is CC2420 then returns the data from the
high. An external pull-up should be used at addressed register on the 16 clock cycles
SO to prevent floating input at following the register address. The SO pin
microcontroller. Unused I/O pins on the is used as the data output and must be
MCU can be set to outputs with a fixed ‘0’ configured as an input by the
level to avoid leakage currents. microcontroller.

The timing for the programming is also

13.2 Register access shown in Figure 9 with reference to Table
There are 33 16-bit configuration and 4. The clocking of the data on SI into the
status registers, 15 command strobe CC2420 is done on the positive edge of
registers, and two 8-bit registers to access SCLK. When the last bit, D0, of the 16
the separate transmit and receive FIFOs. data-bits has been written, the data word
Each of the 50 registers is addressed by a is loaded in the internal configuration
6-bit address. The RAM/Register bit (bit 7) register.
must be cleared for register access. The
Read/Write bit (bit 6) selects a read or a Multiple registers may be written without
write operation and makes up the 8-bit releasing CSn, as described in the Multiple
address field together with the 6-bit SPI access section on page 31.
address.
The register data will be retained during
In each register read or write cycle, 24 bits power down mode, but not when the
are sent on the SI-line. The CSn pin (Chip power-supply is turned off (e.g. by
Select, active low) must be kept low during disabling the voltage regulator using the
this transfer. The bit to be sent first is the VREG_EN pin). The registers can be
programmed in any order.

SWRS041c Page 27 of 85
Not Recommended For New Designs
CC2420
tsp tch tcl tsd thd tns

SCLK

CSn
Write to register / RXFIFO:

SI 0 0 A5 A4 A3 A2 A1 A0 X DW15 DW14 DW13 DW12 DW11 DW10 DW9 DW8 X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X

S7 S6 S5 S4 S3 S2 S1 S0 X
SO
Write to TXFIFO:

SI 0 0 A5 A4 A3 A2 A1 A0 X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X

S7 S6 S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7
SO

Read from register / RXFIFO:

SI 0 1 A5 A4 A3 A2 A1 A0 X

SO S7 S6 S5 S4 S3 S2 S1 S0 DR15 DR14 DR13 DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 DR15

Read and write one byte to RAM: (multiple read / writes also possible)

SI 1 A6 A5 A4 A3 A2 A1 A0 X B1 B0 0 X X X X X X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X

SO S7 S6 S5 S4 S3 S2 S1 S0 X DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 DR7

Read one byte from RAM: (multiple reads also possible)

SI 1 A6 A5 A4 A3 A2 A1 A0 X B1 B0 1 X X X X X X

SO S7 S6 S5 S4 S3 S2 S1 S0 X DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 DR7

Figure 9. SPI timing diagram

Parameter Symbol Min Max Units Conditions

SCLK, clock FSCLK 10 MHz

frequency

SCLK low tcl 25 ns The minimum time SCLK must be low.

pulse
duration
SCLK high tch 25 ns The minimum time SCLK must be high.
pulse
duration

CSn setup tsp 25 ns The minimum time CSn must be low before the
time first positive edge of SCLK.

CSn hold time tns 25 ns The minimum time CSn must be held low after the
last negative edge of SCLK.

SI setup time tsd 25 ns The minimum time data on SI must be ready

before the positive edge of SCLK.

SI hold time thd 25 ns The minimum time data must be held at SI, after
the positive edge of SCLK.

Rise time trise 100 ns The maximum rise time for SCLK and CSn

Fall time tfall 100 ns The maximum fall time for SCLK and CSn

Note: The set-up- and hold-times refer to 50% of VDD.

Table 4. SPI timing specification

pin. The status byte contains 6 status bits

13.3 Status byte
which are described in Table 5.
During transfer of the register access byte,
command strobes, the first RAM address Issuing a SNOP (no operation) command
byte and data transfer to the TXFIFO, the strobe may be used to read the status
CC2420 status byte is returned on the SO byte. It may also be read during access to

SWRS041c Page 28 of 85
Not Recommended For New Designs
CC2420
chip functions such as register or FIFO access.

Bit # Name Description

7 - Reserved, ignore value
6 XOSC16M_STABLE Indicates whether the 16 MHz oscillator is running or not
0 : The 16 MHz crystal oscillator is not running
1 : The 16 MHz crystal oscillator is running
5 TX_UNDERFLOW Indicates whether an FIFO underflow has occurred during
transmission. Must be cleared manually with a SFLUSHTX
command strobe.
0 : No underflow has occurred
1 : An underflow has occurred
4 ENC_BUSY Indicates whether the encryption module is busy
0 : Encryption module is idle
1 : Encryption module is busy
3 TX_ACTIVE Indicates whether RF transmission is active
0 : RF Transmission is idle
1 : RF Transmission is active
2 LOCK Indicates whether the frequency synthesizer PLL is in lock or not
0 : The PLL is out of lock
1 : The PLL is in lock
1 RSSI_VALID Indicates whether the RSSI value is valid or not.
0 : The RSSI value is not valid
1 : The RSSI value is valid, always true when reception has been
enabled at least 8 symbol periods (128 us)
0 - Reserved, ignore value
Table 5. Status byte returned during address transfer and TXFIFO writing

R/W bit (set to 0) and the 6 address bits

13.4 Command strobes
(in the range 0x00 through 0x0E) are
Command strobes may be viewed as written. A command strobe may be
single byte instructions to CC2420. By followed by any other SPI access without
addressing a command strobe register pulling CSn high, and is executed on the
internal sequences will be started. These last falling edge on SCLK.
commands must be used to enable the
crystal oscillator, enable receive mode,
13.5 RAM access
start decryption etc. All 15 command
strobes are listed in Table 11 on page 62. The internal 368 byte RAM may be
accessed through the SPI interface. Single
When the crystal oscillator is disabled or multiple bytes may be read or written
(Power Down state in Figure 25 on page sending the address part (2 bytes) only
44), only the SXOSCON command strobe once. The address is then automatically
may be used. All other command strobes incremented by the CC2420 hardware for
will be ignored and will have no effect. The each new byte. Data is read and written
crystal oscillator must stabilise (see the one byte at a time, unlike register access
XOSC16M_STABLE status bit in Table 5) where 2 bytes are always required after
before other command strobes are each address byte.
accepted.
The crystal oscillator must be running
The command strobe register is accessed when accessing the RAM.
in the same way as for a register write
operation, but no data is transferred. That The RAM/Register bit must be set high to
is, only the RAM/Register bit (set to 0), enable RAM access. The 9 bit RAM

SWRS041c Page 29 of 85
Not Recommended For New Designs
CC2420
address consists of two parts, B1:0 (MSB) For RAM read, the selected byte(s) are
selecting one of the three memory banks output on the SO pin directly after the
and A6:0 (LSB) selecting the address second address byte.
within the selected bank. The RAM is
divided into three memory banks: TXFIFO See Figure 10 for an illustration on how
(bank 0), RXFIFO (bank 1) and security multiple RAM bytes may be read or written
(bank 2). The FIFO banks are 128 bytes in one operation.
each, while the security bank is 112 bytes.
The RAM memory space is shown in
A6:0 is transmitted directly after the Table 6. The lower 256 bytes are used to
RAM/Register bit as shown in Figure 9. store FIFO data. Note that RAM access
For RAM access, a second byte is also should never be used for FIFO write
required before the data transfer. This byte operations because the FIFO counter will
contains B1:0 in bits 7 and 6, followed by not be updated. Use RXFIFO and TXFIFO
the R/W bit (0 for read+write, 1 for read). access instead as described in section
Bits 4 through 0 are don’t care as shown in FIFO access.
Figure 9.
As with register data, data stored in RAM
For RAM write, data to be written must be will be retained during power down mode,
input on the SI pin directly after the but not when the power-supply is turned
second address byte. RAM data read is off (e.g. by disabling the voltage regulator
output on the SO pin simultaneously, but using the VREG_EN pin).
may be ignored by the user if only writing
is of interest.

CSn:

Command strobe: ADDR

Multiple command strobes: ADDR ADDR ADDR ... ... ADDR ADDR

Read or write a whole register (16 bit): ADDR DATA8MSB DATA8LSB

Read 8 MSB of a register: ADDR DATA8MSB

Multiple register read or write ADDR DATA8MSB DATA8LSB ADDR DATA8MSB ... ADDR DATA8MSB DATA8LSB

Read or write n bytes from/to RF FIFO: ADDRFIFO DATAbyte0 DATAbyte1 DATAbyte2 DATAbyte3 ... DATAbyte n-3 DATAbyte n-2 DATAbyte n-1

Read or write n bytes from/to RAM: ADDRLRAM ADDRHRAM DATAADDR DATAADDR+1 DATAADDR+2 ... DATAADDR+n

Note: FIFO and RAM access must be terminated with setting the CSn pin high.
Command strobes and register access may be followed by any other access,
since they are completed on the last negative edge on SCLK. They may however also be
terminated with setting CSn high, if desirable, e.g. for reading only 8 bits from a configuration
register.

Figure 10. Configuration registers write and read operations via SPI

SWRS041c Page 30 of 85
Not Recommended For New Designs
CC2420
Address Byte Ordering Name Description

0x16F – - - Not used

0x16C
0x16B – MSB SHORTADR 16-bit Short address, used for address recognition.
0x16A LSB
0x169 – MSB PANID 16-bit PAN identifier, used for address recognition.
0x168 LSB
0x167 – MSB IEEEADR 64-bit IEEE address of current node, used for address
0x160 LSB recognition.
0x15F – MSB CBCSTATE Temporary storage for CBC-MAC calculations
0x150 LSB
0x14F – MSB (Flags) TXNONCE / TXCTR Transmitter nonce for in-line authentication and
0x140 LSB transmitter counter for in-line encryption.
0x13F – MSB KEY1 Encryption key 1
0x130 LSB
0x12F – MSB SABUF Stand-alone encryption buffer, for plaintext input and
0x120 LSB ciphertext output
0x11F – MSB (Flags) RXNONCE / RXCTR Receiver nonce for in-line authentication or
0x110 LSB receiver counter for in-line decryption.
0x10F – MSB KEY0 Encryption key 0
0x100 LSB
0x0FF – MSB RXFIFO 128 bytes receive FIFO
0x080 LSB
0x07F – MSB TXFIFO 128 bytes transmit FIFO
0x000 LSB
Table 6. CC2420 RAM Memory Space

FIFO access can only be terminated by

13.6 FIFO access
setting the CSn pin high once it has been
The TXFIFO and RXFIFO may be started.
accessed through the TXFIFO (0x3E) and
RXFIFO (0x3F) registers. The FIFO and FIFOP pins also provide
additional information on the data in the
The TXFIFO is write only, but may be read receive FIFO, as will be described in the
back using RAM access as described in Microcontroller Interface and Pin
the previous section. Data is read and Description section on page 32. Note that
written one byte at a time, as with RAM the FIFO and FIFOP pins only apply to the
access. The RXFIFO is both writeable and RXFIFO. The TXFIFO has its underflow
readable. Writing to the RXFIFO should flag in the status byte.
however only be done for debugging or for
using the RXFIFO for security operations The TXFIFO may be flushed by issuing a
(decryption / authentication). SFLUSHTX command strobe. Similarly, a
SFLUSHRX command strobe will flush the
The crystal oscillator must be running receive FIFO.
when accessing the FIFOs.

When writing to the TXFIFO, the status 13.7 Multiple SPI access
byte (see Table 5) is output for each new Register access, command strobes, FIFO
data byte on SO, as shown in Figure 9. access and RAM access may be issued
This could be used to detect TXFIFO continuously without setting CSn high.
underflow (see section RF Data Buffering E.g. the user may issue a command
section on page 39) while writing data to strobe, a register write and writing 3 bytes
the TXFIFO. to the TXFIFO in one operation, as
illustrated in Figure 11. The only exception
Multiple FIFO bytes may be accessed in is that FIFO and RAM access must be
one operation, as with the RAM access. terminated by setting CSn high.
SWRS041c Page 31 of 85
Not Recommended For New Designs
CC2420

CSn

SI ADDR ADDR - - ADDRTXFIFO DATAADDR DATAADDR+1 DATAADDR+2

SO Status Status DATA8MSB DATA8LSB Status Status Status Status

Command Register TXFIFO

Strobe Read Write

Figure 11. Multiple SPI Access Example

14 Microcontroller Interface and Pin Description

When used in a typical system, CC2420 will microcontroller uses 4 I/O pins for the SPI
interface to a microcontroller. This configuration interface (SI, SO, SCLK and
microcontroller must be able to: CSn). SO should be connected to an input
at the microcontroller. SI, SCLK and CSn
 Program CC2420 into different modes, must be microcontroller outputs.
read and write buffered data, and read Preferably the microcontroller should have
back status information via the 4-wire a hardware SPI interface.
SPI-bus configuration interface (SI, SO,
SCLK and CSn). The microcontroller pins connected to SI,
SO and SCLK can be shared with other
 Interface to the receive and transmit SPI-interface devices. SO is a high
FIFOs using the FIFO and FIFOP impedance output as long as CSn is not
status pins. activated (active low).

 Interface to the CCA pin for clear CSn should have an external pull-up
channel assessment. resistor or be set to a high level when the
voltage regulator is turned off in order to
 Interface to the SFD pin for timing prevent the input from floating. SI and
information (particularly for beaconing SCLK should be set to a defined level to
networks). prevent the inputs from floating.

14.1 Configuration interface

A CC2420 to microcontroller interface
example is shown in Figure 12. The

C
CC2420

FIFO GIO0
FIFOP Interrupt
CCA GIO1
SFD Timer Capture

CSn GIO2
SI MOSI
SO MISO
SCLK SCLK

Figure 12. Microcontroller interface example

SWRS041c Page 32 of 85
Not Recommended For New Designs
CC2420

recognition. This may be handled by using

14.2 Receive mode
the FIFOP pin, since this pin does not go
In receive mode, the SFD pin goes active active until the frame passes address
after the start of frame delimiter (SFD) field recognition.
has been completely received. If address
recognition is disabled or is successful, the Figure 14 shows an example of pin activity
SFD pin goes inactive again only after the when reading a packet from the RXFIFO.
last byte of the MPDU has been received. In this example, the packet size is 8 bytes,
If the received frame fails address IOCFG0.FIFOP_THR = 3 and
recognition, the SFD pin goes inactive MODEMCTRL0.AUTOCRC is set. The length
immediately. This is illustrated in Figure will be 8 bytes, RSSI will contain the
13. average RSSI level during reception of the
packet and FCS/corr contains information
The FIFO pin is active when there are one of FCS check result and the correlation
or more data bytes in the RXFIFO. The levels.
first byte to be stored in the RXFIFO is the 14.3 RXFIFO overflow
length field of the received frame, i.e. the
FIFO pin goes active when the length field The RXFIFO can only contain a maximum
is written to the RXFIFO. The FIFO pin of 128 bytes at a given time. This may be
then remains active until the RXFIFO is divided between multiple frames, as long
empty. as the total number of bytes is 128 or less.
If an overflow occurs in the RXFIFO, this is
If a previously received frame is signalled to the microcontroller by making
completely or partially inside the RXFIFO, the FIFO pin go inactive while the FIFOP
the FIFO pin will remain active until the pin is active. Data already in the RXFIFO
RXFIFO is empty. will not be affected by the overflow, i.e.
frames already received may be read out.
The FIFOP pin is active when the number
of unread bytes in the RXFIFO exceeds A SFLUSHRX command strobe is required
the threshold programmed into after an RXFIFO overflow to enable
IOCFG0.FIFOP_THR. When address reception of new data. Note that the
recognition is enabled the FIFOP pin will SFLUSHRX command strobe should be
remain inactive until the incoming frame issued twice to ensure that the SFD pin
passes address recognition, even if the goes back to its inactive state.
number of bytes in the RXFIFO exceeds
the programmed threshold. For security enabled frames, the MAC
layer must read the source address of the
The FIFOP pin will also go active when received frame before it can decide which
the last byte of a new packet is received, key to use to decrypt or authenticate. This
even if the threshold is not exceeded. If data must therefore not be overwritten
so, the FIFOP pin will go inactive once even if it has been read out of the RXFIFO
one byte has been read out of the by the microcontroller. If the
RXFIFO. SECCTRL0.RXFIFO_PROTECTION control
bit is set, CC2420 also protects the frame
When address recognition is enabled, data header of security enabled frames until
should not be read out of the RXFIFO decryption has been performed. If no MAC
before the address is completely received, security is used or if it is implemented
since the frame may be automatically outside the CC2420, this bit may be cleared
flushed by CC2420 if it fails address to achieve optimal use of the RXFIFO.

SWRS041c Page 33 of 85
Not Recommended For New Designs
CC2420
ed on
iv iti
ce gn
e d re
eco U d
ct te r
te by s d PD eive
de th es te t M rec
ng dr le s
S F D
Le Ad omp La yte
c b

Data received over RF Preamble SFD Length MAC Protocol Data Unit (MPDU) with correct address

Address
recognition OK SFD Pin

FIFO Pin

FIFOP Pin, if threshold

higher than frame length

FIFOP Pin, if threshold

lower than frame length

Data received over RF Preamble SFD Length MAC Protocol Data Unit (MPDU) with wrong address

Address
recognition fails SFD Pin

FIFO Pin

FIFOP Pin

Figure 13. Pin activity examples during receive

n
gh f he
hi r o w te
ins be HR o w by
a l st
m um _T es la
re n P go t of
P as IFO
FO ng F FO ou
FI s lo s > FI ad s
a yte re tart
b s

SCLK

SFD

CSn

SI ADDRTXFIFO - - - - - - - - -

SO Status Length PSDU0 PSDU1 PSDU2 PSDU3 PSDU4 PSDU5 RSSI FCS/Corr

FIFOP

FIFO

Figure 14. Example of pin activity when reading RXFIFO.

detected. See the RF Data Buffering

14.4 Transmit mode
section on page 39 for more information
During transmit the FIFO and FIFOP pins on TXFIFO underflow.
are still only related to the RXFIFO. The
SFD pin is however active during As can be seen from comparing Figure 13
transmission of a data frame, as shown in and Figure 15, the SFD pin behaves very
Figure 15. similarly during reception and transmission
of a data frame. If the SFD pins of the
The SFD pin goes active when the SFD transmitter and the receiver are compared
field has been completely transmitted. It during the transmission of a data frame, a
goes inactive again when the complete small delay of approximately 2 μs can be
MPDU (as defined by the length field) has seen because of bandwidth limitations in
been transmitted or if an underflow is both the transmitter and the receiver.

SWRS041c Page 34 of 85
Not Recommended For New Designs
CC2420
d or
an d
m ed U itte
m itt
co sm PD sm w
N n M n f lo
XO e tra st tra er
ST trob D La yte nd
s SF b Xu
T
Data transmitted
Preamble SFD Length MAC Protocol Data Unit (MPDU)
over RF

SFD Pin

CRC generated
12 symbol periods Automatically generated Data fetched by CC2420
preamble and SFD from TXFIFO

Figure 15. Pin activity example during transmit

received data frames. The SFD pin will go

14.5 General control and status pins
active when a start of frame delimiter has
In receive mode, the FIFOP pin can be been completely detected / transmitted.
used to interrupt the microcontroller when The SFD pin should preferably be
a threshold has been exceeded or a connected to a timer capture pin on the
complete frame has been received. This microcontroller.
pin should then be connected to a
microcontroller interrupt pin. For debug purposes, the SFD and CCA
pins can be used to monitor several status
In receive mode, the FIFO pin can be signals as selected by the IOCFG1
used to detect if there is data at all in the register. See Table 12 and Table 13 for
receive FIFO. available signals.

The SFD pin can be used to extract the The polarity of FIFO, FIFOP, SFD and CCA
timing information of transmitted and can be controlled by the IOCFG0 register
(address 0x1C).

15 Demodulator, Symbol Synchroniser and Data Decision

The block diagram for the CC2420 synchronisation is achieved by a

demodulator is shown in Figure 16. continuous start of frame delimiter (SFD)
Channel filtering and frequency offset search.
compensation is performed digitally. The
signal level in the channel is estimated to When a SFD is detected, data is written to
generate the RSSI level (see the RSSI / the RXFIFO and may be read out by the
Energy Detection section on page 48 for microcontroller at a lower bit rate than the
more information). Data filtering is also 250 kbps generated by the receiver.
included for enhanced performance.
The CC2420 demodulator also handles
With the ±40 ppm frequency accuracy symbol rate errors in excess of 120 ppm
requirement from [1], a compliant receiver without performance degradation.
must be able to compensate for up to 80 Resynchronisation is performed
ppm or 200 kHz. The CC2420 demodulator continuously to adjust for error in the
tolerates up to 300 kHz offset without incoming symbol rate.
significant degradation of the receiver
performance. The RXCTRL1.RXBPF_LOCUR control bit
should be written to 1.
Soft decision is used at the chip level, i.e.
the demodulator does not make a decision The MDMCTRL1.CORR_THR control bits
for each chip, only for each received are by default set to 20 defining the
symbol. De-spreading is performed using threshold for detecting IEEE 802.15.4 start
over sampled symbol correlators. Symbol of frame delimiters.

SWRS041c Page 35 of 85
Not Recommended For New Designs
CC2420
Digital Frequency Digital Symbol Data
I / Q Analog
ADC IF Channel Offset Data Correlators and Symbol
IF signal
Filtering Compensation Filtering Synchronisation Output

Average
RSSI Correlation
RSSI
Generator Value (may be
used for LQI)

Figure 16. Demodulator Simplified Block Diagram

16 Frame Format

CC2420 has hardware support for parts of Figure 17 [1] shows a schematic view of
the IEEE 802.15.4 frame format. This the IEEE 802.15.4 frame format. Similar
section gives a brief summary to the IEEE figures describing specific frame formats
802.15.4 frame format, and describes how (data frames, beacon frames,
CC2420 is set up to comply with this. acknowledgment frames and MAC
command frames) are included in [1].

Bytes: 2 1 0 to 20 n 2
MAC Frame Data Frame Check
Address
Layer Control Field Sequence Frame payload Sequence
Information
(FCF) Number (FCS)
MAC Header (MHR) MAC Payload MAC Footer
(MFR)

Bytes: 4 1 1 5 + (0 to 20) + n
Start of frame MAC Protocol
PHY Preamble Frame
Delimiter Data Unit
Layer Sequence Length
(SFD) (MPDU)
Synchronisation Header PHY Header PHY Service Data Unit
(SHR) (PHR) (PSDU)

11 + (0 to 20) + n
PHY Protocol Data Unit
(PPDU)

Figure 17. Schematic view of the IEEE 802.15.4 Frame Format [1]

The preamble sequence length can be set

16.1 Synchronisation header
by MDMCTRL0.PREAMBLE_LENGTH, while
The synchronisation header (SHR) the SFD is programmed in the SYNCWORD
consists of the preamble sequence register. SYNCWORD is 2 bytes long, which
followed by the start of frame delimiter gives the user some extra flexibility as
(SFD). In [1], the preamble sequence is described below. Figure 18 shows how the
defined to be 4 bytes of 0x00. The SFD is CC2420 synchronisation header relates to
one byte, set to 0xA7. the IEEE 802.15.4 specification.

In CC2420, the preamble length and SFD is The programmable preamble length only
configurable. The default values are applies to transmission, it does not affect
compliant with [1]. Changing these values receive mode. The preamble length should
will make the system non-compliant to not be set shorter than the default value.
IEEE 802.15.4. Note that 2 of the 8 zero-symbols in the
preamble sequence required by [1] are
A synchronisation header is always included in the SYNCWORD register so that
transmitted first in all transmit modes. the CC2420 preamble sequence is only 6
symbols long for compliance with [1]. Two
SWRS041c Page 36 of 85
Not Recommended For New Designs
CC2420
additional zero symbols in SYNCWORD A. If SYNCWORD = 0xA70F, CC2420 will
make CC2420 compliant with [1]. require the incoming symbol sequence of
(from left to right) 0 0 7 A. If SYNCWORD =
In reception, CC2420 synchronises to 0xA700, CC2420 will require the incoming
received zero-symbols and searches for symbol sequence of (from left to right) 0 0
the SFD sequence defined by the 0 7 A.
SYNCWORD register. The least significant
symbols in SYNCWORD set to 0xF will be In receive mode CC2420 uses the
ignored, while symbols different from 0xF preamble sequence for symbol
will be required for synchronisation. The synchronisation and frequency offset
default setting of 0xA70F thereby requires adjustments. The SFD is used for byte
one additional zero-symbol for synchronisation, and is not part of the data
synchronisation. This will reduce the stored in the receive buffer (RXFIFO).
number of false frames detected due to
noise.

The following illustrates how the

programmed synch word is interpreted
during reception by CC2420: If SYNCWORD =
0xA7FF, CC2420 will require the incoming
symbol sequence of (from left to right) 0 7

Synchronisation Header

Preamble SFD

IEEE 802.15.4 0 0 0 0 0 0 0 0 7 A

CC2420 2·(PREAMBLE_LENGTH + 1) zero symbols SW0 SW1 SW2 SW3

Each box corresponds to 4 bits. Hence the preamble corresponds to 8 x 4 ''0' s or 4 bytes with the value 0.
SW0 = SYNCWORD[3:0] if different from 'F', else '0'

SW1 = SYNCWORD[7:4] if different from 'F', else '0'

SW2 = SYNCWORD[11:8] if different from 'F', else '0'

SW3 = SYNCWORD[15:12] if different from 'F', else '0'

Figure 18. Transmitted Synchronisation Header

CC2420 uses the length field both for

16.2 Length field
transmission and reception, so this field
The frame length field shown in Figure 17 must always be included. In transmit
defines the number of bytes in the MPDU. mode, the length field is used for
Note that the length field does not include underflow detection, as described in the
the length field itself. It does however FIFO access section on page 31.
include the FCS (Frame Check
Sequence), even if this is inserted
16.3 MAC protocol data unit
automatically by CC2420 hardware. It also
includes the MIC if authentication is used. The FCF, data sequence number and
address information follows the length field
The length field is 7 bits and has a as shown in Figure 17. Together with the
maximum value of 127. The most MAC data payload and Frame Check
significant bit in the length field is reserved Sequence, they form the MAC Protocol
[1], and should be set to zero. Data Unit (MPDU).

The format of the FCF is shown in Figure

19. Please refer to [1] for details.
SWRS041c Page 37 of 85
Not Recommended For New Designs
CC2420
There is no hardware support for the data CC2420 includes hardware address
sequence number, this field must be recognition, as described in the Address
inserted and verified by software. Recognition section on page 41.

Bits: 0-2 3 4 5 6 7-9 10-11 12-13 14-15

Frame Security Frame Acknowledge Intra Reserved Destination Reserved Source
Type Enabled Pending request PAN addressing addressing
mode mode
Figure 19. Format of the Frame Control Field (FCF) [1]

interested in the correctness of the FCS,

16.4 Frame check sequence
not the FCS sequence itself. The FCS
A 2-byte frame check sequence (FCS) sequence itself is therefore not written to
follows the last MAC payload byte as the RXFIFO during receive.
shown in Figure 17. The FCS is calculated
over the MPDU, i.e. the length field is not Instead, when MODEMCTRL0.AUTOCRC is
part of the FCS. This field is automatically set the two FCS bytes are replaced by the
generated and verified by hardware when RSSI value, average correlation value
the MODEMCTRL0.AUTOCRC control bit is (used for LQI) and CRC OK/not OK. This
set. It is recommended to always have this is illustrated in Figure 21.
enabled, except possibly for debug
purposes. If cleared, CRC generation and The first FCS byte is replaced by the 8-bit
verification must be performed by RSSI value. This RSSI value is measured
software. over the first 8 symbols following the SFD.
See the RSSI section on page 48 for
The FCS polynomial is [1]: details.
16 12 5
x +x +x +1 The 7 least significant bits in the last FCS
byte are replaced by the average
The CC2420 hardware implementation is correlation value of the 8 first symbols of
shown in Figure 20. Please refer to [1] for the received PHY header (length field) and
further details. PHY Service Data Unit (PSDU). This
correlation value may be used as a basis
In transmit mode the FCS is appended at for calculating the LQI. See the Link
the correct position defined by the length Quality Indication section on page 49 for
field. The FCS is not written to the details.
TXFIFO, but stored in a separate 16-bit
register. The most significant bit in the last byte of
each frame is set high if the CRC of the
In receive mode the FCS is verified by received frame is correct and low
hardware. The user is normally only otherwise.

Data
input
(LSB
first)
r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15

Figure 20. CC2420 Frame Check Sequence (FCS) hardware implementation [1]

SWRS041c Page 38 of 85
Not Recommended For New Designs
CC2420
Length byte MPDU
RSSI
Data in RXFIFO n MPDU1 MPDU2 MPDUn-2 CRC / Corr
(signed)

Bit number 7 6 5 4 3 2 1 0
CRC
Correlation value (unsigned)
OK

Figure 21. Data in RXFIFO when MDMCTRL0.AUTOCRC is set

17 RF Data Buffering

CC2420 can be configured for different A TXFIFO underflow is issued if too few
transmit and receive modes, as set in the bytes are written to the TXFIFO.
MDMCTRL1.TX_MODE and Transmission is then automatically
MDMCTRL1.RX_MODE control bits. stopped. The underflow is indicated in the
Buffered mode (mode 0) will be used for TX_UNDERFLOW status bit, which is
normal operation of CC2420, while other returned during each address byte and
modes are available for test purposes. each byte written to the TXFIFO. The
underflow bit is only cleared by issuing a
SFLUSHTX command strobe.
17.1 Buffered transmit mode
In buffered transmit mode (TX_MODE 0), The TXFIFO can only contain one data
the 128 byte TXFIFO, located in CC2420 frame at a given time.
RAM, is used to buffer data before
transmission. A preamble sequence After complete transmission of a data
(defined in the Frame Format section frame, the TXFIFO is automatically refilled
below) is automatically inserted before the with the last transmitted frame. Issuing a
length field during transmission. The new STXON or STXONCCA command
length field must always be the first byte strobe will then cause CC2420 to retransmit
written to the transmit buffer for all frames. the last frame.

Writing one or multiple bytes to the Writing to the TXFIFO after a frame has
TXFIFO is described in the FIFO access been transmitted will cause the TXFIFO to
section on page 31. Reading data from the be automatically flushed before the new
TXFIFO is possible with RAM access, but byte is written. The only exception is if a
this does not remove the byte from the TXFIFO underflow has occurred, then a
FIFO. SFLUSHTX command strobe is required.

Transmission is enabled by issuing a

17.2 Buffered receive mode
STXON or STXONCCA command strobe.
See the Radio control state machine In buffered receive mode (RX_MODE 0),
section on page 43 for an illustration of the 128 byte RXFIFO, located in CC2420
how the transmit command strobes affect RAM, is used to buffer data received by
the state of CC2420. The STXONCCA strobe the demodulator. Accessing data in the
is ignored if the channel is busy. See the RXFIFO is described in the FIFO access
Clear Channel Assessment section on section on page 31.
page 50 for details on CCA.
The FIFO and FIFOP pins are used to
The preamble sequence is started 12 assist the microcontroller in supervising
symbol periods after the command strobe. the RXFIFO. Please note that the FIFO
After the programmable start of frame and FIFOP pins are only related to the
delimiter has been transmitted, data is RXFIFO, even if CC2420 is in transmit
fetched from the TXFIFO. mode.
SWRS041c Page 39 of 85
Not Recommended For New Designs
CC2420
Multiple data frames may be in the In serial transmit mode
RXFIFO simultaneously, as long as the (MDMCTRL1.TX_MODE=1), a
total number of bytes does not exceed synchronisation sequence is inserted at
128. the start of each frame by hardware, as in
buffered mode. Data is sampled by CC2420
See the RXFIFO overflow section on page on the positive edge of FIFOP and should
33 for details on how a RXFIFO overflow is be updated by the microcontroller on the
detected and signalled. negative edge of FIFOP. See Figure 22 for
an illustration of the timing in serial
transmit mode. The SFD and CCA pins
17.3 Unbuffered, serial mode
retain their normal operation also in serial
Unbuffered mode should be used for mode. CC2420 will remain in serial transmit
evaluation / debugging purposes only. mode until transmission is turned off
Buffered mode is recommended for all manually.
applications.
In serial receive mode
In unbuffered mode, the FIFO and FIFOP (MDMCTRL1.RX_MODE=1) byte
pins are reconfigured as data and data synchronisation is still performed by
clock pins. The TXFIFO and RXFIFO CC2420. This means that the FIFOP clock
buffers are not used in this mode. A pin will remain inactive until a start of
synchronous data clock is provided by frame delimiter has been detected.
CC2420 at the FIFOP pin, and the FIFO pin
is used as data input/output. The FIFOP
clock frequency is 250 kHz when active.
This is illustrated in Figure 22.

Incoming / outgoing
Preamble SFD s0 s1 s2
RF data

Transmit mode: 4 us

FIFOP
FIFO (from uC) b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b8 b9 b10 b11

Receive mode:

FIFOP
FIFO (from CC2420) b0 b1 b2 b3 b4

Figure 22. Unbuffered test mode, pin activity

SWRS041c Page 40 of 85
Not Recommended For New Designs
CC2420

18 Address Recognition

CC2420 includes hardware support for PAN identifier matches

address recognition, as specified in [1]. macPANId.
Hardware address recognition may be
enabled / disabled using the If any of the above requirements are not
MDMCTRL0.ADR_DECODE control bit. satisfied and address recognition is
enabled, CC2420 will disregard the
Address recognition is based on the incoming frame and flush the data from the
following requirements, listed from section RXFIFO. Only data from the rejected
7.5.6.2 in [1]: frame is flushed, data from previously
accepted frames may still be in the
 The frame type subfield shall not RXFIFO.
contain an illegal frame type
The IOCFG0.BCN_ACCEPT control bit
 If the frame type indicates that the must be set when the PAN identifier
frame is a beacon frame, the programmed into CC2420 RAM is equal to
source PAN identifier shall match 0xFFFF and cleared otherwise. This
macPANId unless macPANId is particularly applies to active and passive
equal to 0xFFFF, in which case scans as defined by [1], which requires all
the beacon frame shall be received beacons to be processed by the
accepted regardless of the source MAC sublayer.
PAN identifier.
Incoming frames with reserved frame
 If a destination PAN identifier is types (FCF frame type subfield is 4, 5, 6 or
included in the frame, it shall 7) is however accepted if the
match macPANId or shall be the RESERVED_FRAME_MODE control bit in
broadcast PAN identifier MDMCTRL0 is set. In this case, no further
(0xFFFF). address recognition is performed on these
frames. This option is included for future
 If a short destination address is expansions of the IEEE 802.15.4 standard.
included in the frame, it shall
match either macShortAddress or If a frame is rejected, CC2420 will only start
the broadcast address (0xFFFF). searching for a new frame after the
Otherwise if an extended rejected frame has been completely
destination address is included in received (as defined by the length field) to
the frame, it shall match avoid detecting false SFDs within the
aExtendedAddress. frame.

 If only source addressing fields The MDMCTRL0.PAN_COORDINATOR

are included in a data or MAC control bit must be correctly set, since
command frame, the frame shall parts of the address recognition procedure
only be accepted if the device is a requires knowledge about whether the
PAN coordinator and the source current device is a PAN coordinator or not.

19 Acknowledge Frames

CC2420 includes hardware support for recognition with the acknowledge request
transmitting acknowledge frames, as flag set and a valid CRC. AUTOACK
specified in [1]. Figure 23 shows the therefore does not make sense unless
format of the acknowledge frame. also ADR_DECODE and AUTOCRC are
enabled. The sequence number is copied
If MDMCTRL0.AUTOACK is enabled, an from the incoming frame.
acknowledge frame is transmitted for all
incoming frames accepted by the address

SWRS041c Page 41 of 85
Not Recommended For New Designs
CC2420
AUTOACK may be used for non-beacon symbol periods after the last symbol of the
systems as long as the frame pending field incoming frame. This is as specified by [1]
(see Figure 19) is cleared. The for non-beacon networks.
acknowledge frame is then transmitted 12

Bytes: 4 1 1 2 1 2
Start of Frame Frame Data Frame Check
Preamble Frame
Delimiter Control Field Sequence Sequence
Sequence Length
(SFD) (FCF) Number (FCS)
Synchronisation Header PHY Header MAC Header (MHR) MAC Footer
(SHR) (PHR) (MFR)

Figure 23. Acknowledge frame format [1]

Two command strobes, SACK and If a SACK or SACKPEND command strobe

SACKPEND are defined to transmit is issued while receiving an incoming
acknowledge frames with the frame frame, the acknowledge frame is
pending field cleared or set, respectively. transmitted 12 symbol periods after the
The acknowledge frame is only transmitted last symbol of the incoming frame. This
if the CRC is valid. should be used to transmit acknowledge
frames in non-beacon networks. This
For systems using beacons, there is an timing is also illustrated in Figure 24.
additional timing requirement that the
acknowledge frame transmission should Using SACKPEND will set the pending data
be started on the first backoff-slot flag for automatically transmitted
boundary (20 symbol periods) at least 12 acknowledge frames using AUTOACK. The
symbol periods after the last symbol of the pending flag will then be set also for future
incoming frame. This timing must be acknowledge frames, until a SACK
controlled by the microcontroller by issuing command strobe is issued.
the SACK and SACKPEND command strobe
12 symbol periods before the following Acknowledge frames may be manually
backoff-slot boundary, as illustrated in transmitted using normal data
Figure 24. transmission if desired.

y
l D ar
b o PEN u nd
m K
sy AC bo
U S lot
D / fs
t PP K k of
s C c
La SA Ba
Beacon
PPDU Acknowledge
network 12
symbol
periods

12 symbol periods <= tack < 32 symbol periods

Non-beacon
PPDU Acknowledge
network

tack = 12 symbol periods

Figure 24. Acknowledge frame timing

SWRS041c Page 42 of 85
Not Recommended For New Designs
CC2420

20 Radio control state machine

CC2420 has a built-in state machine that is For test purposes, the frequency
used to switch between different synthesizer (FS) can also be manually
operational states (modes). The change of calibrated and started by using the
state is done either by using command STXCAL command strobe register. This
strobes or by internal events such as SFD will not start a transmission before a
detected in receive mode. STXON command strobe is issued. This is
not shown in Figure 25.
The radio control state machine states are
shown in Figure 25. The numbers in Enabling transmission is done by issuing a
brackets refer to the state number STXON or STXONCCA command strobe.
readable in the FSMSTATE status register.
Reading the FSMSTATE status register is Turning off RF can be accomplished by
primarily for test / debug purposes. using one of the SRFOFF or SXOSCOFF
command strobe registers.
Before using the radio in either RX or TX
mode, the voltage regulator and crystal After reset the CC2420 is in Power Down
oscillator must be turned on and become mode. All configuration registers can then
stable. The voltage regulator and crystal be programmed in order to make the chip
oscillator start-up times are given in the ready to operate at the correct frequency
Electrical Specifications section on page 9. and mode. Due to the very fast start-up
time, CC2420 can remain in Power Down
The crystal oscillator is controlled by until a transmission session is requested.
accessing the SXOSCON / SXOSCOFF
command strobes. The XOSC16M_STABLE As also described in the 4-wire Serial
bit in the status register returned during Configuration and Data Interface section
address transfer indicates whether the on page 27, the crystal oscillator must be
oscillator is running and stable or not (see running (IDLE) in order to have access to
Table 5). This status register can be polled the RAM and FIFOs.
when waiting for the oscillator to start.

SWRS041c Page 43 of 85
Not Recommended For New Designs
CC2420

Voltage Regulator Off VREG_EN set low

VREG_EN set high

Wait until voltage regulator

has powered up

Chip Reset
(pin or register)
SXOSCOFF
command strobe Crystal oscillator disabled,
Power Down (PD)
All States register access enabled,
[0]
FIFO / RAM access disabled

SXOSCON

Wait for the specified crystal oscillator

start-up time, or poll the
XOSC16M_STABLE status bit

SRFOFF
All States IDLE All RX states
except Power Down (PD) [1]

nd
CC CCA or
N

ST

A) a
XO

XO

ON N
SR

TX XO
N

(S ST
RX_CALIBRATE TX_CALIBRATE
[2 and 40] [32]
Tr

12 symbol periods 8 or 12 symbol

an

later periods later

sm
i

HRX
ss

SFLUS RX_SFD_SEARCH TX_PREAMBLE Preamble and SFD

io
n

[3, 4, 5 and 6] [34, 35 and 36] is transmitted

co
m ple

SFD
ted

Frame received or found

SACK or SACKPEND

failed address
RX_WAIT recognition RX_FRAME TX_FRAME TXFIFO Data
[14] [16 and 40] [37, 38 and 39] is transmitted
low
erf Automatic or manual
Ov Underflow
acknowledge request

RX_OVERFLOW TX_ACK_CALIBRATE TX_UNDERFLOW

[17] [48] [56]

12 symbol The transition from

periods later TX_UNDERFLOW to
RX_CALIBRATE is automatic,
TX_ACK_PREAMBLE but SFLUSHTX must be used to
[49, 50 and 51] reset underflow indication

Acknowledge
completed
TX_ACK
[52, 53 and 54]

Figure 25. Radio control states

SWRS041c Page 44 of 85
Not Recommended For New Designs
CC2420

21 MAC Security Operations (Encryption and Authentication)

CC2420 features hardware IEEE 802.15.4 As can be seen from Table 6 on page 31,
MAC security operations. This includes KEY0 is located from address 0x100 and
counter mode (CTR) encryption / KEY1 from address 0x130.
decryption, CBC-MAC authentication and
CCM encryption + authentication. All A way of establishing the keys used for
security operations are based on AES encryption and authentication must be
encryption [2] using 128 bit keys. Security decided for each particular application.
operations are performed within the IEEE 802.15.4 does not define how this is
transmit and receive FIFOs on a frame done, it is left to the higher layer of the
basis. protocol.

CC2420 also includes stand-alone AES ZigBee uses an Elliptic Curve

encryption, in which one 128 bit plaintext is Cryptography (ECC) based approach to
encrypted to a 128 bit ciphertext. establish keys. For PC based solutions,
more processor intensive solutions such
The SAES, STXENC and SRXDEC as Diffie-Hellman may be chosen. Some
command strobes are used to start applications may also use pre-
security operations in CC2420 as will be programmed keys, e.g. for remote keyless
described in the following sections. The entry where the key and lock are delivered
ENC_BUSY status bit (see Table 5) may be in pairs. A push-button approach for
used to monitor when a security operation loading keys may also be selected.
has been completed. Security command
strobes issued while the security engine is 21.2 Nonce / counter
busy will be ignored, and the ongoing
operation will be completed. The receive and transmit nonces used for
encryption / decryption are located in RAM
Table 6 on page 31 shows the CC2420 from addresses 0x110 and 0x140
RAM memory map, including the security respectively. They are both 16 bytes.
related data located from addresses 0x100
through 0x15F. RAM access (see the RAM The nonce must be correctly initialized
access section on page 29) is used to before receive or transmit CTR or CCM
write or read the keys, nonces and stand- operations are started. The format of the
alone buffer. All security related data is nonce is shown in Table 7. The block
stored little-endian, i.e. the least significant counter must be set to 1 for compliance
byte is transferred first over the SPI with [1]. The key sequence counter is
interface during RAM read or write controlled by a layer above the MAC layer.
operations. The frame counter must be increased for
each new frame by the MAC layer. The
For a complete description of IEEE source address is the 64 bit IEEE address.
802.15.4 MAC security operations, please
refer to [1]. 1 byte 8 bytes 4 bytes 1 byte 2 bytes
Flags Source Frame Key Block
Address Counter Sequence Counter
21.1 Keys Counter
All security operations are based on 128 Table 7. IEEE 802.15.4 Nonce [1]
bit keys. The CC2420 RAM space has
storage space for two individual keys The block counter bytes are not updated in
(KEY0 and KEY1). Transmit, receive and RAM, only in a local copy that is reloaded
stand-alone encryption may select one of for each new in-line security operation. I.e.
these two keys individually in the the block counter part of the nonce does
SEC_TXKEYSEL, SEC_RXKEYSEL and not need to be rewritten. The CC2420 block
SEC_SAKEYSEL control bits (SECCTRL0). counter should be set to 0x0001 for
compliance with [1].

SWRS041c Page 45 of 85
Not Recommended For New Designs
CC2420
CC2420 gives the user full flexibility in The frame counter part of the nonce must
selecting the flags for both nonces. The be incremented for each new packet by
flag setting is stored in the most significant software.
byte of the nonce. The flag byte used for
encryption and authentication is then
generated as shown in Figure 26.
MSB in CC2420 nonce RAM
7 6 5 4 3 2 1 0
CTR Flag CBC Flag
- L SECCTRL0.SEC_M
bits 7:6 bits 7:6

CTR mode flag byte CBC-MAC flag byte

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Res Res 0 0 0 L Res Adata M L

Figure 26. CC2420 Security Flag Byte

therefore be used for all security

21.3 Stand-alone encryption
operations.
Plain AES encryption, with 128 bit plaintext
and 128 bit keys [2], is available using The key, nonce (does not apply to CBC-
stand-alone encryption. The plaintext is MAC), and SECCTRL0 and SECCTRL1
stored in stand-alone buffer located at control registers must be correctly set
RAM location 0x120, as can be seen from before starting any in-line security
Table 6 on page 31. operation.

A stand-alone encryption operation is The in-line security mode is set in

initiated by using the SAES command SECCTRL0.SEC_MODE to one of the
strobe. The selected key following modes:
(SECCTRL0.SEC_SAKEYSEL) is then used
to encrypt the plaintext written to the  Disabled
stand-alone buffer. Upon completion of the  CBC-MAC (authentication)
encryption operation, the ciphertext is  CTR (encryption / decryption)
written back to the stand-alone buffer,  CCM (authentication and encryption /
thereby overwriting the plaintext. decryption)

Note that RAM write operations also When enabled, TX in-line security is
output data currently in RAM, so that a started in one of two ways:
new plaintext may be written at the same
time as reading out the previous  Issue a STXENC command strobe. In-
ciphertext. line security will be performed within
the TXFIFO, but a RF transmission will
21.4 In-line security operations not be started. Ciphertext may be read
back using RAM read operations.
CC2420 can do MAC security operations  Issue a STXON or STXONCCA
(encryption, decryption and authentication) command strobe. In-line security will
on frames within the TXFIFO and RXFIFO. be performed within the TXFIFO and a
These operations are called in-line RF transmission of the ciphertext is
security operations. started.

As with other MAC hardware support

within CC2420, in-line security operation When enabled, RX in-line security is
relies on the length field in the PHY started as follows:
header. A correct length field must

SWRS041c Page 46 of 85
Not Recommended For New Designs
CC2420
 Issue a SRXDEC command strobe. The TXFIFO at all, and data will be encrypted
first frame in the RXFIFO is then as it is written to the TXFIFO.
decrypted / authenticated as set by the
current security mode. When decryption is initiated with a
SRXDEC command strobe, the ciphertext of
RX in-line security operations are always the RXFIFO is then decrypted as specified
performed on the first frame currently by [1].
inside the RXFIFO, even if parts of this
have already been read out over the SPI
21.6 CBC-MAC
interface. This allows the receiver to first
read the source address out to decide CBC-MAC in-line authentication is
which key to use before doing provided by CC2420 hardware.
authentication of the complete frame. In
CTR or CCM mode it is of course SECCTRL0.SEC_M sets the MIC length M,
important that bytes to be decrypted are encoded as (M-2)/2.
not read out before the security operation
is started. When enabling CBC-MAC in-line TXFIFO
authentication, the generated MIC is
When the SRXDEC command strobe is written to the TXFIFO for transmission.
issued, the FIFO and FIFOP pins will go The frame length must include the MIC.
inactive. This is to indicate to the
microcontroller that no further data may be SECCTRL1.SEC_TXL / SEC_RXL sets the
read out before the next byte to be read number of bytes between the length field
has undergone the requested security and the first byte to be authenticated,
operation. normally set to 0 for MAC authentication.

The frame in the RXFIFO may be received SECCTRL0.SEC_CBC_HEAD defines if the

over RF or it may be written into the authentication length is used as the first
RXFIFO over the SPI interface for byte of data to be authenticated or not.
debugging or higher layer security This bit should be set for compliance with
operations. [1].

21.5 CTR mode encryption / When enabling CBC-MAC in-line RXFIFO

decryption authentication, the generated MIC is
compared to the MIC in the RXFIFO. The
CTR mode encryption / decryption is last byte of the MIC is replaced in the
performed by CC2420 on MAC frames RXFIFO with:
within the TXFIFO / RXFIFO respectively.
 0x00 if the MIC is correct
SECCTRL1.SEC_TXL / SEC_RXL sets the
number of bytes between the length field  0xFF if the MIC is incorrect
and the first byte to be encrypted /
decrypted respectively. This controls the The other bytes in the MIC are left
number of plaintext bytes in the current unchanged in the RXFIFO.
frame. For IEEE 802.15.4 MAC encryption,
only the MAC payload (see Figure 17 on
page 36) should be encrypted, so 21.7 CCM
SEC_TXL / SEC_RXL is set to 3 + (0 to 20) CCM combines CTR mode encryption and
depending on the address information in CBC-MAC authentication in one operation.
the current frame. CCM is described in [3].

When encryption is initiated, the plaintext SECCTRL1.SEC_TXL / SEC_RXL sets the

in the TXFIFO is then encrypted as number of bytes after the length field to be
specified by [1]. The encryption module authenticated but not encrypted.
will encrypt all the plaintext currently
available, and wait if not everything is pre- The MIC is generated and verified very
buffered. The encryption operation may much like with CBC-MAC described
also be started without any data in the

SWRS041c Page 47 of 85
Not Recommended For New Designs
CC2420
above. The only differences are from the 21.8 Timing
requirements in [1] for CCM.
Table 8 shows some examples of the time
used by the security module for different
operations.

Mode l(a) l(m) l(MIC) Time

[us]

CCM 50 69 8 222
CTR - 15 - 99
CBC 17 98 12 99
Stand- - 16 - 14
alone
Table 8. Security timing examples

22 Linear IF and AGC Settings

CC2420 is based on a linear IF chain where The AGC characteristics are set through
the signal amplification is done in an the AGCCTRL, AGCTST0, AGCTST1 and
analog VGA (variable gain amplifier). The AGCTST2 registers. The reset values
gain of the VGA is digitally controlled. should be used for all AGC control and
test registers.
The AGC (Automatic Gain Control) loop
ensures that the ADC operates inside its
dynamic range by using an analog/digital
feedback loop.

23 RSSI / Energy Detection

CC2420 has a built-in RSSI (Received where the RSSI_OFFSET is found

Signal Strength Indicator) providing a empirically during system development
digital value that can be read from the 8 from the front end gain. RSSI_OFFSET is
bit, signed 2’s complement approximately –45. E.g. if reading a value
RSSI.RSSI_VAL register. of –20 from the RSSI register, the RF input
power is approximately –65 dBm.
The RSSI value is always averaged over 8
symbol periods (128 μs), in accordance A typical plot of the RSSI_VAL reading as
with [1]. The RSSI_VALID status bit function of input power is shown in Figure
(Table 5) indicates when the RSSI value is 27. It can be seen from the figure that the
valid, meaning that the receiver has been RSSI reading from CC2420 is very linear
enabled for at least 8 symbol periods. and has a dynamic range of about 100 dB.

The RSSI register value RSSI.RSSI_VAL The RSSI register value RSSI.RSSI_VAL
can be referred to the power P at the RF is calculated and continuously updated for
pins by using the following equations: each symbol after RSSI has become valid.

P = RSSI_VAL + RSSI_OFFSET [dBm]

SWRS041c Page 48 of 85
Not Recommended For New Designs
CC2420

60

40

RSSI Register Value 20

0
-100 -80 -60 -40 -20 0
-20

-40

-60
RF Level [dBm]

Figure 27. Typical RSSI value vs. input power

24 Link Quality Indication

The link quality indication (LQI) As described in the Frame check

measurement is a characterisation of the sequence section on page 38, the average
strength and/or quality of a received correlation value for the 8 first symbols is
packet, as defined by [1]. appended to each received frame together
with the RSSI and CRC OK/not OK when
The RSSI value described in the previous MDMCTRL0.AUTOCRC is set. A correlation
section may be used by the MAC software value of ~110 indicates a maximum quality
to produce the LQI value. The LQI value is frame while a value of ~50 is typically the
required by [1] to be limited to the range 0 lowest quality frames detectable by
through 255, with at least 8 unique values. CC2420.
Software is responsible for generating the
appropriate scaling of the LQI value for the Software must convert the correlation
given application. value to the range 0-255 defined by [1],
e.g. by calculating:
Using the RSSI value directly to calculate
the LQI value has the disadvantage that LQI = (CORR – a) · b
e.g. a narrowband interferer inside the
channel bandwidth will increase the LQI limited to the range 0-255, where a and b
value although it actually reduces the true are found empirically based on PER
link quality. CC2420 therefore also provides measurements as a function of the
an average correlation value for each correlation value.
incoming packet, based on the 8 first
symbols following the SFD. This unsigned A combination of RSSI and correlation
7-bit value can be looked upon as a values may also be used to generate the
measurement of the “chip error rate,” LQI value.
although CC2420 does not do chip
decision.

SWRS041c Page 49 of 85
Not Recommended For New Designs
CC2420

25 Clear Channel Assessment

The clear channel assessment signal is 0 Reserved

based on the measured RSSI value and a 1 Clear channel when received energy is below
programmable threshold. The clear threshold.
channel assessment function is used to
2 Clear channel when not receiving valid IEEE
implement the CSMA-CA functionality 802.15.4 data.
specified in [1]. CCA is valid when the
receiver has been enabled for at least 8 3 Clear channel when energy is below threshold
and not receiving valid IEEE 802.15.4 data
symbol periods.

Carrier sense threshold level is

programmed by RSSI.CCA_THR. The Clear channel assessment is available on
threshold value can be programmed in the CCA output pin. CCA is active high, but
steps of 1 dB. A CCA hysteresis can also the polarity may be changed by setting the
be programmed in the IOCFG0.CCA_POLARITY control bit.
MDMCTRL0.CCA_HYST control bits.
Implementing CSMA-CA may easiest be
All 3 CCA modes specified by [1] are done by using the STXONCCA command
implemented in CC2420. They are set in strobe, as described in the Radio control
MDMCTRL0.CCA_MODE, as can be seen in state machine section on page 43.
the register description. The different Transmission will then only start if the
modes are: channel is clear. The TX_ACTIVE status
bit (see Table 5) may be used to detect the
result of the CCA.

26 Frequency and Channel Programming

The operating frequency is set by IEEE 802.15.4 specifies 16 channels

programming the 10 bit frequency word within the 2.4 GHz band, in 5 MHz steps,
located in FSCTRL.FREQ[9:0]. The numbered 11 through 26. The RF
operating frequency FC in MHz is given by: frequency of channel k is given by [1]:

FC = 2048 + FSCTRL.FREQ[9:0] MHz FC = 2405 + 5 (k-11) MHz, k=11, 12, ..., 26

The frequency can be programmed with 1 For operation in channel k, the

MHz resolution. In receive mode the actual FSCTRL.FREQ register should therefore
LO frequency is FC – 2 MHz, since a 2 be set to:
MHz IF is used. Direct conversion is used
for transmission, so here the LO frequency FSCTRL.FREQ = 357 + 5 (k-11)
equals FC. The 2 MHz IF is automatically
set by CC2420, so the frequency
programming is equal for RX and TX.

SWRS041c Page 50 of 85
Not Recommended For New Designs
CC2420

27 VCO and PLL Self-Calibration

In order to ensure reliable operation the
27.1 VCO
VCO’s bias current and tuning range are
The VCO is completely integrated and automatically calibrated every time the RX
operates at 4800 – 4966 MHz. The VCO mode or TX mode is enabled, i.e. in the
frequency is divided by 2 to generate RX_CALIBRATE, TX_CALIBRATE and
frequencies in the desired band (2400- TX_ACK_CALIBRATE control states in
2483.5 MHz). Figure 25 on page 44.

27.2 PLL self-calibration

The VCO's characteristics will vary with
temperature, changes in supply voltages,
and the desired operating frequency.

28 Output Power Programming

The RF output power of the device is settings, including the complete

programmable and is controlled by the programming of the TXCTRL control
TXCTRL.PA_LEVEL register. Table 9 register. The typical current consumption
shows the output power for different is also shown.

PA_LEVEL TXCTRL register Output Power [dBm] Current Consumption [mA]

31 0xA0FF 0 17.4
27 0xA0FB -1 16.5
23 0xA0F7 -3 15.2
19 0xA0F3 -5 13.9
15 0xA0EF -7 12.5
11 0xA0EB -10 11.2
7 0xA0E7 -15 9.9
3 0xA0E3 -25 8.5
Table 9. Output power settings and typical current consumption @ 2.45 GHz

29 Voltage Regulator

CC2420 includes a low drop-out voltage The regulated 1.8 V voltage output is
regulator. This is used to provide a 1.8 V available on the VREG_OUT pin. A
power supply to the CC2420 power simplified schematic of the voltage
supplies. The voltage regulator should not regulator is shown in Figure 28.
be used to provide power to other circuits
because of limited power sourcing The voltage regulator requires external
capability and noise considerations. components as described in the
Application Circuit section on page 19.
The voltage regulator input pin VREG_IN
is connected to the unregulated 2.1 to 3.6 When disabling the voltage regulator, note
V power supply. The voltage regulator is that register and RAM programming will be
enabled / disabled using the active high lost as leakage current reduces the output
voltage regulator enable pin VREG_EN. voltage on the VREG_OUT pin below 1.6 V.

SWRS041c Page 51 of 85
Not Recommended For New Designs
CC2420
CC2420 should then be reset before the be left open. Note that the battery monitor
voltage regulator is disabled. will not work when the voltage regulator is
not used.
In applications where the internal voltage
regulator is not used, connect VREG_EN
and VREG_IN to ground. VREG_OUT shall

VREG_EN VREG_IN

Regulator
Enable / disable

Internal
bandgap 1.25 V
voltage
reference
VREG_OUT

Figure 28. Voltage regulator, simplified schematic

30 Battery Monitor

The on-chip battery monitor enables programmable threshold. A simplified

monitoring the unregulated voltage on the schematic of the battery monitor is shown
VREG_IN pin. It gives status information in Figure 29.
on the voltage being above or below a

SWRS041c Page 52 of 85
Not Recommended For New Designs
CC2420
BATTMON.BATTMON_EN VREG_IN

Internal
bandgap 1.25 V
voltage
BATTMON.BATTMON_OK
reference

BATTMON.BATTMON_VOLTAGE[4:0]

Figure 29. Battery monitor, simplified schematic

The battery monitor is controlled through 72  BATTMON_VO LTAGE
V  1.25 V 
the BATTMON control register. The battery toggle
27
monitor is enabled and disabled using the
BATTMON.BATTMON_EN control bit. The Alternatively, for a desired toggle voltage,
voltage regulator must also be enabled BATTMON_VOLTAGE should be set
when using the battery monitor. according to:

The battery monitor status bit is available

BATTMON_VO LTAGE  72  27 
V toggle

in the BATTMON.BATTMON_OK status bit. 1.25 V

This bit is high when the VREG_IN input
voltage is higher than the toggle voltage The voltage regulator must be enabled for
Vtoggle. at least 100 μs before the first
measurement. After being enabled, the
The battery monitor toggle voltage is set in BATTMON_OK status bit needs 2 μs to
the 5-bit BATTMON.BATTMON_VOLTAGE settle for each new toggle voltage
control bits. BATTMON_VOLTAGE is an programmed.
unsigned, positive number from 0 to 31.
The toggle voltage is given by: The main performance characteristics of
the battery monitor is shown in the
Electrical Specifications section on page 9.

31 Crystal Oscillator

An external clock signal or the internal MAIN.XOSC16M_BYPASS bit must be set

crystal oscillator can be used as main when an external clock signal is used.
frequency reference. The reference
frequency must be 16 MHz. Because the Using the internal crystal oscillator, the
crystal frequency is used as reference for crystal must be connected between the
the data rate as well as other internal XOSC16_Q1 and XOSC16_Q2 pins. The
signal processing functions, other oscillator is designed for parallel mode
frequencies cannot be used. operation of the crystal. In addition,
loading capacitors (C381 and C391) for the
If an external clock signal is used this crystal are required. The loading capacitor
should be connected to XOSC16_Q1, while values depend on the total load
XOSC16_Q2 should be left open. The capacitance, CL, specified for the crystal.
SWRS041c Page 53 of 85
Not Recommended For New Designs
CC2420
The total load capacitance seen between The crystal oscillator circuit is shown in
the crystal terminals should equal CL for Figure 30. Typical component values for
the crystal to oscillate at the specified different values of CL are given in Table
frequency. 10.

1 The crystal oscillator is amplitude

CL   C parasitic regulated. This means that a high current
1 1
 is used to start up the oscillations. When
C381 C391 the amplitude builds up, the current is
reduced to what is necessary to maintain a
The parasitic capacitance is constituted by stable oscillation. This ensures a fast start-
pin input capacitance and PCB stray up and keeps the drive level to a minimum.
capacitance. The total parasitic The ESR of the crystal must be within the
capacitance is typically 2 pF - 5 pF. specification in order to ensure a reliable
start-up (see the Electrical Specifications
section).

XOSC16_Q1 XOSC16_Q2

XTAL

C391 C381

Figure 30. Crystal oscillator circuit

Item CL= 16 pF

C381 27 pF

C391 27 pF
Table 10. Crystal oscillator component values

32 Input / Output Matching

The RF input / output is differential (RF_N Component values are given in Table 2.
and RF_P). In addition there is supply Using a differential antenna, no balun is
switch output pin (TXRX_SWITCH) that required.
must have an external DC path to RF_N
and RF_P. If a single ended output is required (for a
single ended connector or a single ended
In RX mode the TXRX_SWITCH pin is at antenna), a balun should be used for
ground and will bias the LNA. In TX mode optimum performance.
the TXRX_SWITCH pin is at supply rail
voltage and will properly bias the internal The balun adds the signals from the RF_N
PA. and RF_P. This is achieved having two
paths with equal amplitude response, but
The RF output and DC bias can be done 180 degrees phase difference.
using different topologies. Some are
shown in Figure 4 and Figure 5.

SWRS041c Page 54 of 85
Not Recommended For New Designs
CC2420

33 Transmitter Test Modes

CC2420 can be set into different transmit 0x1800 to the DACTST register and issue
test modes for performance evaluation. a STXON command strobe. The transmitter
The test mode descriptions in the following is then enabled while the transmitter I/Q
sections requires that the chip is first reset, DACs are overridden to static values. An
the crystal oscillator is enabled using the unmodulated carrier will then be available
SXOSCON command strobe and that the on the RF output pins.
crystal oscillator has stabilised.
A plot of the single carrier output spectrum
from CC2420 is shown in Figure 31 below.
33.1 Unmodulated carrier
An unmodulated carrier may be
transmitted by setting
MDMCTRL1.TX_MODE to 2 or 3, writing

RBW 10 kHz RF Att 30 dB

Ref Lvl VBW 10 kHz
3 dBm SWT 50 ms Unit dBm
3
0
A

-10

-20

-30 1AVG 1SA

-40

-50

-60

-70

-80

-90

-97
Center 2.45 GHz 200 kHz/ Span 2 MHz

Date: 23.OCT.2003 21:38:33

Figure 31. Single carrier output

SWRS041c Page 55 of 85
Not Recommended For New Designs
CC2420
sequence for bit error testing. Please note
33.2 Modulated spectrum
that CC2420 requires symbol
The CC2420 has a built-in test pattern synchronisation, not only bit
generator that can generate pseudo synchronisation, for correct reception.
random sequence using the CRC Packet error rate is therefore a better
generator. This is enabled by setting measurement for the true RF performance.
MDMCTRL1.TX_MODE to 3 and issues an
STXON command strobe. The modulated Another option to generate a modulated
spectrum is then available on the RF pins. spectrum is to fill the TXFIFO with pseudo-
The low byte of the CRC word is random data and set
transmitted and the CRC is updated with MDMCTRL1.TX_MODE to 2. CC2420 will
0xFF for each new byte. The length of the then transmit data from the FIFO
transmitted data sequence is 65535 bits. disregarding a TXFIFO underflow. The
The transmitted data-sequence is then: length of the transmitted data sequence is
then 1024 bits (128 bytes).
[Synchronisation header] [0x00, 0x78,
0xb8, 0x4b, 0x99, 0xc3, 0xe9, …] A plot of the modulated spectrum from
CC2420 is shown in Figure 32. Note that to
Since a synchronisation header (preamble find the output power from the modulated
and SFD) is transmitted in all TX modes, spectrum, the RBW must be set to 3 MHz
this test mode may also be used to or higher.
transmit a known pseudorandom bit

RBW 100 kHz RF Att 30 dB

Ref Lvl VBW 100 kHz
0 dBm SWT 5 ms Unit dBm
0

-10

-20

-30
1AVG 1SA

-40

-50

-60

-70

-80

-90

-100
Center 2.45 GHz 1 MHz/ Span 10 MHz

Date: 23.OCT.2003 21:34:19

Figure 32. Modulated spectrum plot

SWRS041c Page 56 of 85
Not Recommended For New Designs
CC2420

34 System Considerations and Guidelines

SRD regulations
34.3 Crystal accuracy and drift
International regulations and national laws A crystal accuracy of ±40 ppm is required
regulate the use of radio receivers and for compliance with IEEE 802.15.4 [1].
transmitters. SRDs (Short Range Devices) This accuracy must also take ageing and
for license free operation are allowed to temperature drift into consideration.
operate in the 2.4 GHz band worldwide.
The most important regulations are ETSI A crystal with low temperature drift and low
EN 300 328 and EN 300 440 (Europe), aging could be used without further
FCC CFR-47 part 15.247 and 15.249 compensation. A trimmer capacitor in the
(USA), and ARIB STD-T66 (Japan). crystal oscillator circuit (in parallel with C7)
could be used to set the initial frequency
accurately.
34.1 Frequency hopping and multi-
channel systems
For non-IEEE 802.15.4 systems, the
The 2.4 GHz band is shared by many robust demodulator in CC2420 allows up to
systems both in industrial, office and home 120 ppm total frequency offset between
environments. CC2420 uses direct the transmitter and receiver. This could
sequence spread spectrum (DSSS) as e.g. relax the accuracy requirement to 60
defined by [1] to spread the output power, ppm for each of the devices.
thereby making the communication link
more robust even in a noisy environment. Optionally in a star network topology, the
FFD could be equipped with a more
With CC2420 it is also possible to combine accurate crystal thereby relaxing the
both DSSS and FHSS (frequency hopping requirement on the RFD. This can make
spread spectrum) in a proprietary non- sense in systems where the RFDs ship in
IEEE 802.15.4 system. This is achieved by higher volumes than the FFDs.
reprogramming the operating frequency
(see the Frequency and Channel
34.4 Communication robustness
Programming section on page 50) before
enabling RX or TX. A frequency CC2420 provides very good adjacent,
synchronisation scheme must then be alternate and co channel rejection, image
implemented within the proprietary MAC frequency suppression and blocking
layer to make the transmitter and receiver properties. The CC2420 performance is
operate on the same RF channel. significantly better than the requirements
imposed by [1]. These are highly important
parameters for reliable operation in the 2.4
34.2 Data burst transmissions
GHz band, since an increasing number of
The data buffering in CC2420 lets the user devices/systems are using this license free
have a lower data rate link between the frequency band.
microcontroller and the RF device than the
RF bit rate of 250 kbps. This allows the
34.5 Communication security
microcontroller to buffer data at its own
speed, reducing the workload and timing The hardware encryption and
requirements. authentication operations in CC2420 enable
secure communication, which is required
The relatively high data rate of CC2420 for many applications. Security operations
also reduces the average power require a lot of data processing, which is
consumption compared to the 868 / 915 costly in an 8-bit microcontroller system.
MHz bands defined by [1], where only 20 / The hardware support within CC2420
40 kbps are available. CC2420 may be enables a high level of security even with
powered up a smaller portion of the time, a low-cost 8 bit controller.
so that the average power consumption is
reduced for a given amount of data to be
transferred.
SWRS041c Page 57 of 85
Not Recommended For New Designs
CC2420
34.6 Low-cost systems required to re-gain
synchronisation.
As the CC2420 provides 250 kbps multi-
channel performance without any external
In an IEEE 802.15.4 system, all
filters, a very low-cost system can be
communication is based on packets. The
made.
sensitivity limit specified by [1] is based on
Packet Error Rate (PER) measurements
A differential antenna will eliminate the instead of BER. This is a more accurate
need for a balun, and the DC biasing can measurement of the true RF performance
be achieved in the antenna topology. since it mirrors the way the actual system
operates.
34.7 Battery operated systems
It is recommended to perform PER
In low power applications, the CC2420 measurements instead of BER
should be powered down when not being measurements to evaluate the
active. Extremely low power consumption performance of IEEE 802.15.4 systems.
may be achieved when disabling also the To do PER measurements, the following
voltage regulator. This will require may be used as a guideline:
reprogramming of the register and RAM
configuration.  A valid preamble, SFD and length
field must be used for each
34.8 BER / PER measurements packet.

CC2420 includes test modes where data is  The PSDU (see Figure 17 on page
received infinitely and output to pins 36) length should be 20 bytes for
(RX_MODE 2, see page 40). This mode sensitivity measurements as
may be used for Bit Error Rate (BER) specified by [1].
measurements. However, the following
actions must be taken to do such a  The sensitivity limit specified by [1]
measurement: is the RF level resulting in a 1%
PER. The packet sample space
 A preamble and SFD sequence for a given measurement must
must be used, even if pseudo then be >> 100 to have a
random data is transmitted, since sufficiently large sample space.
receiving the DSSS modulated E.g. at least 1000 packets should
signal requires symbol be used to measure the sensitivity.
synchronisation, not bit
synchronisation like e.g. in 2FSK  The data transmitted over air must
systems. The SYNCWORD may be be spread according to [1] and the
set to another value to fit to the description on page 24. Pre-
measurement setup if necessary. generated packets may be used,
although [1] requires that the PER
 The data transmitted over air must is averaged over random PSDU
be spread according to [1] and the data.
description on page 24. This
means that the transmitter used  The CC2420 receive FIFO may be
during measurements must be used to buffer data received
able to do spreading of the bit data during PER measurements, since
to chip data. Remember that the it is able to buffer up to 128 bytes.
chip sequence transmitted by the
test setup is not the same as the  The MDMCTRL1.CORR_THR
bit sequence, which is output by
control register is by default set to
CC2420. 20, as described in the
Demodulator, Symbol
 When operating at or below the Synchroniser and Data Decision
sensitivity limit, CC2420 may loose section.
symbol synchronisation in infinite
receive mode. A new SFD and
restart of the receiver may be
SWRS041c Page 58 of 85
Not Recommended For New Designs
CC2420
 The RXCTRL1.RXBPF_LOCUR signal has the same phase shifts as the O-
control bit should be set to 1. QPSK sequence previously defined.

The simplest way of making a PER For a desired symbol sequence s0, s1, … ,
measurement will be to use another sn-1 of length n symbols, the desired chip
CC2420 as the reference transmitter. sequence c0, c1, c2, …, c32n-1 of length 32n
However, this makes it difficult to measure is found using table lookup from Table 3
the exact receiver performance. on page 24. It can be seen from comparing
the phase shifts of the O-QPSK signal with
Using a signal generator, this may either the frequency of a MSK signal that the
be set up as O-QPSK with half-sine MSK chip sequence is generated as:
shaping or as MSK. If using O-QPSK, the
phases must be selected according to [1]. (c0 xnor c1), (c1 xor c2), (c2 xnor c3), … ,
If using MSK, the chip sequence must be (c32n-1 xor c32n) where c32n may be
modified such that the modulated MSK arbitrarily selected.

35 PCB Layout Recommendations

Following Texas Instruments’s reference vias. Supply power filtering is very

design is highly recommended. important.

In our reference design, the top layer is The external components should be as
used for signal routing, and the open areas small as possible (0402 is recommended)
are filled with metallisation connected to and surface mount devices must be used.
ground using several vias. Layer 2 has not
been used in our CC2420 reference Caution should be used when placing the
designs. Layer 3 is used for power routing microcontroller in order to avoid
and the bottom layer serves as ground interference with the RF circuitry.
plane with a little routing.
A Development Kit with a fully assembled
The area under the chip is used for Evaluation Module is available. It is
grounding and must be well connected to strongly advised that this reference layout
the ground plane with several vias. is followed very closely in order to get the
best performance.
The ground pins should be connected to
ground as close as possible to the The schematic, BOM and layout Gerber
package pin using individual vias. The de- files for the reference designs are all
coupling capacitors should also be placed available from the Texas Instruments
as close as possible to the supply pins and website.
connected to the ground plane by separate

36 Antenna Considerations

CC2420 can be used together with various Other commonly used antennas for short-
types of antennas. A differential antenna range communication are monopole,
like a dipole would be the easiest to helical and loop antennas. The single-
interface not needing a balun (balanced to ended monopole and helical would require
un-balanced transformation network). a balun network between the differential
output and the antenna.
The length of the /2-dipole antenna is
given by: Monopole antennas are resonant antennas
with a length corresponding to one quarter
L = 14250 / f of the electrical wavelength (/4). They are
very easy to design and can be
where f is in MHz, giving the length in cm. implemented simply as a “piece of wire” or
An antenna for 2450 MHz should be 5.8 even integrated into the PCB.
cm. Each arm is therefore 2.9 cm.
SWRS041c Page 59 of 85
Not Recommended For New Designs
CC2420
Helical antennas can be thought of as a
combination of a monopole and a loop
The length of the /4-monopole antenna is antenna. They are a good compromise in
given by: size critical applications. Helical antennas
tend to be more difficult to optimize than
L = 7125 / f the simple monopole.

where f is in MHz, giving the length in cm. Loop antennas are easy to integrate into
An antenna for 2450 MHz should be 2.9 the PCB, but are less effective due to
cm. difficult impedance matching because of
their very low radiation resistance.
Non-resonant monopole antennas shorter
than /4 can also be used, but at the For low power applications the differential
expense of range. In size and cost critical antenna is recommended giving the best
applications such an antenna may very range and because of its simplicity.
well be integrated into the PCB.
The antenna should be connected as
Enclosing the antenna in high dielectric close as possible to the IC. If the antenna
constant material reduces the overall size is located away from the RF pins the
of the antenna. Many vendors offer such antenna should be matched to the feeding
antennas intended for PCB mounting. transmission line (50 ).

SWRS041c Page 60 of 85
Not Recommended For New Designs
CC2420

37 Configuration Registers

The configuration of CC2420 is done by in Table 11. Many of these registers are
programming the 16-bit configuration for test purposes only, and need not be
registers. Complete descriptions of the accessed for normal operation of CC2420.
registers are given in the following tables.
After chip reset (from the RESETn pin or The FIFOs are accessed through two 8-bit
programmable through the MAIN.RESETn registers, TXFIFO and RXFIFO. The
configuration bit), all the registers have TXFIFO register is write only. Data may
default values as shown in the tables. still be read out of the TXFIFO through
regular RAM access (see section RAM
Note that the MAIN register is only reset by access section on page 29), but data is
using the pin reset RESETn. When writing then not removed from the FIFO. Note that
to this register, all bits will get the value the crystal oscillator must be active for all
written, not the default value. This also FIFO and RAM access.
means that the MAIN.RESETn bit must be
written both low and then high to perform a During address transfer, and while data is
chip reset through the serial interface. being written to the TXFIFO, a status byte
is returned on the serial data output pin
15 registers are Strobe Command SO. This status byte is described in Table
Registers, listed first in Table 11 below. 5 on page 29.
Accessing these registers will initiate the
change of an internal state or mode. There All configuration and status registers are
are 33 normal 16-bits registers, also listed described in the tables following Table 11.

Address Register Register type Description

0x00 SNOP S No Operation (has no other effect than reading out status-bits)
0x01 SXOSCON S Turn on the crystal oscillator (set XOSC16M_PD = 0 and
BIAS_PD = 0)
0x02 STXCAL S Enable and calibrate frequency synthesizer for TX;
Go from RX / TX to a wait state where only the synthesizer is
running.
0x03 SRXON S Enable RX
0x04 STXON S Enable TX after calibration (if not already performed)
Start TX in-line encryption if SPI_SEC_MODE  0

0x05 STXONCCA S If CCA indicates a clear channel:

Enable calibration, then TX.
Start in-line encryption if SPI_SEC_MODE  0
else
do nothing
0x06 SRFOFF S Disable RX/TX and frequency synthesizer
0x07 SXOSCOFF S Turn off the crystal oscillator and RF
0x08 SFLUSHRX S Flush the RX FIFO buffer and reset the demodulator. Always
read at least one byte from the RXFIFO before issuing the
SFLUSHRX command strobe

0x09 SFLUSHTX S Flush the TX FIFO buffer

0x0A SACK S Send acknowledge frame, with pending field cleared.
0x0B SACKPEND S Send acknowledge frame, with pending field set.
0x0C SRXDEC S Start RXFIFO in-line decryption / authentication (as set by
SPI_SEC_MODE)
0x0D STXENC S Start TXFIFO in-line encryption / authentication (as set by
SPI_SEC_MODE), without starting TX.

SWRS041c Page 61 of 85
Not Recommended For New Designs
CC2420
Address Register Register type Description

0x0E SAES S AES Stand alone encryption strobe. SPI_SEC_MODE is not

required to be 0, but the encryption module must be idle. If not,
the strobe is ignored.
0x0F - - Not used
0x10 MAIN R/W Main Control Register
0x11 MDMCTRL0 R/W Modem Control Register 0
0x12 MDMCTRL1 R/W Modem Control Register 1
0x13 RSSI R/W RSSI and CCA Status and Control register
0x14 SYNCWORD R/W Synchronisation word control register
0x15 TXCTRL R/W Transmit Control Register
0x16 RXCTRL0 R/W Receive Control Register 0
0x17 RXCTRL1 R/W Receive Control Register 1
0x18 FSCTRL R/W Frequency Synthesizer Control and Status Register
0x19 SECCTRL0 R/W Security Control Register 0
0x1A SECCTRL1 R/W Security Control Register 1
0x1B BATTMON R/W Battery Monitor Control and Status Register
0x1C IOCFG0 R/W Input / Output Control Register 0
0x1D IOCFG1 R/W Input / Output Control Register 1
0x1E MANFIDL R/W Manufacturer ID, Low 16 bits
0x1F MANFIDH R/W Manufacturer ID, High 16 bits
0x20 FSMTC R/W Finite State Machine Time Constants
0x21 MANAND R/W Manual signal AND override register
0x22 MANOR R/W Manual signal OR override register
0x23 AGCCTRL R/W AGC Control Register
0x24 AGCTST0 R/W AGC Test Register 0
0x25 AGCTST1 R/W AGC Test Register 1
0x26 AGCTST2 R/W AGC Test Register 2
0x27 FSTST0 R/W Frequency Synthesizer Test Register 0
0x28 FSTST1 R/W Frequency Synthesizer Test Register 1
0x29 FSTST2 R/W Frequency Synthesizer Test Register 2
0x2A FSTST3 R/W Frequency Synthesizer Test Register 3
0x2B RXBPFTST R/W Receiver Bandpass Filter Test Register
0x2C FSMSTATE R Finite State Machine State Status Register
0x2D ADCTST R/W ADC Test Register
0x2E DACTST R/W DAC Test Register
0x2F TOPTST R/W Top Level Test Register
0x30 RESERVED R/W Reserved for future use control / status register
0x31- Not used
0x3D - -
0x3E TXFIFO W Transmit FIFO Byte Register
0x3F RXFIFO R/W Receiver FIFO Byte Register
R/W - Read/write (control/status), R - Read only, W – Write only, S – Command Strobe (perform action upon
access)
Table 11. Configuration registers overview

SWRS041c Page 62 of 85
Not Recommended For New Designs
CC2420
MAIN (0x10) - Main Control Register

Bit Field Name Reset R/W Description

15 RESETn 1 R/W Active low reset of the entire circuit should be applied before
doing anything else. Equivalent to using the RESETn reset pin.

14 ENC_RESETn 1 R/W Active low reset of the encryption module. (Test purposes only)

13 DEMOD_RESETn 1 R/W Active low reset of the demodulator module. (Test purposes
only)
12 MOD_RESETn 1 R/W Active low reset of the modulator module. (Test purposes only)

11 FS_RESETn 1 R/W Active low reset of the frequency synthesizer module. (Test
purposes only)
10:1 - 0 W0 Reserved, write as 0

0 XOSC16M_BYPASS 0 R/W Bypasses the crystal oscillator and uses a buffered version of
the signal on Q1 directly. This can be used to apply an external
rail-rail clock signal to the Q1 pin.

SWRS041c Page 63 of 85
Not Recommended For New Designs
CC2420
MDMCTRL0 (0x11) - Modem Control Register 0

Bit Field Name Reset R/W Description

15:14 - 0 W0 Reserved, write as 0

13 RESERVED_FRAME_MODE 0 R/W Mode for accepting reserved IEE 802.15.4 frame types when
address recognition is enabled (MDMCTRL0.ADR_DECODE = 1).
0 : Reserved frame types (100, 101, 110, 111) are rejected by
address recognition.
1 : Reserved frame types (100, 101, 110, 111) are always
accepted by address recognition. No further address decoding is
done.
When address recognition is disabled (MDMCTRL0.ADR_DECODE
= 0), all frames are received and RESERVED_FRAME_MODE is
don’t care.
12 PAN_COORDINATOR 0 R/W Should be set high when the device is a PAN Coordinator. Used
for filtering packets with no destination address, as specified in
section 7.5.6.2 in 802.15.4, D18
11 ADR_DECODE 1 R/W Hardware Address decode enable.
0 : Address decoding is disabled
1 : Address decoding is enabled
10:8 CCA_HYST[2:0] 2 R/W CCA Hysteresis in dB, values 0 through 7 dB

7:6 CCA_MODE[1:0] 3 R/W 0 : Reserved

1 : CCA=1 when RSSI_VAL < CCA_THR - CCA_HYST
CCA=0 when RSSI_VAL ≥ CCA_THR
2 : CCA=1 when not receiving valid IEEE 802.15.4 data,
CCA=0 otherwise
3 : CCA=1 when RSSI_VAL < CCA_THR - CCA_HYST and not
receiving valid IEEE 802.15.4 data.
CCA=0 when RSSI_VAL ≥ CCA_THR or receiving a packet

5 AUTOCRC 1 R/W In packet mode a CRC-16 (ITU-T) is calculated and is

transmitted after the last data byte in TX. In RX CRC is
calculated and checked for validity.
4 AUTOACK 0 R/W If AUTOACK is set, all packets accepted by address recognition
with the acknowledge request flag set and a valid CRC are
acknowledged 12 symbol periods after being received.
3:0 PREAMBLE_LENGTH 2 R/W The number of preamble bytes (2 zero-symbols) to be sent in TX
[3:0] mode prior to the SYNCWORD, encoded in steps of 2. The
reset value of 2 is compliant with IEEE 802.15.4, since the 4th
zero byte is included in the SYNCWORD.
0 : 1 leading zero bytes (not recommended)
1 : 2 leading zero bytes (not recommended)
2 : 3 leading zero bytes (IEEE 802.15.4 compliant)
3 : 4 leading zero bytes
…
15 : 16 leading zero bytes

SWRS041c Page 64 of 85
Not Recommended For New Designs
CC2420
MDMCTRL1 (0x12)– Modem Control Register 1

Bit Field Name Reset R/W Description

15:11 - 0 W0 Reserved, write as 0.

10:6 CORR_THR[4:0] 20 R/W Demodulator correlator threshold value, required before SFD
search. Note that on early CC2420 versions the reset value was
0.
5 DEMOD_AVG_MODE 0 R/W Frequency offset average filter behaviour.
0 : Lock frequency offset filter after preamble match
1 : Continuously update frequency offset filter.
4 MODULATION_MODE 0 R/W Set one of two RF modulation modes for RX / TX
0 : IEEE 802.15.4 compliant mode
1 : Reversed phase, non-IEEE compliant (could be used to set
up a system which will not receive 802.15.4 packets)
3:2 TX_MODE[1:0] 0 R/W Set test modes for TX
0 : Buffered mode, use TXFIFO (normal operation)
1 : Serial mode, use transmit data on serial interface, infinite
transmission. For lab testing only.
2 : TXFIFO looping ignore underflow in TXFIFO and read cyclic,
infinite transmission. For lab testing only.
3 : Send random data from CRC, infinite transmission. For lab
testing only.
1:0 RX_MODE[1:0] 0 R/W Set test mode of RX
0 : Buffered mode, use RXFIFO (normal operation)
1 : Receive serial mode, output received data on pins. Infinite
RX. For lab testing only.
2 : RXFIFO looping ignore overflow in RXFIFO and write cyclic,
infinite reception. For lab testing only.
3 : Reserved

RSSI (0x13) - RSSI and CCA Status and Control Register

Bit Field Name Reset R/W Description

15:8 CCA_THR[7:0] -32 R/W Clear Channel Assessment threshold value, signed number on
2’s complement for comparison with the RSSI.
The unit is 1 dB, offset is the same as for RSSI_VAL. The CCA
signal goes active when the received signal is below this value.
The CCA signal is available on the CCA pin.
The reset value is approximately -77 dBm.
7:0 RSSI_VAL[7:0] -128 R RSSI estimate on a logarithmic scale, signed number on 2’s
complement.
Unit is 1 dB, offset is described in the RSSI / Energy Detection
section on page 48.
The RSSI_VAL value is averaged over 8 symbol periods. The
RSSI_VALID status bit may be checked to verify that the
receiver has been enabled for at least 8 symbol periods.
The reset value of –128 also indicates that the RSSI_VAL value
is invalid.

SWRS041c Page 65 of 85
Not Recommended For New Designs
CC2420
SYNCWORD (0x14) - Sync Word

Bit Field Name Reset R/W Description

15:0 SYNCWORD[15:0] 0xA70F R/W Synchronisation word. The SYNCWORD is processed from the
least significant nibble (F at reset) to the most significant
nibble (A at reset).
SYNCWORD is used both during modulation (where 0xF’s are
replaced with 0x0’s) and during demodulation (where 0xF’s are
not required for frame synchronisation). In reception an implicit
zero is required before the first symbol required by SYNCWORD.
The reset value is compliant with IEEE 802.15.4.

TXCTRL (0x15) - Transmit Control Register

Bit Field Name Reset R/W Description

15:14 TXMIXBUF_CUR[1:0] 2 R/W TX mixer buffer bias current.

0: 690uA
1: 980uA
2: 1.16mA (nominal)
3: 1.44mA
13 TX_TURNAROUND 1 R/W Sets the wait time after STXON before transmission is started.
0 : 8 symbol periods (128 us)
1 : 12 symbol periods (192 us)
12:11 TXMIX_CAP_ARRAY[1:0] 0 R/W Selects varactor array settings in the transmit mixers.

10:9 TXMIX_CURRENT[1:0] 0 R/W Transmit mixers current:

0: 1.72 mA
1: 1.88 mA
2: 2.05 mA
3: 2.21 mA
8:6 PA_CURRENT[2:0] 3 R/W Current programming of the PA
0: -3 current adjustment
1: -2 current adjustment
2: -1 current adjustment
3: Nominal setting
4: +1 current adjustment
5: +2 current adjustment
6: +3 current adjustment
7: +4 current adjustment
5 - 1 W1 Reserved, write as 1.

4:0 PA_LEVEL[4:0] 31 R/W Output PA level. (~0 dBm)

SWRS041c Page 66 of 85
Not Recommended For New Designs
CC2420
RXCTRL0 (0x16) – Receive control register 0

Bit Field Name Reset R/W Description

15:14 - 0 W0 Reserved, write as 0.

13:12 RXMIXBUF_CUR[1:0] 1 R/W RX mixer buffer bias current.

0: 690uA
1: 980uA (nominal)
2: 1.16mA
3: 1.44mA
11:10 HIGH_LNA_GAIN[1:0] 0 R/W Controls current in the LNA gain compensation branch in AGC
High gain mode.
0: Compensation disabled
1: 100 µA compensation current
2: 300 µA compensation current (Nominal)
3: 1000 µA compensation current
9:8 MED_LNA_GAIN[1:0] 2 R/W Controls current in the LNA gain compensation branch in AGC
Med gain mode.
7:6 LOW_LNA_GAIN[1:0] 3 R/W Controls current in the LNA gain compensation branch in AGC
Low gain mode
5:4 HIGH_LNA_CURRENT[1:0] 2 R/W Controls main current in the LNA in AGC High gain mode
0: 240 µA LNA current (x2)
1: 480 µA LNA current (x2)
2: 640 µA LNA current (x2)
3: 1280 µA LNA current (x2)
3:2 MED_LNA_CURRENT[1:0] 1 R/W Controls main current in the LNA in AGC Med gain mode

1:0 LOW_LNA_CURRENT[1:0] 1 R/W Controls main current in the LNA in AGC Low gain mode

SWRS041c Page 67 of 85
Not Recommended For New Designs
CC2420
RXCTRL1 (0x17) - Receive control register 1

Bit Field Name Reset R/W Description

15:14 - 0 W0 Reserved, write as 0.

13 RXBPF_LOCUR 0 R/W Controls reference bias current to RX bandpass filters:

0: 4 uA (Reset value) Use 1 instead
1: 3 uA Note: Recommended setting
12 RXBPF_MIDCUR 0 R/W Controls reference bias current to RX bandpass filters:
0: 4 uA (Default)
1: 3.5 uA
11 LOW_LOWGAIN 1 R/W LNA low gain mode setting in AGC low gain mode.

10 MED_LOWGAIN 0 R/W LNA low gain mode setting in AGC medium gain mode.

9 HIGH_HGM 1 R/W RX Mixers high gain mode setting in AGC high gain mode.

8 MED_HGM 0 R/W RX Mixers high gain mode setting in AGC medium gain mode.

7:6 LNA_CAP_ARRAY[1:0] 1 R/W Selects varactor array setting in the LNA

0: OFF
1: 0.1pF (x2) (Nominal)
2: 0.2pF (x2)
3: 0.3pF (x2)
5:4 RXMIX_TAIL[1:0] 1 R/W Control of the receiver mixers output current.
0: 12 µA
1: 16 µA (Nominal)
2: 20 µA
3: 24 µA
3:2 RXMIX_VCM[1:0] 1 R/W Controls VCM level in the mixer feedback loop
0: 8 µA mixer current
1: 12 µA mixer current (Nominal)
2: 16 µA mixer current
3: 20 µA mixer current
1:0 RXMIX_CURRENT[1:0] 2 R/W Controls current in the mixer
0: 360 µA mixer current (x2)
1: 720 µA mixer current (x2)
2: 900 µA mixer current (x2) (Nominal)
3: 1260 µA mixer current (x2)

SWRS041c Page 68 of 85
Not Recommended For New Designs
CC2420
FSCTRL (0x18) - Frequency Synthesizer Control and Status

Bit Field Name Reset R/W Description

15:14 LOCK_THR[1:0] 1 R/W Number of consecutive reference clock periods with successful
synchronisation windows required to indicate lock:
0: 64
1: 128 (recommended)
2: 256
3: 512
13 CAL_DONE 0 R Calibration has been performed since the last time the
frequency synthesizer was turned on.
12 CAL_RUNNING 0 R Calibration status, '1' when calibration in progress and ‘0’
otherwise.
11 LOCK_LENGTH 0 R/W Synchronisation window pulse width:
0: 2 prescaler clock periods (recommended)
1: 4 prescaler clock periods
10 LOCK_STATUS 0 R Frequency synthesizer lock status:
0 : Frequency synthesizer is out of lock
1 : Frequency synthesizer is in lock
9:0 FREQ[9:0] 357 R/W Frequency control word, controlling the RF operating frequency
FC. In transmit mode, the local oscillator (LO) frequency equals
FC. In receive mode, the LO frequency is 2 MHz below FC.
(2405
MHz) FC = 2048 + FREQ[9:0] MHz
See the Frequency and Channel Programming section on page
50 for further information.

SWRS041c Page 69 of 85
Not Recommended For New Designs
CC2420
SECCTRL0 (0x19) - Security Control Register

Bit Field Name Reset R/W Description

15:10 - 0 W0 Reserved, write as 0

9 RXFIFO_PROTECTION 1 R/W Protection enable of the RXFIFO, see description in the RXFIFO
overflow section on page 33. Should be cleared if MAC level
security is not used or is implemented outside CC2420.
8 SEC_CBC_HEAD 1 R/W Defines what to use for the first byte in CBC-MAC (does not
apply to CBC-MAC part of CCM):
0 : Use the first data byte as the first byte into CBC-MAC
1 : Use the length of the data to be authenticated (calculated as
(the packet length field – SEC_TXL – 2) for TX or using
SEC_RXL for RX) as the first byte into CBC-MAC (before the first
data byte).
This bit should be set high for CBC-MAC 802.15.4 inline
security.
7 SEC_SAKEYSEL 1 R/W Stand Alone Key select
0 : Key 0 is used
1 : Key 1 is used
6 SEC_TXKEYSEL 1 R/W TX Key select
0 : Key 0 is used
1 : Key 1 is used
5 SEC_RXKEYSEL 0 R/W RX Key select
0 : Key 0 is used
1 : Key 1 is used
4:2 SEC_M[2:0] 1 R/W Number of bytes in authentication field for CBC-MAC, encoded
as (M-2)/2
0 : Reserved
1:4
2:6
3:8
4 : 10
5 : 12
6 : 14
7 : 16
1:0 SEC_MODE[1:0] 0 R/W Security mode
0 : In-line security is disabled
1 : CBC-MAC
2 : CTR
3 : CCM

SWRS041c Page 70 of 85
Not Recommended For New Designs
CC2420
SECCTRL1 (0x1A) - Security Control Register

Bit Field Name Reset R/W Description

15 - 0 W0 Reserved, write as 0

14:8 SEC_TXL 0 R/W Multi-purpose length byte for TX in-line security operations:
CTR : Number of cleartext bytes between length byte and the
first byte to be encrypted
CBC/MAC : Number of cleartext bytes between length byte and
the first byte to be authenticated
CCM : l(a), defining the number of bytes to be authenticated but
not encrypted
Stand-alone : SEC_TXL has no effect
7 - 0 W0 Reserved, write as 0

6:0 SEC_RXL 0 R/W Multi-purpose length byte for RX in-line security operations:
CTR : Number of cleartext bytes between length byte and the
first byte to be decrypted
CBC/MAC : Number of cleartext bytes between length byte and
the first byte to be authenticated
CCM : l(a), defining the number of bytes to be authenticated but
not decrypted
Stand-alone : SEC_RXL has no effect

BATTMON (0x1B) – Battery Monitor Control register

Bit Field Name Reset R/W Description

15:7 - 0 W0 Reserved, write as 0

6 BATTMON_OK 1 R Battery monitor comparator output, read only. BATT_OK is valid

5 us after BATTMON_EN has been asserted and
BATTMON_VOLTAGE has been programmed.
0 : Power supply < Toggle Voltage
1 : Power supply > Toggle Voltage
5 BATTMON_EN 0 R/W Battery monitor enable
0 : Battery monitor is disabled
1 : Battery monitor is enabled
4:0 BATTMON_VOLTAGE 0 R/W Battery monitor toggle voltage. The toggle voltage is given by:
[4:0]
72  BATTMON_VO LTAGE
V toggle
 1.25 V 
27

SWRS041c Page 71 of 85
Not Recommended For New Designs
CC2420
IOCFG0 (0x1C) – I/O Configuration Register 0

Bit Field Name Reset R/W Description

15:12 - 0 W0 Reserved, write as 0

11 BCN_ACCEPT 0 R/W Accept all beacon frames when address recognition is enabled.
This bit should be set when the PAN identifier programmed into
CC2420 RAM is equal to 0xFFFF and cleared otherwise. This bit
is don't care when MDMCTRL0.ADR_DECODE = 0.
0 : Only accept beacons with a source PAN identifier which
matches the PAN identifier programmed into CC2420 RAM
1 : Accept all beacons regardless of the source PAN identifier
10 FIFO_POLARITY 0 R/W Polarity of the output signal FIFO.
0 : Polarity is active high
1 : Polarity is active low
9 FIFOP_POLARITY 0 R/W Polarity of the output signal FIFOP.
0 : Polarity is active high
1 : Polarity is active low
8 SFD_POLARITY 0 R/W Polarity of the SFD pin.
0 : Polarity is active high
1 : Polarity is active low
7 CCA_POLARITY 0 R/W Polarity of the CCA pin.
0 : Polarity is active high
1 : Polarity is active low
6:0 FIFOP_THR[6:0] 64 R/W FIFOP_THR sets the threshold in number of bytes in the
RXFIFO for FIFOP to go active.

SWRS041c Page 72 of 85
Not Recommended For New Designs
CC2420
IOCFG1 (0x1D) – I/O Configuration Register 1

Bit Field Name Reset R/W Description

15:13 - 0 W0 Reserved, write as 0

12:10 HSSD_SRC[2:0] 0 R/W The HSSD module is used as follows:

0: Off.
1: Output AGC status (gain setting / peak detector status /
accumulator value)
2: Output ADC I and Q values.
3: Output I/Q after digital down mix and channel filtering.
4: Reserved
5: Reserved
6: Input ADC I and Q values
7: Input DAC I and Q values.
The HSSD module requires that the FS is up and running as it
uses CLK_PRE (~150 MHZ) to produce its ~37.5 MHz data
clock and serialize its output words.
9:5 SFDMUX[4:0] 0 R/W Multiplexer setting for the SFD pin.
4:0 CCAMUX[4:0] 0 R/W Multiplexer setting for the CCA pin.

MANFIDL (0x1E) - Manufacturer ID, Lower 16 Bit

Bit Field Name Reset R/W Description

15:12 PARTNUM[3:0] 2 R The device part number. CC2420 has part number 0x002.

11:0 MANFID[11:0] 0x33D R Gives the JEDEC manufacturer ID. The actual manufacturer ID
can be found in MANIFID[7:1], the number of continuation bytes
in MANFID[11:8] and MANFID[0]=1.
Chipcon's JEDEC manufacturer ID is 0x7F 0x7F 0x7F 0x9E
(0x1E preceded by three continuation bytes.)

MANFIDH (0x1F) - Manufacturer ID, Upper 16 Bit

Bit Field Name Reset R/W Description

15:12 VERSION[3:0] 3 R Version number. Current version is 3.

Note that previous CC2420 versions will have lower reset
values.
11:0 PARTNUM[15:4] 0 R The device part number. CC2420 has part number 0x002.

FSMTC (0x20) - Finite state machine time constants

Bit Field Name Reset R/W Description

15:13 TC_RXCHAIN2RX[2:0] 3 R/W The time in 5 us steps between the time the RX chain is enabled
and the demodulator and AGC is enabled. The RX chain is
started when the bandpass filter has been calibrated (after 6.5
symbol periods).
12:10 TC_SWITCH2TX[2:0] 6 R/W The time in advance the RXTX switch is set high, before
enabling TX. In s.
9:6 TC_PAON2TX[3:0] 10 R/W The time in advance the PA is powered up before enabling TX.
In s.
5:3 TC_TXEND2SWITCH[2:0] 2 R/W The time after the last chip in the packet is sent, and the TXRX
switch is disabled. In s.
2:0 TC_TXEND2PAOFF[2:0] 4 R/W The time after the last chip in the packet is sent, and the PA is
set in power-down. Also the time at which the modulator is
disabled. In s.

SWRS041c Page 73 of 85
Not Recommended For New Designs
CC2420
1
MANAND (0x21) - Manual signal AND override register

Bit Field Name Reset R/W Description

15 VGA_RESET_N 1 R/W The VGA_RESET_N signal is used to reset the peak detectors
in the VGA in the RX chain.
14 BIAS_PD 1 R/W Global bias power down (1)

13 BALUN_CTRL 1 R/W The BALUN_CTRL signal controls whether the PA should

receive its required external biasing (1) or not (0) by controlling
the RX/TX output switch.
12 RXTX 1 R/W RXTX signal: controls whether the LO buffers (0) or PA buffers
(1) should be used.
11 PRE_PD 1 R/W Powerdown of prescaler.

10 PA_N_PD 1 R/W Powerdown of PA (negative path).

9 PA_P_PD 1 R/W Powerdown of PA (positive path). When PA_N_PD=1 and

PA_P_PD=1 the up-conversion mixers are in powerdown.
8 DAC_LPF_PD 1 R/W Powerdown of TX DACs.

7 XOSC16M_PD 1 R/W
6 RXBPF_CAL_PD 1 R/W Powerdown control of complex bandpass receive filter
calibration oscillator.
5 CHP_PD 1 R/W Powerdown control of charge pump.

4 FS_PD 1 R/W Powerdown control of VCO, I/Q generator, LO buffers.

3 ADC_PD 1 R/W Powerdown control of the ADCs.

2 VGA_PD 1 R/W Powerdown control of the VGA.

1 RXBPF_PD 1 R/W Powerdown control of complex bandpass receive filter.

0 LNAMIX_PD 1 R/W Powerdown control of LNA, down-conversion mixers and front-

end bias.

1
For some important signals the value used by analog and digital modules can be overridden manually. This is done
as follows for the hypothetical important signal IS:
IS_USED = (IS * IS_AND_MASK) + IS_OR_MASK,
using boolean notation.
The AND-mask and OR-mask for the important signals listed resides in the MANAND and MANOR registers,
respectively.
Examples:
 Writing 0xFFFE to MANAND and 0x0000 to MANOR will force LNAMIX_PD0 whereas all other signals will be
unaffected.
 Writing 0xFFFF to MANAND and 0x0001 to MANOR will force LNAMIX_PD1 whereas all other signals will be
unaffected.

SWRS041c Page 74 of 85
Not Recommended For New Designs
CC2420
MANOR (0x22) - Manual signal OR override register

Bit Field Name Reset R/W Description

15 VGA_RESET_N 0 R/W The VGA_RESET_N signal is used to reset the peak detectors in
the VGA in the RX chain.
14 BIAS_PD 0 R/W Global Bias power down (1)

13 BALUN_CTRL 0 R/W The BALUN_CTRL signal controls whether the PA should receive
its required external biasing (1) or not (0) by controlling the
RX/TX output switch.
12 RXTX 0 R/W RXTX signal: controls whether the LO buffers (0) or PA buffers
(1) should be used.
11 PRE_PD 0 R/W Powerdown of prescaler.

10 PA_N_PD 0 R/W Powerdown of PA (negative path).

9 PA_P_PD 0 R/W Powerdown of PA (positive path). When PA_N_PD=1 and

PA_P_PD=1 the up-conversion mixers are in powerdown.
8 DAC_LPF_PD 0 R/W Powerdown of TX DACs.

7 XOSC16M_PD 0
6 RXBPF_CAL_PD 0 R/W Powerdown control of complex bandpass receive filter
calibration oscillator.
5 CHP_PD 0 R/W Powerdown control of charge pump.

4 FS_PD 0 R/W Powerdown control of VCO, I/Q generator, LO buffers.

3 ADC_PD 0 R/W Powerdown control of the ADCs.

2 VGA_PD 0 R/W Powerdown control of the VGA.

1 RXBPF_PD 0 R/W Powerdown control of complex bandpass receive filter.

0 LNAMIX_PD 0 R/W Powerdown control of LNA, down-conversion mixers and front-

end bias.

AGCCTRL (0x23) - AGC Control

Bit Field Name Reset R/W Description

15:12 - 0 W0 Reserved, write as 0

11 VGA_GAIN_OE 0 R/W Use the VGA_GAIN value during RX instead of the AGC value.

10:4 VGA_GAIN [6:0] 0x7F R/W When written, VGA manual gain override value; when read, the
currently used VGA gain setting.
3:2 LNAMIX_GAINMODE_O 0 R/W LNA / Mixer Gain mode override setting
[1:0]
0 : Gain mode is set by AGC algorithm
1 : Gain mode is always low-gain
2 : Gain mode is always med-gain
3 : Gain mode is always high-gain
1:0 LNAMIX_GAINMODE 3 R Status bit, defining the currently selected gain mode selected by
[1:0] the AGC or overridden by the LNAMIX_GAINMODE_O setting.

SWRS041c Page 75 of 85
Not Recommended For New Designs
CC2420

AGCTST0 (0x24) - AGC Test Register 0

Bit Field Name Reset R/W Description

15:12 LNAMIX_HYST[3:0] 3 R/W Hysteresis on the switching between different RF front-end

gain modes, defined in 2 dB steps
11:6 LNAMIX_THR_H[5:0] 25 R/W Threshold for switching between medium and high RF front-
end gain mode, defined in 2 dB steps
5:0 LNAMIX_THR_L[5:0] 9 R/W Threshold for switching between low and medium RF front-
end gain mode, defined in 2 dB steps

AGCTST1 (0x25) - AGC Test Register 1

Bit Field Name Reset R/W Description

15 - 0 W0 Reserved, write as 0

14 AGC_BLANK_MODE 0 R/W Set the VGA blanking mode when switching out a gain stage
When VGA_GAIN_OE = 0:
0 : Blanking is performed when the AGC algorithm switches
out one or more 14dB gain stages.
1 : Blanking is never performed.
When VGA_GAIN_OE = 1:
Blanking is performed when AGC_BLANK_MODE=1

13 PEAKDET_CUR_BOOST 0 R/W Doubles the bias current in the peak-detectors in-between the
VGA stages when set.
12:11 AGC_SETTLE_WAIT[1:0] 1 R/W Timing for AGC to wait for analog gain to settle.

10:8 AGC_PEAK_DET_MODE 0 R/W Sets the AGC mode for use of the VGA peak detectors:
[2:0]
Bit 2 : Digital ADC peak detector enable / disable
Bit 1 : Analog fixed stages peak detector enable /
disable
Bit 0 : Analog variable gain stage peak detector enable /
disable
7:6 AGC_WIN_SIZE[1:0] 1 R/W Window size for the accumulate and dump function in the
AGC.
0 : 8 samples
1 : 16 samples
2 : 32 samples
3 : 64 samples
5:0 AGC_REF[5:0] 20 R/W Target value for the AGC control loop, given in 2 dB steps.
Reset value corresponds to approximately 25% of the ADC
dynamic range in reception.

AGCTST2 (0x26) - AGC Test Register 2

Bit Field Name Reset R/W Description

15:10 - 0 W0 Reserved, write as 0

9:5 MED2HIGHGAIN[4:0] 9 R/W MED2HIGHGAIN sets the difference in the receiver

LNA/MIXER gain from medium gain mode to high gain mode,
used by the AGC for setting the correct front-end gain mode.
4:0 LOW2MEDGAIN[4:0] 10 R/W LOW2MEDGAIN sets the difference in the receiver
LNA/MIXER gain from low gain mode to medium gain mode,
used by the AGC for setting the correct front-end gain mode.

SWRS041c Page 76 of 85
Not Recommended For New Designs
CC2420
FSTST0 (0x27) - Frequency Synthesizer Test Register 0

Bit Field Name Reset R/W Description

15:12 - 0 W0 Reserved, write as 0

11 VCO_ARRAY_SETTLE_LONG 0 R/W When '1' this control bit doubles the time allowed for VCO
settling during VCO calibration.
10 VCO_ARRAY_OE 0 R/W VCO array manual override enable.

9:5 VCO_ARRAY_O[4:0] 16 R/W VCO array override value.

4:0 VCO_ARRAY_RES[4:0] 16 R The VCO array result holds the register content of the most
recent calibration.

FSTST1 (0x28) - Frequency Synthesizer Test Register 1

Bit Field Name Reset R/W Description

15 VCO_TX_NOCAL 0 R/W 0 : VCO calibration is always performed when going to RX or

when going to TX.
1 : VCO calibration is only performed when going to RX or when
using the STXCAL command strobe
14 VCO_ARRAY_CAL_LONG 1 R/W When ‘1’ this control bit doubles the time allowed for VCO
frequency measurements during VCO calibration.
0 : PLL Calibration time is 37 us
1 : PLL Calibration time is 57 us
13:10 VCO_CURRENT_REF[3:0] 4 R/W The value of the reference current calibrated against during
VCO calibration.
9:4 VCO_CURRENT_K[5:0] 0 R/W VCO current calibration constant. (Current B override value
when FSTST2.VCO_CURRENT_OE=1.)
3 VC_DAC_EN 0 R/W Controls the source of the VCO VC node in normal operation
(TOPTST.VC_IN_TEST_EN=0):
0: Loop filter (closed loop PLL)
1: VC DAC (open loop PLL)
2:0 VC_DAC_VAL[2:0] 2 R/W VC DAC output value

FSTST2 (0x29) - Frequency Synthesizer Test Register 2

Bit Field Name Reset R/W Description

15 - 0 W0 Reserved, write as 0.

14:13 VCO_CURCAL_SPEED[1:0] 0 R/W VCO current calibration speed:

0: Normal
1: Double speed
2: Half speed
3: Undefined.
12 VCO_CURRENT_OE 0 R/W VCO current manual override enable.

11:6 VCO_CURRENT_O[5:0] 24 R/W VCO current override value (current A).

5:0 VCO_CURRENT_RES[5:0] 32 R The VCO current result holds the register content of the most
recent calibration.

SWRS041c Page 77 of 85
Not Recommended For New Designs
CC2420
FSTST3 (0x2A) - Frequency Synthesizer Test Register 3

Bit Field Name Reset R/W Description

15 CHP_CAL_DISABLE 1 R/W Disable charge pump during VCO calibration when set.

14 CHP_CURRENT_OE 0 R/W Charge pump current override enable

0 : Charge pump current set by calibration
1 : Charge pump current set by START_CHP_CURRENT
13 CHP_TEST_UP 0 R/W Forces the CHP to output "up" current when set

12 CHP_TEST_DN 0 R/W Forces the CHP to output "down" current when set

11 CHP_DISABLE 0 R/W Set to manually disable charge pump by masking the up and
down pulses from the phase-detector.
10 PD_DELAY 0 R/W Selects short or long reset delay in phase detector:
0: Short reset delay
1: Long reset delay
9:8 CHP_STEP_PERIOD[1:0] 2 R/W The charge pump current value step period:
0: 0.25 us
1: 0.5 us
2: 1 us
3: 4 us
7:4 STOP_CHP_CURRENT[3:0] 13 R/W The charge pump current to stop at after the current is stepped
down from START_CHP_CURRENT after VCO calibration is
complete. The current is stepped down periodically with intervals
as defined in CHP_STEP_PERIOD.
3:0 START_CHP_CURRENT[3:0] 13 R/W The charge pump current to start with after VCO calibration is
complete. The current is then stepped down periodically to the
value STOP_CHP_CURRENT with intervals as defined in
CHP_STEP_PERIOD.
Also used for overriding the charge pump current when
CHP_CURRENT_OE=’1’

RXBPFTST (0x2B) - Receiver Bandpass Filters Test Register

Bit Field Name Reset R/W Description

15 - 0 W0 Reserved, write as 0.

14 RXBPF_CAP_OE 0 R/W RX bandpass filter capacitance calibration override enable.

13:7 RXBPF_CAP_O[6:0] 0 R/W RX bandpass filter capacitance calibration override value.

6:0 RXBPF_CAP_RES[6:0] 0 R RX bandpass filter capacitance calibration result.

0: Minimum capacitance in the feedback.
1: Second smallest capacitance setting.
…
127: Maximum capacitance in the feedback.

FSMSTATE (0x2C) - Finite state machine information

Bit Field Name Reset R/W Description

15:6 - 0 W0 Reserved, write as 0.

5:0 FSM_CUR_STATE[5:0] 0 R Provides the current state of the FIFO and Frame Control
(FFCTRL) finite state machine. See the Radio control state
machine section on page 43 for details.

SWRS041c Page 78 of 85
Not Recommended For New Designs
CC2420
ADCTST (0x2D) - ADC Test Register

Bit Field Name Reset R/W Description

15 ADC_CLOCK_DISABLE 0 R/W ADC Clock Disable

0 : Clock enabled when ADC enabled
1 : Clock disabled, even if ADC is enabled
14:8 ADC_I[6:0] 0 R Read the current ADC I-branch value.

7 - 0 W0 Reserved, write as 0.

6:0 ADC_Q[6:0] 0 R Read the current ADC Q-branch value.

DACTST (0x2E) - DAC Test Register

Bit Field Name Reset R/W Description

15 - 0 W0 Reserved, write as 0.

14:12 DAC_SRC[2:0] 0 R/W The TX DACs data source is selected by DAC_SRC according
to:
0: Normal operation (from modulator).
1: The DAC_I_O and DAC_Q_O override values below.-
2: From ADC, most significant bits
3: I/Q after digital down mixing and channel filtering.
4: Full-spectrum White Noise (from CRC)
5: From ADC, least significant bits
6: RSSI / Cordic Magnitude Output
7: HSSD module.
This feature will often require the DACs to be manually turned
on in MANOR and TOPTST.ATESTMOD_MODE=4.
11:6 DAC_I_O[5:0] 0 R/W I-branch DAC override value.

5:0 DAC_Q_O[5:0] 0 R/W Q-branch DAC override value.

SWRS041c Page 79 of 85
Not Recommended For New Designs
CC2420
TOPTST (0x2F) - Top Level Test Register

Bit Field Name Reset R/W Description

15:8 - 0 W0 Reserved, write as 0.

7 RAM_BIST_RUN 0 R/W Enable BIST of the RAM

0 : RAM BIST disabled, normal operation
1 : RAM BIST Enabled. Result output to pin, as set in IOCFG1.
6 TEST_BATTMON_EN 0 R/W Enable test output of the battery monitor.

5 VC_IN_TEST_EN 0 R/W When ATESTMOD_MODE=7 this controls whether the ATEST2

in is used to output the VC node voltage (0) or to control the VC
node voltage (1).
4 ATESTMOD_PD 1 R/W Powerdown of analog test module.
0 : Power up
1 : Power down
3:0 ATESTMOD_MODE[3:0] 0 When ATESTMOD_PD=0, the function of the analog test module
is as follows:
0: Outputs “I” (ATEST1) and “Q” (ATEST2) from RxMIX.
1: Inputs “I” (ATEST2) and “Q” (ATEST1) to BPF.
2: Outputs “I” (ATEST1) and “Q” (ATEST2) from VGA.
3: Inputs “I” (ATEST2) and “Q” (ATEST1) to ADC.
4: Outputs “I” (ATEST1) and “Q” (ATEST2) from LPF.
5: Inputs “I” (ATEST2) and “Q” (ATEST1) to TxMIX.
6: Outputs “P” (ATEST1) and “N” (ATEST2) from Prescaler. Must
be terminated externally.
7: Connects TX IF to RX IF and simultaneously the ATEST1 pin
to the internal VC node (see VC_IN_TEST_EN).
8. Connect ATEST1 (input) to ATEST2 (output) through
single2diff and diff2single buffers, used for measurements on
the test-interface

RESERVED (0x30) - Reserved register containing spare control and status bits

Bit Field Name Reset R/W Description

15:0 RES[15:0] 0 R/W Reserved for future use

TXFIFO (0x3E) – Transmit FIFO Byte register

Bit Field Name Reset R/W Description

7:0 TXFIFO[7:0] 0 W Transmit FIFO byte register, write only. Reading the TXFIFO is
only possible using RAM read. Note that the crystal oscillator
must be running for writing to the TXFIFO.

RXFIFO (0x3F) – Receive FIFO Byte register

Bit Field Name Reset R/W Description

7:0 RXFIFO[7:0] 0 R/W Receive FIFO byte register, read / write. Note that the crystal
oscillator must be running for accessing the RXFIFO.

SWRS041c Page 80 of 85
Not Recommended For New Designs
CC2420

38 Test Output Signals

The two digital output pins CCA and SFD, IOCFG1.SFDMUX. This is summarized in
can be set up to output test signals defined Table 12 and Table 13 below.
by IOCFG1.CCAMUX and

CCAMUX Signal output on CCA pin Description

0 CCA Normal operation

1 ADC_Q[0] ADC, Q-branch, LSB used for random number generation
2 DEMOD_RESYNC_LATE High one 16 MHz clock cycle each time the demodulator
resynchronises late
3 LOCK_STATUS Lock status, same as FSCTRL.LOCK_STATUS

4 MOD_CHIPCLK Chip rate clock signal during transmission

5 MOD_SERIAL_CLK Bit rate clock signal during transmission
6 FFCTRL_FS_PD Frequency synthesizer power down, active high
7 FFCTRL_ADC_PD ADC power down, active high
8 FFCTRL_VGA_PD VGA power down, active high
9 FFCTRL_RXBPF_PD Receiver bandpass filter power down, active high
10 FFCTRL_LNAMIX_PD Receiver LNA / Mixer power down, active high
11 FFCTRL_PA_P_PD Power amplifier power down, active high
12 AGC_UPDATE High one 16 MHz clock cycle each time the AGC updates its gain
setting
13 VGA_PEAK_DET[1] VGA Peak detector, gain stage 1
14 VGA_PEAK_DET[3] VGA Peak detector, gain stage 3
15 AGC_LNAMIX_GAINMODE[1] RF receiver front-end gain mode, bit 1
16 AGC_VGA_GAIN[1] VGA gain setting, bit 1
17 VGA_RESET_N VGA peak-detector reset sign, active low.
18 - Reserved
19 - Reserved
20 - Reserved
21 - Reserved
22 - Reserved
23 CLK_8M 8 MHz clock signal output
24 XOSC16M_STABLE 16 MHz crystal oscillator stabilised, same as the status bit in
Table 5
25 FSDIG_FREF Frequency synthesizer, 4 MHz reference signal
26 FSDIG_FPLL Frequency synthesizer, 4 MHz divided signal
27 FSDIG_LOCK_WINDOW Frequency synthesizer, lock window
28 WINDOW_SYNC Frequency synthesizer, synchronized lock window
29 CLK_ADC ADC clock signal 1
30 ZERO Low
31 ONE High
Table 12. CCA test signal select table

SWRS041c Page 81 of 85
Not Recommended For New Designs
CC2420
SFDMUX Signal output on SFD pin Description

0 SFD Normal operation

1 ADC_I[0] ADC, I-branch, LSB used for random number generation
2 DEMOD_RESYNCH_EARLY High one 16 MHz clock cycle each time the demodulator
resynchronises early
3 LOCK_STATUS Lock status, same as FSCTRL.LOCK_STATUS

4 MOD_CHIP Chip rate data signal during transmission

5 MOD_SERIAL_DATA_OUT Bit rate data signal during transmission
6 FFCTRL_FS_PD Frequency synthesizer power down, active high
7 FFCTRL_ADC_PD ADC power down, active high
8 FFCTRL_VGA_PD VGA power down, active high
9 FFCTRL_RXBPF_PD Receiver bandpass filter power down, active high
10 FFCTRL_LNAMIX_PD Receiver LNA / Mixer power down, active high
11 FFCTRL_PA_P_PD Power amplifier power down, active high
12 VGA_PEAK_DET[0] VGA Peak detector, gain stage 0
13 VGA_PEAK_DET[2] VGA Peak detector, gain stage 2
14 VGA_PEAK_DET[4] VGA Peak detector, gain stage 4
15 AGC_LNAMIX_GAINMODE[0] RF receiver front-end gain mode, bit 0
16 AGC_VGA_GAIN[0] VGA gain setting, bit 0
17 RXBPF_CAL_CLK Receiver bandpass filter calibration clock
18 - Reserved
19 - Reserved
20 - Reserved
21 - Reserved
22 - Reserved
23 - Reserved
24 PD_F_COMP Frequency synthesizer frequency comparator value
25 FSDIG_FREF Frequency synthesizer, 4 MHz reference signal
26 FSDIG_FPLL Frequency synthesizer, 4 MHz divided signal
27 FSDIG_LOCK_WINDOW Frequency synthesizer, lock window
28 WINDOW_SYNC Frequency synthesizer, synchronized lock window
29 CLK_ADC_DIG ADC clock signal 2
30 ZERO Low
31 ONE High
Table 13. SFD test signal select table

SWRS041c Page 82 of 85
Not Recommended For New Designs
CC2420

39 Soldering information

Recommended soldering profile is according to IPC/JEDEC J-STD-020C. Please see the

CC2420EM reference design for details on layout.

SWRS041c Page 83 of 85
Not Recommended For New Designs
CC2420

40 General Information

40.1 Document History

Revision Date Description/Changes

SWRS041c 2013-02-20 Changed packaging and orderable information to reflect change to RGZ package.

SWRS041b 2007-03-19 Slightly changed optimum load impedance on Page 9 and 19 to better describe the
Application circuit.

SWRS041a 2006-12-18 Updated ordering information.

Updated address information.
Typical data latency changed from 2 to 3 us.
Updates reflecting the programmable polarity of FIFO, FIFOP, SFD and CCA pins.
Clarification relating to VREG_EN as digital input.
BATT_OK changed to BATTMON_OK for consistency.
MANFIDH.VERSION register, reset value changed to ”current version is 3”.
Added reset values for several registers.
Some typographical changes.
Removed Chipcon specific Disclaimer, Trademarks and Life Support Policy sections.
SWRS041 2006-04-06 Ordering part number changed from CC2420-RTB2 and CC2420-RTR2 to CC2420Z-
RTB1 and CC2420Z-RTR1 respectively.
(1.4)
1.3 2005-10-03 Important: New recommended setting for RXBPF_LOCUR in RXCTRL1 (0x17) use 1
instead of reset value 0.
Updated address information.
Added new balun circuit with transmission lines in section Application Circuit.
Updated electrical specifications with measured data on CC2420 EM with new balun.
Updated values and figure for suggested application circuit with folded dipole
antenna.
Corrected values for capacitors in Table 2, discrete balun.
Added data latency figure in receiver specification.
Updated crystal oscillator start up time.
Updated PLL loop filter bandwidth.
Updated adjacent channel rejection figures.
Updated current consumption for RX mode.
Typographical errors corrected in text and figures.
Removed comment about tuning capacitor for crystal oscillator.
Added statement that RAM access shall not be used for FIFO access.
Added more details about RSSI.
Clarified the interpretation of a programmed synchronisation word.
Updated purchasing information.
Updated soldering standard.
Added chapter numbering and split table for electrical specifications for readability.
Gathered and added information related to pin configurations in section 13.
Included TX_UNDERFLOW and RX_UNDERFLOW in state diagram.
Disclaimer updated to include Z-stack TM information.
Product status changed to “Full Production”.

SWRS041c Page 84 of 85
Not Recommended For New Designs
CC2420
Revision Date Description/Changes

1.2 2004-06-09 Output power range: 24 dB (was 40 dB).

Deleted option for single ended external PA.
Adjacent channel rejection corrected to 46 dB for + 5MHz (was 39 dB), 39 dB for –5
MHz (was 46 dB) 58 dB for +10 MHz (was 53 dB) and 55 dB for-10 MHz (was 57 dB).
“image channel” deleted in text for In band spurious reception.
Revision for reference [1] updated.
CSMA-CA added to abbreviations.
Schematic view of the IEEE 802.15.4 Frame Format corrected, address field 0 to 20
bits.
Changed blocking specifications to relate to EN 300 440 class 2.
Updated addresses for Chipcon offices.
Added section Operating Conditions.
Section RAM access: A6:0 (LSB).
IOCFG0.BCN_ACCEPT bit added and described in section Address recognition and
the IOCFG0 register.
The previous IDLE mode has been renamed to power down to be consistent with
other Chipcon data sheets. Three power modes defined: Voltage regulator off (OFF),
Power down (PD) (Voltage regulator enabled), IDLE (XOSC running) and used
throughout the document.
Default TXMIXBUF_CUR[1:0] in table for TXCTRL set to 2.
Added information: compliance with EN 300 328 og EN 300 440 (Class 2).
Added more information about FIFOP in section Receive mode.
Removed text about SO programmable pull up from entire document.
In Voltage regulator section of Electrical Specifications: voltage regulator may only
supply CC2420.
MANFIDH.VERSION register, changed to ”current version is 2”.
Included package height in package drawing.
Included layout drawing for package.
Power supply pins defined clearer in Absolute maximum ratings.
Third harmonic level corrected to –51dBm in Electrical specifications, second
harmonic to –37dBm.
Table with Crystal oscillator component values corrected.
Link to reference [3] corrected.
Corrected spelling grammar and references to tables and figures.
Figure showing SmartRF Studio user interface included.
Added figure to describe pin activity during RXFIFO read out.
Added description on how to connect pins when not using internal regulator.
1.1 2004-03-22 Application circuits: Pin 20 and pin 37 connected to 1.8 V from VREG_OUT.
IOCFG0.SO_PULLUP deleted.
Added document history table.

1.0 2003-11-17 Initial release.

SWRS041c Page 85 of 85
PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CC2420RGZR NRND VQFN RGZ 48 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 CC2420
& no Sb/Br)
CC2420RGZT NRND VQFN RGZ 48 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 CC2420
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 15-Apr-2017

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 12-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC2420RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
CC2420RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 12-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CC2420RGZR VQFN RGZ 48 2500 350.0 350.0 43.0
CC2420RGZT VQFN RGZ 48 250 213.0 191.0 55.0

Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGZ 48 VQFN - 1 mm max height
7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224671/A

www.ti.com
PACKAGE OUTLINE
RGZ0048A VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD

7.1 A
B 6.9

7.1
PIN 1 INDEX AREA 6.9

(0.1) TYP

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS

1 MAX
C

SEATING PLANE
0.05 0.08 C
0.00
2X 5.5

5.15±0.1 (0.2) TYP

13 24
44X 0.5
12
25
SEE SIDE WALL
DETAIL

2X SYMM
5.5

1 36
PIN1 ID 48X 0.30
0.18
48 37
(OPTIONAL)
SYMM 0.1 C A B
48X 0.5
0.3 0.05 C

4219044/B 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
EXAMPLE BOARD LAYOUT
RGZ0048A VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD

2X (6.8)
( 5.15)
SYMM
48X (0.6) 48 35

48X (0.24)

44X (0.5) 1
34

2X SYMM 2X
(5.5) (6.8)

2X
(1.26)

2X
(1.065)

(R0.05)
TYP
23
12
21X (Ø0.2) VIA
TYP

13 22
2X (1.26) 2X (1.065)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X

0.07 MAX 0.07 MIN SOLDER MASK

ALL AROUND ALL AROUND OPENING

EXPOSED METAL EXPOSED METAL

METAL
SOLDER MASK METAL UNDER
OPENING NON SOLDER MASK SOLDER MASK
SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4219044/B 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
EXAMPLE STENCIL DESIGN
RGZ0048A VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD

2X (6.8)
SYMM ( 1.06)
48X (0.6)

48X (0.24)

44X (0.5)

2X SYMM 2X
(5.5) 2X (6.8)
(0.63)

2X
(1.26)

(R0.05)
TYP

2X
2X (0.63)
(1.26)
2X (5.5)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X

4219044/B 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated