Department of Electronics and Communication Engineering

The National Institute of Engineering

Mysuru - 570008

Minor Project Presentation

Phase 1

A 45nm CMOS PHASE LOCKED LOOP For 5G mobile Communications

Under the guidance of:
Dr. Remya Jayachandran, Assistant Professor

Submitted by :
Ankitha A Renjal (4NI22EC009)
Chandrashekar A R (4NI22EC022)
Disha L(4NI22EC028)
Ksheeraj S K(4NI22EC041)

V Semester B.E
2024-2025

04/12/2024 1
INTRODUCTION

• A Phase Locked Loop (PLL) is a key component in communication systems, crucial for frequency synthesis,

clock generation, and signal modulation. In 5G, PLLs ensure that the communication signals remain

synchronized with high precision.

• The 45nm CMOS process is a mature, cost-effective technology node that offers a balance between

performance and power efficiency. It allows for higher speed and integration levels, which are essential for

handling the high-frequency demands of 5G communication.

• In the design of a 45nm CMOS PLL for 5G, both the charge pump and PFD must be optimized for high-speed

operation with minimal power consumption and phase noise. The low power and high accuracy of these

components directly impact the performance of the entire PLL system, ensuring that it meets the stringent

requirements of 5G, such as low phase noise and fast settling time.

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Phase lock loop-PLL

• A control system that generates an output signal whose phase is fixed relative to the phase of an input
signal.

• Basic elements are phase detector, low pass filter, voltage controlled oscillator and feedback path.

• WORKING:

Whenever loop is turned on, VCO runs at fo(free running frequency), now phase detector refers the
input frequency(fin) with oscillator frequency(fo), based on that it generates error signal(E(t)). Now this
error signal is passed to LPF, it generates error voltage(Ev) based on the error signal. Based on this Ev,
VCO either increases or decreases the fo until the fo locks the fin. Under lock condition, no phase
difference or constant phase difference between two signals.

• Loop in lock condition : f0=fin and ΔФ=0 or constant.

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Observations:

Free-running frequency observed : 3.36khz.

Upper limit of lock range: 4.57khz.
Upper limit of pll capture range: 3.45khz.
Lower limit of lock range: 2.82khz.
Lower limit of pll capture range: 3.27khz.

From these observations, we can say that:

Pll lock range : 1.75khz

PLL capture range : 0.18khz

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• Ratings:

 Supply Voltage: ±12V

 Power Dissipation: 1400 mW

 Differential Input Voltage: ±1V

 Operating Temperature Range: 0°C to +70°C

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Technical Specifications of PLL:

PLL Parameters:
• Frequency range : 24.1-27.6 GHz
• Skew :
• Jitter :
• Supply Voltage : 1.2V
• Power : 58.3mW
• Architecture : CP-PLL
• Technology : 45nm
Tools used:
• Cadence Virtuoso

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Introduction to Charge Pump and Phase Frequency Detector for PLL Design:

• The charge pump is a critical component in a Phase Locked Loop (PLL) system, responsible for
converting the digital output from the Phase Frequency Detector (PFD) into an analog control voltage.
This control voltage adjusts the frequency of the Voltage Controlled Oscillator (VCO), ensuring that the
PLL stays locked to the input reference frequency. A well-designed charge pump ensures minimal noise
and contributes to the overall stability of the loop.

• The Phase Frequency Detector (PFD) compares the phase and frequency of the input reference signal
and the feedback signal from the VCO. It generates two outputs, typically UP and DOWN signals, which
indicate whether the VCO frequency needs to be increased or decreased. The PFD’s accurate detection
of phase differences enables the PLL to lock onto the correct frequency quickly and efficiently. It’s an
essential component to reduce jitter and achieve precise frequency control, which is especially crucial
for high-speed 5G communication.

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Phase Frequency Detector:

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Charge Pump:

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Previous Work:

• Studied and analysed the technical specifications of LM565 PLL IC.

• Realised nmos , pmos and cmos inverter design in cadence virtuoso.

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Project Objectives:

1. Literature Survey

2. Design and implementation of charge pump in Cadence virtuoso and compare with the
performance metrics by designing a high precision charge pump with low power consumption.

3. Design and implementation of phase frequency detector consisting of high resolution, optimized for
low power consumption and helps to minimize the dead zone.

4. Design and implementation of phase lock loop(PLL) for 5g-6g communication.

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Literature Survey:
AUTHORS TITLE JOURNAL/CONFERENCE YEAR REVIEW
Suming You , Changchum A 65nm CMOS Phase-locked PhotonIcs & Electromagnetics 2019 A PLL for 5G mobile communications is
Zhang , Feng Yuan , Yi Loop for 5G Mobile Research Symposium | Fall presented in TSMC 65nm CMOS
Zhang. Communications (PIERS | FALL), Xiamen, technology.
China
S. Soliman, F. Yuan, and An overview of design techniques Department of Electrical and 2003 Explores various design methodologies
K. Raahemifar for CMOS phase detectors Computer Engineering to improve the efficiency, speed, and
Ryerson University accuracy of CMOS phase detectors,
Toronto, Ontario, Canada which are crucial in timing and
M5B 2K3 synchronization applications, including
clock recovery and frequency synthesis
in digital systems.

E.R. Suraparaju, P.V.R. Simple high-resolution CMOS Electrical Engineering, 2015 It discusses a design for a CMOS-
Arja and S. Ren phase Wright State University, based phase frequency detector (PFD)
frequency detector Dayton, OH 45435, USA that prioritizes high resolution and
simplicity, making it suitable for modern,
high-speed digital applications requiring
precise phase and frequency alignment.

Advancements and Integration of School of automotive 2024 In this paper, the author explores the
Jinchen Yao CMOS Phase Detectors in engineering, Jilin University, design, evolution, and applications of
Modern Communication Systems Changchun, Jilin Province, CMOS phase detectors.
and Imaging Technologies China

Chandra Shekhar Comparative Analysis of Charge IEEE International Conference 2022 Several Charge Pump (CP)
Srivastava, Pumps for PLL on Distributed Computing and architectures with integrated Phase
1
Sayyedhussain Siddiqui, Applications Electrical Circuits and Frequency Detector (PFD) were 3
Contd
AUTHORS TITLE JOURNAL/CONFERENCE YEAR REVIEW

UmakantaNanda, Study of Recent Charge Pump I.J. Modern Education and 2016 The paper includes analysis of different
Jyotirmayee Sarangi, Circuits in Phase Computer Science, 2016, 8, charge pumps in PLLs demonstrates
Prakash Kumar Rout Locked Loop 59-65 key performance metrics like lock time,
lock range, phase noise, and reference
spur. The basic CP-PLL shows a tuning
range of 119.5 MHz – 2.3 GHz, with fast
lock time (204 ns), low phase noise (-89
dBc/Hz at 1 MHz offset), and reference
spur (-101 dBc/Hz).
Labonnah Farzana Design Topologies of a CMOS MDPI 2021 In this article, various topologies of
Rahman, Mohammad Charge Pump Circuit for Low designing CP circuits for low power
Marufuzzaman , Lubna Power Applications applications are reviewed based on
Alam and Mazlin Bin different design schemes. CP’s essential
Mokhtar features. CMOS process and the charge
pumping capabilities, are compared in
detail.

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Technical Specifications of PFD:

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Technical Specifications of CP:

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Thank you!

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