CC2500

CC2500
Single Chip Low Cost Low Power RF Transceiver

Applications
• 2400-2483.5 MHz ISM/SRD band systems • Wireless audio
• Consumer Electronics • Wireless keyboard and mouse
• Wireless game controllers

Product Description
The CC2500 is a low cost true single chip 2.4 controlled via an SPI interface. In a typical
GHz transceiver designed for very low power system, the CC2500 will be used together with
wireless applications. The circuit is intended a microcontroller and a few additional passive
for the ISM (Industrial, Scientific and Medical) components.
and SRD (Short Range Device) frequency
band at 2400-2483.5 MHz. CC2500 is based on Chipcon’s SmartRF®04
technology in 0.18 µm CMOS.
The RF transceiver is integrated with a highly
configurable baseband modem. The modem
supports various modulation formats and has
a configurable data rate up to 500 kbps. The
communication range can be increased by
enabling a Forward Error Correction option,
which is integrated in the modem.
CC2500 provides extensive hardware support
for packet handling, data buffering, burst
transmissions, clear channel assessment, link
quality indication and wake-on-radio.
The main operating parameters and the 64-
byte transmit/receive FIFOs of CC2500 can be

Key Features
• Small size (QLP 4x4 mm package, 20 • Suitable for frequency hopping systems
pins) due to a fast settling frequency synthesizer
• True single chip 2.4 GHz RF transceiver • Optional Forward Error Correction with
• Frequency range: 2400-2483.5 MHz interleaving
• High sensitivity (–101 dBm at 10 kbps, 1% • Separate 64-byte RX and TX data FIFOs
packet error rate) • Efficient SPI interface: All registers can be
• Programmable data rate up to 500 kbps programmed with one “burst” transfer
• Low current consumption (13.3 mA in RX, • Digital RSSI output
250 kbps, input 30 dB above sensitivity • Suited for systems compliant with EN 300
limit) 328 and EN 300 440 class 2 (Europe),
• Programmable output power up to +1 dBm CFR47 Part 15 (US), and ARIB STD-T66
• Excellent receiver selectivity and blocking (Japan)
performance • Wake-on-radio functionality for automatic
• Very few external components: low-power RX polling
Completely on-chip frequency synthesizer, • Many powerful digital features allow a
no external filters or RF switch needed high-performance RF system to be made
• Programmable baseband modem using an inexpensive microcontroller
• Ideal for multi-channel operation • Integrated analog temperature sensor
• Configurable packet handling hardware • Lead-free “green“ package

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 1 of 77

CC2500

Features (continued from front page)

• Flexible support for packet oriented compatibility with existing radio
systems: On chip support for sync word communication protocols
detection, address check, flexible packet • Programmable Carrier Sense indicator
length and automatic CRC handling. • Programmable Preamble Quality Indicator
• Programmable channel filter bandwidth for detecting preambles and improved
• 2-FSK, GFSK and MSK supported protection against sync word detection in
• OOK supported random noise
• Automatic Frequency Compensation can • Support for automatic Clear Channel
be used to align the frequency synthesizer Assessment (CCA) before transmitting (for
to received centre frequency listen-before-talk systems)
• Optional automatic whitening and de- • Support for per-package Link Quality
whitening of data Indication
• Support for asynchronous transparent
receive/transmit mode for backwards

Abbreviations
Abbreviations used in this data sheet are described below.
2-FSK Binary Frequency Shift Keying MSK Minimum Shift Keying
ADC Analog to Digital Converter NA Not Applicable
AFC Automatic Frequency Offset Compensation PA Power Amplifier
AGC Automatic Gain Control PCB Printed Circuit Board
AMR Automatic Meter Reading PD Power Down
ASK Amplitude Shift Keying PER Packet Error Rate
BER Bit Error Rate PLL Phase Locked Loop
CCA Clear Channel Assessment POR Power-on Reset
CRC Cyclic Redundancy Check PQI Preamble Quality Indicator
CS Carrier Sense PQT Preamble Quality Threshold
DC Direct Current RCOSC RC Oscillator
EIRP Equivalent Isotropic Radiated Power RF Radio Frequency
ESR Equivalent Series Resistance RSSI Received Signal Strength Indicator
FEC Forward Error Correction RX Receive, Receive Mode
FIFO First-In-First-Out SAW Surface Aqustic Wave
FHSS Frequency Hopping Spread Spectrum SNR Signal to Noise Ratio
FSK Frequency Shift Keying SPI Serial Peripheral Interface
GFSK Gaussian shaped Frequency Shift Keying TBD To Be Defined
IF Intermediate Frequency TX Transmit, Transmit Mode
LBT Listen Before Transmit VCO Voltage Controlled Oscillator
LNA Low Noise Amplifier WOR Wake on Radio, Low power polling
LO Local Oscillator XOSC Crystal Oscillator
LQI Link Quality Indicator XTAL Crystal
MCU Microcontroller Unit

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 2 of 77

CC2500

Table Of Contents
APPLICATIONS ...........................................................................................................................................1
PRODUCT DESCRIPTION.........................................................................................................................1
KEY FEATURES ..........................................................................................................................................1
FEATURES (CONTINUED FROM FRONT PAGE)................................................................................2
ABBREVIATIONS........................................................................................................................................2
TABLE OF CONTENTS ..............................................................................................................................3
1 ABSOLUTE MAXIMUM RATINGS ..............................................................................................6
2 OPERATING CONDITIONS ..........................................................................................................6
3 GENERAL CHARACTERISTICS..................................................................................................6
4 ELECTRICAL SPECIFICATIONS ................................................................................................7
4.1 CURRENT CONSUMPTION .....................................................................................................................7
4.2 RF RECEIVE SECTION ...........................................................................................................................8
4.3 RF TRANSMIT SECTION ......................................................................................................................10
4.4 CRYSTAL OSCILLATOR .......................................................................................................................10
4.5 LOW POWER RC OSCILLATOR ............................................................................................................11
4.6 FREQUENCY SYNTHESIZER CHARACTERISTICS ...................................................................................11
4.7 ANALOG TEMPERATURE SENSOR .......................................................................................................12
4.8 DC CHARACTERISTICS .......................................................................................................................12
4.9 POWER-ON RESET ..............................................................................................................................12
5 PIN CONFIGURATION.................................................................................................................13
6 CIRCUIT DESCRIPTION .............................................................................................................15
7 APPLICATION CIRCUIT .............................................................................................................15
8 CONFIGURATION OVERVIEW .................................................................................................17
9 CONFIGURATION SOFTWARE.................................................................................................18
10 4-WIRE SERIAL CONFIGURATION AND DATA INTERFACE ...........................................19
10.1 CHIP STATUS BYTE ............................................................................................................................20
10.2 REGISTER ACCESS ..............................................................................................................................21
10.3 COMMAND STROBES ..........................................................................................................................22
10.4 FIFO ACCESS .....................................................................................................................................22
10.5 PATABLE ACCESS ............................................................................................................................22
11 MICROCONTROLLER INTERFACE AND PIN CONFIGURATION ...................................23
11.1 CONFIGURATION INTERFACE ..............................................................................................................23
11.2 GENERAL CONTROL AND STATUS PINS ..............................................................................................23
11.3 OPTIONAL RADIO CONTROL FEATURE ...............................................................................................23
12 DATA RATE PROGRAMMING...................................................................................................24
13 RECEIVER CHANNEL FILTER BANDWIDTH .......................................................................24
14 DEMODULATOR, SYMBOL SYNCHRONIZER AND DATA DECISION............................25
14.1 FREQUENCY OFFSET COMPENSATION.................................................................................................25
14.2 BIT SYNCHRONIZATION ......................................................................................................................25
14.3 BYTE SYNCHRONIZATION ...................................................................................................................25
15 PACKET HANDLING HARDWARE SUPPORT .......................................................................25
15.1 DATA WHITENING ..............................................................................................................................26
15.2 PACKET FORMAT ................................................................................................................................26
15.3 PACKET FILTERING IN RECEIVE MODE ...............................................................................................27
15.4 CRC CHECK .......................................................................................................................................28
15.5 PACKET HANDLING IN TRANSMIT MODE ............................................................................................28
15.6 PACKET HANDLING IN RECEIVE MODE ..............................................................................................28
16 MODULATION FORMATS ..........................................................................................................29
16.1 FREQUENCY SHIFT KEYING ................................................................................................................29
16.2 MINIMUM SHIFT KEYING....................................................................................................................29
16.3 AMPLITUDE MODULATION .................................................................................................................29

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 3 of 77

CC2500
17 RECEIVED SIGNAL QUALIFIERS AND LINK QUALITY INFORMATION .....................30
17.1 SYNC WORD QUALIFIER .....................................................................................................................30
17.2 PREAMBLE QUALITY THRESHOLD (PQT) ...........................................................................................30
17.3 RSSI...................................................................................................................................................30
17.4 CARRIER SENSE (CS)..........................................................................................................................31
17.5 CLEAR CHANNEL ASSESSMENT (CCA) ..............................................................................................32
17.6 LINK QUALITY INDICATOR (LQI) .......................................................................................................32
18 FORWARD ERROR CORRECTION WITH INTERLEAVING ..............................................33
18.1 FORWARD ERROR CORRECTION (FEC)...............................................................................................33
18.2 INTERLEAVING ...................................................................................................................................33
19 RADIO CONTROL.........................................................................................................................34
19.1 POWER-ON START-UP SEQUENCE ......................................................................................................35
19.2 CRYSTAL CONTROL ............................................................................................................................35
19.3 VOLTAGE REGULATOR CONTROL.......................................................................................................35
19.4 ACTIVE MODES ..................................................................................................................................35
19.5 WAKE ON RADIO (WOR)...................................................................................................................36
19.6 TIMING ...............................................................................................................................................37
19.7 RX TERMINATION TIMER ...................................................................................................................37
20 DATA FIFO .....................................................................................................................................38
21 FREQUENCY PROGRAMMING.................................................................................................39
22 VCO ..................................................................................................................................................40
22.1 VCO AND PLL SELF-CALIBRATION ...................................................................................................40
23 VOLTAGE REGULATORS ..........................................................................................................40
24 OUTPUT POWER PROGRAMMING .........................................................................................40
25 SELECTIVITY GRAPHS ..............................................................................................................42
26 CRYSTAL OSCILLATOR.............................................................................................................44
26.1 REFERENCE SIGNAL ...........................................................................................................................44
27 EXTERNAL RF MATCH ..............................................................................................................45
28 GENERAL PURPOSE / TEST OUTPUT CONTROL PINS ......................................................45
29 ASYNCHRONOUS AND SYNCHRONOUS SERIAL OPERATION .......................................47
29.1 ASYNCHRONOUS OPERATION..............................................................................................................47
29.2 SYNCHRONOUS SERIAL OPERATION ....................................................................................................47
30 SYSTEM CONSIDERATIONS AND GUIDELINES ..................................................................47
30.1 SRD REGULATIONS ............................................................................................................................47
30.2 FREQUENCY HOPPING AND MULTI-CHANNEL SYSTEMS .....................................................................47
30.3 DATA BURST TRANSMISSIONS............................................................................................................48
30.4 CONTINUOUS TRANSMISSIONS ...........................................................................................................48
30.5 CRYSTAL DRIFT COMPENSATION .......................................................................................................48
30.6 SPECTRUM EFFICIENT MODULATION ..................................................................................................48
30.7 LOW COST SYSTEMS ..........................................................................................................................49
30.8 BATTERY OPERATED SYSTEMS ..........................................................................................................49
30.9 INCREASING OUTPUT POWER .............................................................................................................49
31 CONFIGURATION REGISTERS.................................................................................................49
31.1 CONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE ..........54
31.2 CONFIGURATION REGISTER DETAILS – REGISTERS THAT LOSE PROGRAMMING IN SLEEP STATE ........69
31.3 STATUS REGISTER DETAILS .................................................................................................................70
32 PACKAGE DESCRIPTION (QLP 20)..........................................................................................73
32.1 RECOMMENDED PCB LAYOUT FOR PACKAGE (QLP 20) .....................................................................74
32.2 PACKAGE THERMAL PROPERTIES ........................................................................................................74
32.3 SOLDERING INFORMATION..................................................................................................................74
32.4 TRAY SPECIFICATION ..........................................................................................................................74
32.5 CARRIER TAPE AND REEL SPECIFICATION ...........................................................................................75
33 ORDERING INFORMATION.......................................................................................................75
34 GENERAL INFORMATION.........................................................................................................75

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 4 of 77

CC2500
34.1 DOCUMENT HISTORY .........................................................................................................................75
34.2 PRODUCT STATUS DEFINITIONS .........................................................................................................75
34.3 DISCLAIMER .......................................................................................................................................76
34.4 TRADEMARKS .....................................................................................................................................76
34.5 LIFE SUPPORT POLICY ........................................................................................................................76
35 ADDRESS INFORMATION ..........................................................................................................77

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 5 of 77

CC2500

1 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress
exceeding one or more of the limiting values may cause permanent damage to the device.
Caution! ESD sensitive device.
Precaution should be used when handling
the device in order to prevent permanent
damage.

Parameter Min Max Units Condition

Supply voltage –0.3 3.6 V All supply pins must have the same voltage
Voltage on any digital pin –0.3 VDD+0.3 V
max 3.6
Voltage on the pins RF_P, RF_N –0.3 2.0 V
and DCOUPL
Voltage ramp-up rate 120 kV/µs
Input RF level +10 dBm
Storage temperature range –50 150 °C
Solder reflow temperature 260 °C T = 10 s

Table 1: Absolute Maximum Ratings

2 Operating Conditions
The operating conditions for CC2500 are listed Table 2 in below.
Parameter Min Max Unit Condition
Operating temperature –40 85 °C
Operating supply voltage 1.8 3.6 V All supply pins must have the same voltage

Table 2: Operating Conditions

3 General Characteristics
Parameter Min Typ Max Unit Condition/Note
Frequency range 2400 2483.5 MHz
Data rate 1.2 500 kbps Modulation formats supported:
(Shaped) MSK (also known as differential offset
QPSK) up to 500 kbps
2-FSK up to 500 kbps

GFSK and OOK (up to 250 kbps)

Optional Manchester encoding (halves the data rate).

Table 3: General Characteristics

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 6 of 77

CC2500

4 Electrical Specifications

4.1 Current Consumption

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurements were performed using the CC2500EM reference design.

Parameter Min Typ Max Unit Condition

Current consumption in 400 nA Voltage regulator to digital part off, register values retained
power down modes (SLEEP state)
900 nA Voltage regulator to digital part off, register values retained, low-
power RC oscillator running (SLEEP state with WOR enabled)
92 µA Voltage regulator to digital part off, register values retained,
XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set)

157 µA Voltage regulator to digital part on, all other modules in power
down (XOFF state)
Current consumption 1.4 µA Automatic RX polling once each second, using low-power RC
oscillator, with 460 kHz filter bandwidth and 250 kbps data rate,
th
PLL calibration every 4 wakeup. Average current with signal in
channel below carrier sense level.

17 µA Same as above, but with signal in channel above carrier sense

level, 1.9 ms RX timeout, and no preamble/sync word found.
th
0.9 µA Automatic RX polling every 15 second, using low-power RC
oscillator, with 460 kHz filter bandwidth and 250 kbps data rate,
th
PLL calibration every 4 wakeup. Average current with signal in
channel below carrier sense level.
37 µA Same as above, but with signal in channel above carrier sense
level, 14 ms RX timeout, and no preamble/sync word found.
1.5 mA Only voltage regulator to digital part and crystal oscillator running
(IDLE state)
7.4 mA Only the frequency synthesizer running (after going from IDLE
until reaching RX or TX states, and frequency calibration states)
Current consumption, 15.3 mA Receive mode, 2.4 kbps, input at sensitivity limit,
RX states MDMCFG2.DEM_DCFILT_OFF = 1

12.8 mA Receive mode, 2.4 kbps, input 30 dB above sensitivity limit,

MDMCFG2.DEM_DCFILT_OFF = 1

15.4 mA Receive mode, 10 kbps, input at sensitivity limit,

MDMCFG2.DEM_DCFILT_OFF = 1

12.9 mA Receive mode, 10 kbps, input 30 dB above sensitivity limit,

MDMCFG2.DEM_DCFILT_OFF = 1

18.8 mA Receive mode, 250 kbps, input at sensitivity limit,

MDMCFG2.DEM_DCFILT_OFF = 0

15.7 mA Receive mode, 250 kbps, input 30 dB above sensitivity limit,

MDMCFG2.DEM_DCFILT_OFF = 0

16.6 mA Receive mode, 250 kbps reduced current, input at sensitivity

limit, MDMCFG2.DEM_DCFILT_OFF = 1

13.3 mA Receive mode, 250 kbps reduced current, input 30 dB above

sensitivity limit, MDMCFG2.DEM_DCFILT_OFF = 1

19.6 mA Receive mode, 500 kbps, input at sensitivity limit,

MDMCFG2.DEM_DCFILT_OFF = 0

17.0 mA Receive mode, 500 kbps, input 30 dB above sensitivity limit,

MDMCFG2.DEM_DCFILT_OFF = 0

Current consumption, 11.1 mA Transmit mode, –12 dBm output power

TX states
15.1 mA Transmit mode, -6 dBm output power

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 7 of 77

CC2500

Parameter Min Typ Max Unit Condition

21.2 mA Transmit mode, 0 dBm output power

21.5 mA Transmit mode, 1.5 dBm output power

Table 4: Current Consumption

4.2 RF Receive Section

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurements were performed using the CC2500EM reference design.

Parameter Min Typ Max Unit Condition/Note

Digital channel filter 58 812 kHz User programmable. The bandwidth limits are proportional
bandwidth to crystal frequency (given values assume a 26.0 MHz
crystal).
2.4 kbps data rate, reduced current, MDMCFG2.DEM_DCFILT_OFF = 1
(2-FSK, 1% packet error rate, 20 bytes packet length, 203 kHz digital channel filter bandwidth)
Receiver sensitivity –104 dBm The sensitivity can be improved to typically –106 dBm by
setting MDMCFG2.DEM_DCFILT_OFF = 0 . The typical
current consumption is in this case 17.0 mA at sensitivity
llimit.
Saturation –13 dBm
Adjacent channel 23 dB Desired channel 3 dB above the sensitivity limit. 250 kHz
rejection channel spacing
Alternate channel 31 dB Desired channel 3 dB above the sensitivity limit. 250 kHz
rejection channel spacing
See Figure 17 for plot of selectivity versus frequency offset
10 kbps data rate, reduced current, MDMCFG2.DEM_DCFILT_OFF = 1
(2-FSK, 1% packet error rate, 20 bytes packet length, 232 kHz digital channel filter bandwidth)
Receiver sensitivity –99 dBm The sensitivity can be improved to typically –101 dBm by
setting MDMCFG2.DEM_DCFILT_OFF = 0 . The typical
current consumption is in this case 17.3 mA at sensitivity
llimit.
Saturation –9 dBm
Adjacent channel 18 dB Desired channel 3 dB above the sensitivity limit. 250 kHz
rejection channel spacing
Alternate channel 25 dB Desired channel 3 dB above the sensitivity limit. 250 kHz
rejection channel spacing
See Figure 18 for plot of selectivity versus frequency offset
250 kbps data rate, MDMCFG2.DEM_DCFILT_OFF = 0
(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver sensitivity –89 dBm
Saturation –13 dBm
Adjacent channel 21 dB Desired channel 3 dB above the sensitivity limit. 750 kHz
rejection channel spacing
Alternate channel 30 dB Desired channel 3 dB above the sensitivity limit. 750 kHz
rejection channel spacing
See Figure 19 for plot of selectivity versus frequency offset

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 8 of 77

CC2500
Parameter Min Typ Max Unit Condition/Note
250 kbps data rate, reduced current, MDMCFG2.DEM_DCFILT_OFF = 1
(MSK, 1% packet error rate, 20 bytes packet length, 540 kHz digital channel filter bandwidth)
Receiver sensitivity –87 dBm
Saturation –13 dBm
Adjacent channel 21 dB Desired channel 3 dB above the sensitivity limit. 750 kHz
rejection channel spacing
Alternate channel 30 dB Desired channel 3 dB above the sensitivity limit. 750 kHz
rejection channel spacing
See Figure 20 for plot of selectivity versus frequency offset
500 kbps data rate, MDMCFG2.DEM_DCFILT_OFF = 0
(MSK, 1% packet error rate, 20 bytes packet length, 812 kHz digital channel filter bandwidth)
Receiver sensitivity –82 dBm
Saturation –18 dBm
Adjacent channel 14 dB Desired channel 3 dB above the sensitivity limit. 1 MHz
rejection channel spacing
Alternate channel 25 dB Desired channel 3 dB above the sensitivity limit. 1 MHz
rejection channel spacing
See Figure 21 for plot of selectivity versus frequency offset
General
Selectivity at 10 MHz 47 dB Desired channel at –80 dBm. Compliant with ETSI EN 300
offset 440 class 2 receiver requirements.
Selectivity at 20 MHz 52 dB Desired channel at –80 dBm. Compliant with ETSI EN 300
offset 440 class 2 receiver requirements.
Selectivity at 50 MHz 54 dB Desired channel at –80 dBm. Compliant with ETSI EN 300
offset 440 class 2 receiver requirements.
Spurious emissions
25 MHz – 1 GHz –57 dBm
Above 1 GHz –47 dBm

Table 5: RF Receive Parameters

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 9 of 77

CC2500
4.3 RF Transmit Section
Tc = 25°C, VDD = 3.0 V, 0 dBm if nothing else stated. All measurements were performed using the CC2500EM reference
design.

Parameter Min Typ Max Unit Condition/Note

Differential load 80 + j74 Ω Differential impedance as seen from the RF-port (RF_P and
impedance RF_N) towards the antenna. Follow the CC2500EM
reference design available from Chipcon’s website.
Output power, +1 dBm Output power is programmable and is available across the
highest setting entire frequency band
Delivered to a 50 Ω single-ended load via Chipcon
reference design RF matching network.
Output power, –30 dBm Output power is programmable and is available across the
lowest setting entire frequency band
Delivered to a 50 Ω single-ended load via Chipcon
reference design RF matching network.
Spurious emissions
25 MHz – 1 GHz –36 dBm
47-74, 87.5-118, 174- –54 dBm
230, 470-862 MHz
1800-1900 MHz –47 dBm Restricted band in Europe
At 2·RF and 3·RF –41 dBm Restricted bands in USA
Otherwise above 1 –30 dBm
GHz

Table 6: RF Transmit Parameters

4.4 Crystal Oscillator

Tc = 25°C, VDD = 3.0 V if nothing else stated.

Parameter Min Typ Max Unit Condition/Note

Crystal frequency 26 26 27 MHz
Tolerance ±40 ppm This is the total tolerance including a) initial tolerance, b) crystal
loading, c) aging and d) temperature dependence.
The acceptable crystal tolerance depends on RF frequency and
channel spacing / bandwidth.
ESR 100 Ω
Start-up time 300 µs Measured on Chipcon’s CC2500EM reference design.

Table 7: Crystal Oscillator Parameters

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 10 of 77

CC2500
4.5 Low Power RC Oscillator
Typical performance is for Tc = 25°C @ VDD = 3.0 V if nothing else is stated. The values in the table are simulated results
and will be updated in later versions of the data sheet.

Parameter Min Typ Max Unit Condition/Note

Calibrated frequency 34.6 34.7 36 kHz Calibrated RC Oscillator frequency is XTAL
frequency divided by 750
Frequency accuracy after +0.3 %
calibration -10
Temperature coefficient +0.4 % / °C Frequency drift when temperature changes
after calibration
Supply voltage coefficient +3 %/V Frequency drift when supply voltage changes
after calibration
Initial calibration time 2 ms When the RC Oscillator is enabled, calibration
is continuously done in the background as long
as the crystal oscillator is running.
Wake-up period 58e-6 59650 Seconds Programmable, dependent on XTAL frequency

Table 8: RC Oscillator Parameters

4.6 Frequency Synthesizer Characteristics

Tc = 25°C, VDD = 3.0 V if nothing else stated. All measurements were performed using the CC2500EM reference design.

Parameter Min Typ Max Unit Condition/Note

Programmed 397 FXOSC/ 412 Hz 26-27 MHz crystal.

16
frequency resolution 2
Synthesizer frequency ±40 ppm Given by crystal used. Required accuracy (including
tolerance temperature and aging) depends on frequency band and
channel bandwidth / spacing.
RF carrier phase noise –78 dBc/Hz @ 50 kHz offset from carrier
RF carrier phase noise –78 dBc/Hz @ 100 kHz offset from carrier
RF carrier phase noise –81 dBc/Hz @ 200 kHz offset from carrier
RF carrier phase noise –90 dBc/Hz @ 500 kHz offset from carrier
RF carrier phase noise –100 dBc/Hz @ 1 MHz offset from carrier
RF carrier phase noise –108 dBc/Hz @ 2 MHz offset from carrier
RF carrier phase noise –116 dBc/Hz @ 5 MHz offset from carrier
RF carrier phase noise –127 dBc/Hz @ 10 MHz offset from carrier
PLL turn-on / hop time 90 µs Time from leaving the IDLE state until arriving in the RX,
FSTXON or TX state, when not performing calibration.
Crystal oscillator running.
PLL RX/TX and 10 µs Settling time for the 1xIF frequency step from RX to TX,
TX/RX settling time and vice versa.
PLL calibration time 18739 XOSC Calibration can be initiated manually, or automatically
cycles before entering or after leaving RX/TX.
0.69 0.72 0.72 ms Min/typ/max time is for 27/26/26 MHz crystal frequency.

Table 9: Frequency Synthesizer Parameters

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 11 of 77

CC2500

4.7 Analog Temperature Sensor

The characteristics of the analog temperature sensor are listed in Table 10 below. Note that it is
necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE
state.
Parameter Min Typ Max Unit Condition/Note

Output voltage at –40°C 0.660 V

Output voltage at 0°C 0.755 V

Output voltage at +40°C 0.859 V

Output voltage at +80°C 0.958 V

Output voltage at +120°C 1.056 V

Temperature coefficient 2.54 mV/°C Fitted from –20°C to +80°C

Error in calculated 0 °C From –20°C to +80°C when using 2.54 mV / °C,
temperature, calibrated after 1-point calibration at room temperature
Current consumption 0.3 mA
increase when enabled

Table 10: Analog Temperature Sensor Parameters

4.8 DC Characteristics
The DC Characteristics of CC2500 are listed in Table 11 below.
Tc = 25°C if nothing else stated.

Digital Inputs/Outputs Min Max Unit Condition

Logic "0" input voltage 0 0.7 V
Logic "1" input voltage VDD-0.7 VDD V
Logic "0" output voltage 0 0.5 V For up to 4 mA output current
Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current
Logic "0" input current NA –1 µA Input equals 0V

Logic "1" input current NA 1 µA Input equals VDD

Table 11: DC Characteristics

4.9 Power-On Reset

When the power supply complies with the requirements in Table 12 below, proper Power-On-
Reset functionality is guaranteed. Otherwise, the chip should be assumed to have unknown state
until transmitting an SRES strobe over the SPI interface. See Section 19.1 on page 35 for further
details.
Parameter Min Typ Max Unit Condition/Note

Power ramp-up time 5 ms From 0 V until reaching 1.8 V

Power off time 1 ms Minimum time between power-on and power-off.

Table 12: Power-On Reset Requirements

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 12 of 77

CC2500

5 Pin Configuration

DGUARD
RBIAS
GND

GND
SI
20 19 18 17 16

SCLK 1 15 AVDD
SO (GDO1) 2 14 AVDD
GDO2 3 13 RF_N
DVDD 4 12 RF_P
DCOUPL 5 11 AVDD

GND
6 7 8 9 10
Exposed die
GDO0 (ATEST)
CSn
XOSC_Q1
AVDD
XOSC_Q2
attach pad

Figure 1: Pinout top view

Note: The exposed die attach pad must be connected to a solid ground plane as this is the main
ground connection for the chip.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 13 of 77

CC2500

Pin # Pin name Pin type Description

1 SCLK Digital Input Serial configuration interface, clock input

2 SO Digital Output Serial configuration interface, data output.

(GDO1) Optional general output pin when CSn is high

3 GDO2 Digital Output Digital output pin for general use:

• Test signals
• FIFO status signals
• Clear Channel Indicator
• Clock output, down-divided from XOSC
• Serial output RX data

4 DVDD Power (Digital) 1.8 - 3.6 V digital power supply for digital I/O’s and for the digital core
voltage regulator
5 DCOUPL Power (Digital) 1.6 - 2.0 V digital power supply output for decoupling.
NOTE: This pin is intended for use with the CC2500 only. It can not be
used to provide supply voltage to other devices.
6 GDO0 Digital I/O Digital output pin for general use:

(ATEST) • Test signals

• FIFO status signals
• Clear Channel Indicator
• Clock output, down-divided from XOSC
• Serial output RX data
• Serial input TX data
Also used as analog test I/O for prototype/production testing

7 CSn Digital Input Serial configuration interface, chip select

8 XOSC_Q1 Analog I/O Crystal oscillator pin 1, or external clock input

9 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

10 XOSC_Q2 Analog I/O Crystal oscillator pin 2

11 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

12 RF_P RF I/O Positive RF input signal to LNA in receive mode

Positive RF output signal from PA in transmit mode
13 RF_N RF I/O Negative RF input signal to LNA in receive mode
Negative RF output signal from PA in transmit mode
14 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

15 AVDD Power (Analog) 1.8 - 3.6 V analog power supply connection

16 GND Ground (Analog) Analog ground connection

17 RBIAS Analog I/O External bias resistor for reference current

18 DGUARD Power (Digital) Power supply connection for digital noise isolation

19 GND Ground (Digital) Ground connection for digital noise isolation

20 SI Digital Input Serial configuration interface, data input

Table 13: Pinout overview

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 14 of 77

CC2500

6 Circuit Description

RADIO CONTROL

DEMODULATOR
ADC

RXFIFO
LNA

DIGITAL INTERFACE TO MCU

FEC / INTERLEAVER
ADC SCLK

PACKET HANDLER
SO (GDO1)
SI
RF_P FREQ
0 CSn
RF_N SYNTH
90
GDO0 (ATEST)
GDO2

PA MODULATOR

TXFIFO
RC OSC BIAS XOSC

RBIAS XOSC_Q1 XOSC_Q2

Figure 2: CC2500 simplified block diagram

A simplified block diagram of CC2500 is shown phase shifter for generating the I and Q LO
in Figure 2. signals to the down-conversion mixers in
receive mode.
CC2500 features a low-IF receiver. The
received RF signal is amplified by the low- A crystal is to be connected to XOSC_Q1 and
noise amplifier (LNA) and down-converted in XOSC_Q2. The crystal oscillator generates the
quadrature (I and Q) to the intermediate reference frequency for the synthesizer, as
frequency (IF). At IF, the I/Q signals are well as clocks for the ADC and the digital part.
digitised by the ADCs. Automatic gain control A 4-wire SPI serial interface is used for
(AGC), fine channel filtering, demodulation configuration and data buffer access.
bit/packet synchronization is performed
digitally. The digital baseband includes support for
channel configuration, packet handling and
The transmitter part of CC2500 is based on data buffering.
direct synthesis of the RF frequency.
The frequency synthesizer includes a
completely on-chip LC VCO and a 90 degrees

7 Application Circuit
Only a few external components are required Bias resistor
for using the CC2500. The recommended
The bias resistor R171 is used to set an
application circuit is shown in Figure 3. The
accurate bias current.
external components are described in Table
14, and typical values are given in Table 15. Balun and RF matching
Note that the PCB antenna alternative
C122, C132, L121 and L131 form a balun that
indicated in Figure 3 is preliminary and subject
to changes. Performance for the PCB antenna converts the differential RF signal on CC2500
to a single-ended RF signal (C121 and C131
alternative will be included in future revisions
of this data sheet. are also needed for DC blocking). Together

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 15 of 77

CC2500
with an appropriate LC network, the balun Power supply decoupling
components also transform the impedance to
The power supply must be properly decoupled
match a 50 Ω antenna (or cable). Component
close to the supply pins. Note that decoupling
values for the RF balun and LC network are
capacitors are not shown in the application
easily found using the SmartRF® Studio circuit. The placement and the size of the
software. Suggested values are listed in Table decoupling capacitors are very important to
15. achieve the optimum performance. Chipcon
Crystal provides a reference design that should be
followed closely.
The crystal oscillator uses an external crystal
with two loading capacitors (C81 and C101).
See Section 26 on page 44 for details.

Component Description

C51 Decoupling capacitor for on-chip voltage regulator to digital part

C81/C101 Crystal loading capacitors, see Section 26 on page 44 for details

C121/C131 RF balun DC blocking capacitors

C122/C132 RF balun/matching capacitors

C123/C124 RF LC filter/matching capacitors

L121/L131 RF balun/matching inductors (inexpensive multi-layer type)
L122 RF LC filter inductor (inexpensive multi-layer type)

R171 Resistor for internal bias current reference

XTAL 26-27 MHz crystal, see Section 26 on page 44 for details

Table 14: Overview of external components (excluding supply decoupling capacitors)

1.8V-3.6V power supply

R171

SI
GND 19

DGUARD 18

GND 16
SI 20

RBIAS 17

Antenna
SCLK (50 Ohm)
1 SCLK AVDD 15

SO L131
Digital Inteface

2 SO (GDO1) AVDD 14
(GDO1)

CC2500
GDO2 C131 C132
3 GDO2 RF_N 13
(optional)
C121
4 DVDD DIE ATTACH PAD: RF_P 12 L122
L121
C123 C124
10 XOSC_Q2

5 DCOUPL AVDD 11
8 XOSC_Q1

C122
6 GDO0

9 AVDD
7 CSn

C51
GDO0 Alternative:
(optional) Folded dipole PCB
CSn
antenna (no external
XTAL components needed)

C81 C101

Figure 3: Typical application and evaluation circuit (excluding supply decoupling capacitors)

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 16 of 77

CC2500

Component Value
C51 100 nF ±10%, 0402 X5R
C81 27 pF ±5%, 0402 NP0
C101 27 pF ±5%, 0402 NP0
C121 100 pF ±5%, 0402 NP0
C122 1.0 pF ±0.25 pF, 0402 NP0
C123 1.8 pF ±0.25 pF, 0402 NP0
C124 1.5 pF ±0.25 pF, 0402 NP0
C131 100 pF ±5%, 0402 NP0
C132 1.0 pF ±0.25 pF, 0402 NP0
L121 1.2 nH ±0.3 nH, 0402 monolithic, Murata LQG-15 series
L122 1.2 nH ±0.3 nH, 0402 monolithic, Murata LQG-15 series
L131 1.2 nH ±0.3 nH, 0402 monolithic, Murata LQG-15 series
R171 56 kΩ ±1%, 0402
XTAL 26.0 MHz surface mount crystal

Table 15: Bill Of Materials for the application circuit

In the CC2500EM reference design LQG-15 multi-layer inductors from other manufacturers
series inductors from Murata have been used. (e.g. Würth) and the measurement results
Measurements have been performed with were the same as when using the Murata part.

8 Configuration Overview

CC2500 can be configured to achieve optimum • Packet radio hardware support

performance for many different applications. • Forward Error Correction with interleaving
Configuration is done using the SPI interface. • Data Whitening
The following key parameters can be • Wake-On-Radio (WOR)
programmed:
• Power-down / power up mode Details of each configuration register can be
• Crystal oscillator power-up / power-down found in Section 31, starting on page 49.
• Receive / transmit mode
Figure 4 shows a simplified state diagram that
• RF channel selection
explains the main CC2500 states, together with
• Data rate
typical usage and current consumption. For
• Modulation format
detailed information on controlling the CC2500
• RX channel filter bandwidth state machine, and a complete state diagram,
• RF output power see Section 19, starting on page 34.
• Data buffering with separate 64-byte
receive and transmit FIFOs

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 17 of 77

CC2500
Lowest power mode. Most
register values are retained.
Typ. current consumption
Sleep
400nA, or 900nA when
SIDLE SPWD or wake-on-radio (WOR) wake-on-radio (WOR) is
enabled.
Default state when the radio is not
receiving or transmitting. Typ. CSn=0
current consumption: 1.5mA.
Idle
SXOFF
Used for calibrating frequency SCAL
synthesizer upfront (entering CSn=0
All register values are
receive or transmit mode can Manual freq. Crystal
retained. Typ. current
then be done quicker). synth. calibration SRX or STX or SFSTXON or wake-on-radio (WOR) oscillator off
consumption; 0.16mA.
Transitional state. Typ. current
consumption: 7.4mA.

Frequency
Frequency synthesizer is turned on, can optionally be
synthesizer startup,
calibrated, and then settles to the correct frequency.
SFSTXON optional calibration,
Frequency synthesizer is on, Transitional state. Typ. current consumption: 7.4mA.
settling
ready to start transmitting.
Transmission starts very Frequency
quickly after receiving the synthesizer on
STX command strobe.Typ.
STX
current consumption: 7.4mA.
SRX or wake-on-radio (WOR)

STX TXOFF_MODE=01

SFSTXON or RXOFF_MODE=01

Typ. current consumption: Typ. current consumption:

11.1mA at -12dBm output, STX or RXOFF_MODE=10 from 13.3mA (strong
Transmit mode Receive mode
15.1mA at -6dBm output, input signal) to 16.3mA
21.2mA at 0dBm output. SRX or TXOFF_MODE=11 (weak input sgnal).

TXOFF_MODE=00 RXOFF_MODE=00
Optional transitional state. Typ.
In FIFO-based modes, current consumption: 7.4mA.
In FIFO-based modes,
transmission is turned off
reception is turned off and
and this state entered if the TX FIFO Optional freq. RX FIFO
this state entered if the RX
TX FIFO becomes empty in underflow synth. calibration overflow
FIFO overflows. Typ. current
the middle of a packet. Typ.
consumption: 1.5mA.
current consumption: 1.5mA.

SFTX
SFRX

Idle

Figure 4: Simplified state diagram, with typical usage and current consumption at 250 kbps
data rate and MDMCFG2.DEM_DCFILT_OFF = 1 (reduced current)

9 Configuration Software

CC2500 can be configured using the SmartRF® optimum register settings, and for evaluating
Studio software, available for download from performance and functionality. A screenshot of
http://www.chipcon.com. The SmartRF® Studio the SmartRF® Studio user interface for CC2500
software is highly recommended for obtaining is shown in Figure 5.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 18 of 77

CC2500

Figure 5: SmartRF® Studio user interface

10 4-wire Serial Configuration and Data Interface

CC2500 is configured via a simple 4-wire SPI- will be cancelled. The timing for the address
compatible interface (SI, SO, SCLK and CSn) and data transfer on the SPI interface is
where CC2500 is the slave. This interface is shown in Figure 6 with reference to Table 16.
also used to read and write buffered data. All When CSn goes low, the MCU must wait until
address and data transfer on the SPI interface
CC2500 SO pin goes low before starting to
is done most significant bit first.
transfer the header byte. This indicates that
All transactions on the SPI interface start with the voltage regulator has stabilized and the
a header byte containing a read/write bit, a crystal is running. Unless the chip was in the
burst access bit and a 6-bit address. SLEEP or XOFF states, the SO pin will always
During address and data transfer, the CSn pin go low immediately after taking CSn low.
(Chip Select, active low) must be kept low. If Figure 7 gives a brief overview of different
CSn goes high during the access, the transfer register access types possible.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 19 of 77

CC2500
tsp tch tcl tsd thd tns

SCLK:

CSn:
Write to register:

SI
X 0 A6 A5 A4 A3 A2 A1 A0 X D 7
W
D 6
W
D 5
W
D 4
W
D 3
W
D 2
W
D 1
W
D 0
W
X

Hi-Z S7 S6 S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 S7 Hi-Z
SO
Read from register:

SI
X 1 A6 A5 A4 A3 A2 A1 A0 X

S7 S6 S5 S4 S3 S2 S1 S0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
SO Hi-Z R R R R R R R R
Hi-Z

Figure 6: Configuration registers write and read operations (A6 is the “burst” bit)

Parameter Description Min Max Units

FSCLK SCLK frequency 0 10 MHz

tsp,pd CSn low to positive edge on SCLK, in power-down mode TBD - µs

tsp CSn low to positive edge on SCLK, in active mode TBD - ns

tch Clock high 50 - ns

tcl Clock low 50 - ns
trise Clock rise time - TBD ns
tfall Clock rise time - TBD ns
tsd Setup data to positive edge on SCLK TBD - ns

thd Hold data after positive edge on SCLK TBD - ns

tns Negative edge on SCLK to CSn high. TBD - ns

Table 16: SPI interface timing requirements

CSn:

Command strobe(s): ADDRstrobe ADDRstrobe ADDRstrobe ...

Read or write register(s): ADDRreg DATA ADDRreg DATA ADDRreg DATA ...

Read or write consecutive registers (burst): ADDRreg n DATAn DATAn+1 DATAn+2 ...
Read or write n+1 bytes from/to RF FIFO: ADDRFIFO DATAbyte 0 DATAbyte 1 DATAbyte 2 ... DATAbyte n-1 DATAbyte n

Combinations: ADDRreg DATA ADDRstrobe ADDRreg DATA ADDRstrobe ADDRFIFO DATAbyte 0 DATAbyte 1 ...

Figure 7: Register access types

10.1 Chip Status Byte

When the header byte, data byte or command the CHIP_RDYn signal; this signal must go low
strobe is sent on the SPI interface, the chip before the first positive edge of SCLK. The
status byte is sent by the CC2500 on the SO CHIP_RDYn signal indicates that the crystal is
pin. The status byte contains key status running and the regulated digital supply
signals, useful for the MCU. The first bit, s7, is voltage is stable.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 20 of 77

CC2500
Bits 6, 5 and 4 comprise the STATE value. The last four bits (3:0) in the status byte con-
This value reflects the state of the chip. The tains FIFO_BYTES_AVAILABLE. For read
XOSC and power to the digital core is on in operations, the FIFO_BYTES_AVAILABLE
the IDLE state, but all other modules are in field contains the number of bytes available for
power down. The frequency and channel reading from the RX FIFO. For write
configuration should only be updated when the operations, the FIFO_BYTES_AVAILABLE
chip is in this state. The RX state will be active field contains the number of bytes free for
when the chip is in receive mode. Likewise, TX writing into the TX FIFO. When
is active when the chip is transmitting. FIFO_BYTES_AVAILABLE=15, 15 or more
bytes are available/free.
Table 17 gives a status byte summary.

Bits Name Description

7 CHIP_RDYn Stays high until power and crystal have stabilized. Should always be low when using
the SPI interface.
6:4 STATE[2:0] Indicates the current main state machine mode
Value State Description
000 IDLE Idle state
(Also reported for some transitional states instead
of SETTLING or CALIBRATE)

001 RX Receive mode

010 TX Transmit mode
011 FSTXON Frequency synthesizer is on, ready to start
transmitting
100 CALIBRATE Frequency synthesizer calibration is running
101 SETTLING PLL is settling
110 RXFIFO_OVERFLOW RX FIFO has overflowed. Read out any
useful data, then flush the FIFO with SFRX

111 TXFIFO_UNDERFLOW TX FIFO has underflowed. Acknowledge with

SFTX
3:0 FIFO_BYTES_AVAILABLE[3:0] The number of bytes available in the RX FIFO or free bytes in the TX FIFO
(depends on the read/write-bit). If FIFO_BYTES_AVAILABLE=15, there are 15 or
more bytes in RX FIFO or 49 or less bytes in the TX FIFO.

Table 17: Status byte summary

10.2 Register Access Registers with consecutive addresses can be

accessed in an efficient way by setting the
The configuration registers of the CC2500 are burst bit in the address header. The address
located on SPI addresses from 0x00 to 0x2F. sets the start address in an internal address
Table 35 on page 51 lists all configuration counter. This counter is incremented by one
registers. The detailed description of each each new byte (every 8 clock pulses). The
register is found in Section 31.1, starting on burst access is either a read or a write access
page 54. All configuration registers can be and must be terminated by setting CSn high.
both written to and read. The read/write bit
controls if the register should be written to or For register addresses in the range 0x30-
read. When writing to registers, the status byte 0x3D, the “burst” bit is used to select between
is sent on the SO pin each time a header byte status registers and command strobes (see
or data byte is transmitted on the SI pin. below). The status registers can only be read.
When reading from registers, the status byte is Burst read is not available for status registers,
sent on the SO pin each time a header byte is so they must be read one at a time.
transmitted on the SI pin.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 21 of 77

CC2500
10.3 Command Strobes while writing data to the TX FIFO. Note that
the status byte contains the number of bytes
Command Strobes may be viewed as single
free before writing the byte in progress to the
byte instructions to CC2500. By addressing a TX FIFO. When the last byte that fits in the TX
Command Strobe register, internal sequences
FIFO is transmitted to the SI pin, the status
will be started. These commands are used to
byte received concurrently on the SO pin will
disable the crystal oscillator, enable receive
mode, enable wake-on-radio etc. The 14 indicate that one byte is free in the TX FIFO.
command strobes are listed in Table 34 on The transmit FIFO may be flushed by issuing a
page 50. SFTX command strobe. Similarly, a SFRX
The command strobe registers are accessed command strobe will flush the receive FIFO. A
in the same way as for a register write SFTX or SFRX command strobe can only be
operation, but no data is transferred. That is, issued in the IDLE, TXFIFO_UNDERLOW or
only the R/W bit (set to 0), burst access (set to RXFIFO_OVERFLOW state. Both FIFOs are
0) and the six address bits (in the range 0x30 flushed when going to the SLEEP state.
through 0x3D) are written. A command strobe
may be followed by any other SPI access 10.5 PATABLE Access
without pulling CSn high. The command
strobes are executed immediately, with the The 0x3E address is used to access the
exception of the SPWD and the SXOFF strobes PATABLE, which is used for selecting PA
that are executed when CSn goes high. power control settings. The SPI expects up to
eight data bytes after receiving the address.
When writing command strobes, the status By programming the PATABLE, controlled PA
byte is sent on the SO pin. power ramp-up and ramp-down can be
achieved. See Section 0 on page 40 for output
10.4 FIFO Access power programming details.

The 64-byte TX FIFO and the 64-byte RX The PATABLE is an 8-byte table that defines
FIFO are accessed through the 0x3F address. the PA control settings to use for each of the
When the read/write bit is zero, the TX FIFO is eight PA power values (selected by the 3-bit
accessed, and the RX FIFO is accessed when value FREND0.PA_POWER). The table is
the read/write bit is one. written and read from the lowest setting (0) to
the highest (7), one byte at a time. An index
The TX FIFO is write-only, while the RX FIFO counter is used to control the access to the
is read-only. table. This counter is incremented each time a
The burst bit is used to determine if FIFO byte is read or written to the table, and set to
access is single byte or a burst access. The the lowest index when CSn is high. When the
single byte access method expects address highest value is reached the counter restarts
with burst bit set to zero and one data byte. at zero.
After the data byte a new address is expected; The access to the PATABLE is either single
hence, CSn can remain low. The burst access byte or burst access depending on the burst
method expects one address byte and then bit. When using burst access the index counter
consecutive data bytes until terminating the will count up; when reaching 7 the counter will
access by setting CSn high. restart at 0. The read/write bit controls whether
The following header bytes access the FIFOs: the access is a write access (R/W=0) or a read
access (R/W=1).
• 0x3F: Single byte access to TX FIFO
If one byte is written to the PATABLE and this
• 0x7F: Burst access to TX FIFO value is to be read out then CSn must be set
• 0xBF: Single byte access to RX FIFO high before the read access in order to set the
index counter back to zero.
• 0xFF: Burst access to RX FIFO
Note that the content of the PATABLE is lost
when entering the SLEEP state, except for the
When writing to the TX FIFO, the status byte first byte (index 0).
(see Section 10.1) is output for each new data
byte on SO, as shown in Figure 6. This status
byte can be used to detect TX FIFO underflow

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 22 of 77

CC2500

11 Microcontroller Interface and Pin Configuration

In a typical system, CC2500 will interface to a IDLE state, the PTEST register should be
microcontroller. This microcontroller must be restored to its default value (0x7F).
able to:
• Program CC2500 into different modes, 11.3 Optional Radio Control Feature
• Read and write buffered data The CC2500 has an optional way of controlling
the radio, by reusing SI, SCLK and CSn from
• Read back status information via the 4-wire
the SPI interface. This feature allows for a
SPI-bus configuration interface (SI, SO,
simple three-pin control of the major states of
SCLK and CSn). the radio: SLEEP, IDLE, RX and TX.
This optional functionality is enabled with the
11.1 Configuration Interface MCSM0.PIN_CTRL_EN configuration bit.
The microcontroller uses four I/O pins for the State changes are commanded as follows:
SPI configuration interface (SI, SO, SCLK and When CSn is high the SI and SCLK is set to
CSn). The SPI is described in Section 10 on the desired state according to Table 18. When
page 19. CSn goes low the state of SI and SCLK is
latched and a command strobe is generated
11.2 General Control and Status Pins internally according to the control coding. It is
only possible to change state with this
The CC2500 has two dedicated configurable functionality. That means that for instance RX
pins and one shared pin that can output will not be restarted if SI and SCLK are set to
internal status information useful for control RX and CSn toggles. When CSn is low the SI
software. These pins can be used to generate and SCLK has normal SPI functionality.
interrupts on the MCU. See Section 28 on
page 45 for more details on the signals that All pin control command strobes are executed
can be programmed. The dedicated pins are immediately, except the SPWD strobe, which is
called GDO0 and GDO2. The shared pin is the delayed until CSn goes high.
SO pin in the SPI interface. The default setting
for GDO1/SO is 3-state output. By selecting
any other of the programming options the CSn SCLK SI Function
GDO1/SO pin will become a generic pin. When Chip unaffected by
1 X X
CSn is low, the pin will always function as a SCLK/SI
normal SO pin. ↓ 0 0 Generates SPWD strobe
↓ 0 1 Generates STX strobe
In the synchronous and asynchronous serial
modes, the GDO0 pin is used as a serial TX ↓ 1 0 Generates SIDLE strobe
data input pin while in transmit mode. ↓ 1 1 Generates SRX strobe
SPI SPI SPI mode (wakes up into
The GDO0 pin can also be used for an on-chip 0
mode mode IDLE if in SLEEP/XOFF)
analog temperature sensor. By measuring the
voltage on the GDO0 pin with an external ADC, Table 18: Optional pin control coding
the temperature can be calculated.
Specifications for the temperature sensor are
found in Section 4.7 on page 12.
The temperature sensor output is only
available when the frequency synthesizer is
enabled (e.g. the MANCAL, FSTXON, RX and
TX states). It is necessary to write 0xBF to the
PTEST register to use the analog temperature
sensor in the IDLE state. Before leaving the

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 23 of 77

CC2500

12 Data Rate Programming

The data rate used when transmitting, or the The data rate can be set from 1.2 kbps to 500
data rate expected in receive is programmed kbps with the minimum step size of:
by the MDMCFG3.DRATE_M and the
MDMCFG4.DRATE_E configuration registers.
The data rate is given by the formula below. Data rate Typical Data rate Data rate
As the formula shows, the programmed data start data rate stop step size
rate depends on the crystal frequency. 0.8 kbps 1.2/2.4 3.17 kbps 0.0062 kbps
kbps
RDATA =
(256 + DRATE _ M ) ⋅ 2 DRATE _ E
⋅ f XOSC 3.17 kbps 4.8 kbps 6.35 kbps 0.0124 kbps
228
6.35 kbps 9.6 kbps 12.7 kbps 0.0248 kbps
12.7 kbps 19.6 kbps 25.4 kbps 0.0496 kbps
The following approach can be used to find 25.4 kbps 38.4 kbps 50.8 kbps 0.0992 kbps
suitable values for a given data rate:
50.8 kbps 76.8 kbps 101.6 kbps 0.1984 kbps
⎢ ⎛R ⋅ 2 20 ⎞⎥ 101.6 kbps 153.6 kbps 203.1 kbps 0.3967 kbps
DRATE _ E = ⎢log 2 ⎜⎜ DATA ⎟⎟⎥
⎢⎣ ⎝ f XOSC ⎠⎥⎦ 203.1 kbps 250 kbps 406.3 kbps 0.7935 kbps
406.3 kbps 500 kbps 500 kbps 1.5869 kbps
R DATA ⋅ 2 28
DRATE _ M = − 256 Table 19: Data rate step size
f XOSC ⋅ 2 DRATE _ E
If DRATE_M is rounded to the nearest integer
and becomes 256, increment DRATE_E and
use DRATE_M=0.

13 Receiver Channel Filter Bandwidth

In order to meet different channel width MDMCFG4. MDMCFG4.CHANBW_E
requirements, the receiver channel filter is
CHANBW_M 00 01 10 11
programmable. The MDMCFG4.CHANBW_E and
MDMCFG4.CHANBW_M configuration registers 00 812 406 203 102
control the receiver channel filter bandwidth, 01 650 325 162 81
which scales with the crystal oscillator
10 541 270 135 68
frequency. The following formula gives the
relation between the register settings and the 11 464 232 116 58
channel filter bandwidth:
Table 20: Channel filter bandwidths [kHz]
f XOSC (assuming a 26 MHz crystal)
BWchannel =
8 ⋅ (4 + CHANBW _ M )·2CHANBW _ E
Above 300 kHz bandwidth, however, the
sensitivity and blocking performance may be
The CC2500 supports the following channel somewhat degraded. For best performance,
filter bandwidths: the channel filter bandwidth should be
selected so that the signal bandwidth occupies
at most 80% of the channel filter bandwidth.
The channel centre tolerance due to crystal
accuracy should also be subtracted from the
signal bandwidth. The following example
illustrates this:
With the channel filter bandwidth set to 600
kHz, the signal should stay within 80% of 600

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 24 of 77

CC2500
kHz, which is 480 kHz. Assuming 2.44 GHz ±98 kHz. If the whole transmitted signal
frequency and ±20 ppm frequency uncertainty bandwidth is to be received within 480 kHz,
for both the transmitting device and the the transmitted signal bandwidth should be
receiving device, the total frequency maximum 480 kHz–2·98 kHz, which is 284
uncertainty is ±40 ppm of 2.44 GHz, which is kHz.

14 Demodulator, Symbol Synchronizer and Data Decision

CC2500 contains an advanced and highly 14.3 Byte Synchronization

configurable demodulator. Channel filtering
Byte synchronization is achieved by a
and frequency offset compensation is
continuous sync word search. The sync word
performed digitally. To generate the RSSI level
is a 16 or 32 bit configurable field that is
(see Section 17.3 for more information) the
automatically inserted at the start of the packet
signal level in the channel is estimated. Data
by the modulator in transmit mode. The
filtering is also included for enhanced
demodulator uses this field to find the byte
performance.
boundaries in the stream of bits. The sync
word will also function as a system identifier,
14.1 Frequency Offset Compensation since only packets with the correct predefined
sync word will be received. The sync word
When using FSK, GFSK or MSK modulation, detector correlates against the user-configured
the demodulator will compensate for the offset 16-bit sync word. The correlation threshold
between the transmitter and receiver can be set to 15/16 bits match or 16/16 bits
frequency, within certain limits, by estimating match. The sync word can be further qualified
the centre of the received data. This value is using the preamble quality indicator
available in the FREQEST status register. mechanism described below and/or a carrier
Writing the value from FREQEST into sense condition. The sync word is
FSCTRL0.FREQOFF the frequency programmed with SYNC1 and SYNC0.
synthesizer is automatically adjusted
according to the estimated frequency offset. In order to make false detections of sync
words less likely, a mechanism called
Note that frequency offset compensation is not preamble quality indication (PQI) can be used
supported for OOK modulation. to qualify the sync word. A threshold value for
the preamble quality must be exceeded in
14.2 Bit Synchronization order for a detected sync word to be accepted.
See Section 17.2 on page 30 for more details.
The bit synchronization algorithm extracts the
clock from the incoming symbols. The
algorithm requires that the expected data rate
is programmed as described in Section 12 on
page 24. Re-synchronization is performed
continuously to adjust for error in the incoming
symbol rate.

15 Packet Handling Hardware Support

The CC2500 has built-in hardware support for • A two byte Synchronization Word. Can be
packet oriented radio protocols. duplicated to give a 4-byte sync word.
(Recommended).
In transmit mode, the packet handler will add
• Optionally whiten the data with a PN9
the following elements to the packet stored in
sequence.
the TX FIFO:
• Optionally Interleave and Forward Error
• A programmable number of preamble Code the data.
bytes. 4 preamble bytes is recommended. • Optionally compute and add a CRC
checksum over the data field.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 25 of 77

CC2500
In receive mode, the packet handling support Setting PKTCTRL0.WHITE_DATA=1 is recom-
will de-construct the data packet: mended for all uses, except when over-the-air
compatibility with other systems is needed.
• Preamble detection.
• Sync word detection.
15.2 Packet Format
• Optional one byte address check.
• Optionally compute and check CRC. The format of the data packet can be
• Optionally append two status bytes (see configured and consists of the following items:
Table 21 and Table 22) with RSSI value, • Preamble
Link Quality Indication and CRC status.
• Synchronization word
• Length byte or constant programmable
packet length
Bit Field name Description
• Optional address byte
7:0 RSSI RSSI value • Payload
• Optional 2 byte CRC
Table 21: Received packet status byte 1
(first byte appended after the data) The preamble pattern is an alternating
sequence of ones and zeros (01010101…).
The minimum length of the preamble is
Bit Field name Description programmable. When enabling TX, the
7 CRC_OK 1: CRC for received data OK (or modulator will start transmitting the preamble.
CRC disabled) When the programmed number of preamble
0: CRC error in received data bytes has been transmitted, the modulator will
send the sync word and then data from the TX
6:0 LQI The Link Quality Indicator
estimates how easily a received
FIFO if data is available. If the TX FIFO is
signal can be demodulated empty, the modulator will continue to send
preamble bytes until the first byte is written to
Table 22: Received packet status byte 2 the TX FIFO. The modulator will then send the
(second byte appended after the data) sync word and then the data bytes. The
number of preamble bytes is programmed with
the MDMCFG1.NUM_PREAMBLE value.
Note that register fields that control the packet
handling features should only be altered when
The synchronization word is a two-byte value
CC2500 is in the IDLE state.
set in the SYNC1 and SYNC0 registers. The
sync word provides byte synchronization of the
15.1 Data Whitening incoming packet. A one-byte sync word can be
emulated by setting the SYNC1 value to the
From a radio perspective, the ideal over the air
preamble pattern. It is also possible to emulate
data are random and DC free. This results in
a 32 bit sync word by using
the smoothest power distribution over the
occupied bandwidth. This also gives the MDMCFG2.SYNC_MODE=3 or 7. The sync word
regulation loops in the receiver uniform will then be repeated twice.
operation conditions (no data dependencies). CC2500 supports both fixed packet length
Real world data often contain long sequences protocols and variable packet length protocols.
of zeros and ones. Performance can then be Variable or fixed packet length mode can be
improved by whitening the data before used for packet up to 255 bytes. For longer
transmitting, and de-whitening in the receiver. packets, infinite packet length mode must be
With CC2500, this can be done automatically used.
by setting PKTCTRL0.WHITE_DATA=1. All Fixed packet length mode is selected by
data, except the preamble and the sync word, setting PKTCTRL0.LENGTH_CONFIG=0. The
are then XOR-ed with a 9-bit pseudo-random desired packet length is set by the PKTLEN
(PN9) sequence before being transmitted. At register. The packet length is defined as the
the receiver end, the data are XOR-ed with the payload data, excluding the length byte and
same pseudo-random sequence. This way, the the optional automatic CRC. In variable length
whitening is reversed, and the original data mode, PKTCTRL0.LENGTH_CONFIG=1, the
appear in the receiver. packet length is configured by the first byte
after the sync word. The PKTLEN register is

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 26 of 77

CC2500
used to set the maximum packet length By utilizing the infinite packet length option,
allowed in RX. Any packet received with a arbitrary packet length is available. At the start
length byte with a value greater than PKTLEN of the packet, the infinite mode must be active.
will be discarded. When less than 256 bytes remains of the
packet, the MCU sets the PKTLEN register to
With PKTCTRL0.LENGTH_CONFIG=2, the
mod(length, 256), disables infinite packet
packet length is set to infinite and transmission
length and activates fixed length packets.
and reception will continue until turned off
When the internal byte counter reaches the
manually. The infinite mode can be turned off
PKTLEN value, the transmission or reception
while a packet is being transmitted or received.
ends. Automatic CRC appending/checking can
As described in the next section, this can be
used to support packet formats with different be used (by setting PKTCTRL0.CRC_EN to 1).
length configuration than natively supported by When for example a 454-byte packet is to be
CC2500. transmitted, the MCU does the following:

15.2.1 Arbitrary Length Field Configuration • Set PKTCTRL0.LENGTH_CONFIG=2 (10).

The fixed length field can be reprogrammed • Pre-program the PKTLEN register to
during receive and transmit. This opens the mod(454,256)=198.
possibility to have a different length field • Transmit at least 198 bytes, for example
configuration than supported for variable by filling the 64-byte TX FIFO four times
length packets. At the start of reception, the (256 bytes transmitted).
packet length is set to a large value. The MCU
reads out enough bytes to interpret the length • Set PKTCTRL0.LENGTH_CONFIG=0 (00).
field in the packet. Then the PKTLEN value is
set according to this value. The end of packet • The transmission ends when the packet
will occur when the byte counter in the packet counter reaches 198. A total of
256+198=454 bytes are transmitted.
handler is equal to the PKTLEN register. Thus,
the MCU must be able to program the correct
length, before the internal counter reaches the
packet length.

Optional data whitening

Optionally FEC encoded/decoded Legend:
Optional CRC-16 calculation Inserted automatically in TX,
processed and removed in RX.
Address field
Length field
Sync word

CRC-16

Preamble bits Optional user-provided fields processed in TX,

Data field processed but not removed in RX.
(1010...1010)
Unprocessed user data (apart from FEC
and/or whitening)
8 8
8 x n bits 16/32 bits 8 x n bits 16 bits
bits bits
Figure 8: Packet format

15.3 Packet Filtering in Receive Mode 0xFF broadcast addresses when

PKTCTRL1.ADR_CHK=11. If the received
CC2500 supports three different packet-filtering
address matches a valid address, the packet is
criteria: address filtering, maximum length
received and written into the RX FIFO. If the
filtering and CRC filtering.
address match fails, the packet is discarded
and receive mode restarted (regardless of the
15.3.1 Adress Filtering
MCSM1.RXOFF_MODE setting).
Setting PKTCTRL1.ADR_CHK to any other
value than zero enables the packet address 15.3.2 Maximum Length Filtering
filter. The packet handler engine will compare
In the variable packet length mode the
the destination address byte in the packet with
PKTLEN.PACKET_LENGTH register value is
the programmed node address in the ADDR
used to set the maximum allowed packet
register and the 0x00 broadcast address when
length. If the received length byte has a larger
PKTCTRL1.ADR_CHK=10 or both 0x00 and
value than this, the packet is discarded and

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 27 of 77

CC2500
receive mode restarted (regardless of the 15.5 Packet Handling in Transmit Mode
MCSM1.RXOFF_MODE setting).
The payload that is to be transmitted must be
written into the TX FIFO. The first byte written
15.3.3 CRC Filtering must be the length byte when variable packet
The filtering of a packet when CRC check fails length is enabled. The length byte has a value
is enabled with PKTCTRL1.CRC_AUTOFLUSH. equal to the payload of the packet (including
The CRC auto flush function will flush the the optional address byte). If fixed packet
entire RX FIFO if the CRC check fails. After length is enabled, then the first byte written to
auto flushing the RX FIFO, the next state the TX FIFO is interpreted as the destination
depends on the MCSM1.RXOFF_MODE setting. address, if this feature is enabled in the device
that receives the packet.
When using the auto flush function, the
maximum packet length is 63 bytes in variable The modulator will first send the programmed
packet length mode and 64 bytes in fixed number of preamble bytes. If data is available
packet length mode. Note that the maximum in the TX FIFO, the modulator will send the
allowed packet length is reduced by two bytes two-byte (optionally 4-byte) sync word and
when PKTCTRL1.APPEND_STATUS is then the payload in the TX FIFO. If CRC is
enabled, to make room in the RX FIFO for the enabled, the checksum is calculated over all
two status bytes appended at the end of the the data pulled from the TX FIFO and the
packet. Since the entire RX FIFO is flushed result is sent as two extra bytes at the end of
when the CRC check fails, the previously the payload data.
received packet must be read out of the FIFO If whitening is enabled, the length byte,
before receiving the current packet. The MCU payload data and the two CRC bytes will be
must not read from the current packet until the whitened. This is done before the optional
CRC has been checked as OK. FEC/Interleaver stage. Whitening is enabled
by setting PKTCTRL0.WHITE_DATA=1.
15.4 CRC Check If FEC/Interleaving is enabled, the length byte,
It is possible to read back the CRC status in 2 payload data and the two CRC bytes will be
different ways: scrambled by the interleaver, and FEC
encoded before being modulated.
1) Set PKTCTRL1.APPEND_STATUS=1 and
read the CRC_OK flag in the MSB of the
second byte appended to the RX FIFO after 15.6 Packet Handling in Receive Mode
the packet data. This requires double buffering In receive mode, the demodulator and packet
of the packet, i.e. the entire packet content of handler will search for a valid preamble and
the RX FIFO must be completely read out the sync word. When found, the demodulator
before it is possible to check whether the CRC has obtained both bit and byte synchronism
indication is OK or not. and will receive the first payload byte.
2) To avoid reading the whole RX FIFO, If FEC/Interleaving is enabled, the FEC
another solution is to use the decoder will start to decode the first payload
PKTCTRL1.CRC_AUTOFLUSH feature. If this byte. The interleaver will de-scramble the bits
feature is enabled, the entire RX FIFO will be before any other processing is done to the
flushed if the CRC check fails. If data.
GDOx_CFG=0x06 the GDOx pin will be
If whitening is enabled, the data will be de-
asserted when a sync word is found. The
whitened at this stage.
GDOx pin will be de-asserted at the end of the
packet. When the latter occurs the MCU When variable packet length is enabled, the
should read the number of bytes in the RX first byte is the length byte. The packet handler
FIFO from the RXBYTES.NUM_RXBYTES stores this value as the packet length and
status register. If RXBYTES.NUM_RXBYTES=0 receives the number of bytes indicated by the
the CRC check failed and the FIFO was length byte. If fixed packet length is used, the
flushed. If RXBYTES.NUM_RXBYTES>0 the packet handler will accept the programmed
CRC check was OK and data can be read out number of bytes.
of the FIFO. Next, the packet handler optionally checks the
address and only continues the reception if the
address matches. If automatic CRC check is

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 28 of 77

CC2500
enabled, the packet handler computes CRC At the end of the payload, the packet handler
and matches it with the appended CRC will optionally write two extra packet status
checksum. bytes that contain CRC status, link quality
indication and RSSI value.

16 Modulation Formats

CC2500 supports amplitude, frequency and 16.2 Minimum Shift Keying

phase shift modulation formats. The desired
When using MSK1, the complete transmission
modulation format is set in the
(preamble, sync word and payload) will be
MDMCFG2.MOD_FORMAT register. MSK modulated.
Optionally, the data stream can be Manchester Phase shifts are performed with a constant
coded by the modulator and decoded by the transition time. This means that the rate of
demodulator. This option is enabled by setting change for the 180-degree transition is twice
MDMCFG2.MANCHESTER_EN=1. Manchester that of the 90-degree transition.
encoding is not supported at the same time as
using the FEC/Interleaver option. Manchester The fraction of a symbol period used to
coding can be used with the 2-ary modulation change the phase can be modified with the
formats (2-FSK, GFSK, OOK and MSK). DEVIATN.DEVIATION_M setting. This is
equivalent to changing the shaping of the
symbol. Setting DEVIATN.DEVIATION_M=7
16.1 Frequency Shift Keying will generate a standard shaped MSK signal.
2-FSK can optionally be shaped by a The MSK modulation format implemented in
Gaussian filter with BT=1, producing a GFSK
CC2500 inverts the sync word and data
modulated signal.
compared to e.g. signal generators.
The frequency deviation is programmed with
the DEVIATION_M and DEVIATION_E values
16.3 Amplitude Modulation
in the DEVIATN register. The value has an
exponent/mantissa form, and the resultant The supported amplitude modulation On-Off
deviation is given by: Keying (OOK) simply turns on or off the PA to
modulate 1 and 0 respectively.
f xosc
f dev = ⋅ (8 + DEVIATION _ M ) ⋅ 2 DEVIATION _ E
217
1
Identical to offset QPSK with half-sine
shaping (data coding may differ)
The symbol encoding is shown in Table 23.
Format Symbol Coding
2-FSK/GFSK ‘0’ – Deviation
‘1’ + Deviation

Table 23: Symbol encoding for FSK

modulation

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 29 of 77

CC2500

17 Received Signal Qualifiers and Link Quality Information

CC2500 has several qualifiers that can be used PKTCTRL1.PQT. A threshold of 4·PQT for this
to increase the likelihood that a valid sync counter is used to gate sync word detection.
word is detected. By setting the value to zero, the preamble
quality qualifier of the sync word is disabled.
17.1 Sync Word Qualifier A “Preamble Quality Reached” flag can also
be observed on one of the GDO pins and in
If sync word detection in RX is enabled in
the status register bit
register MDMCFG2 the CC2500 will not start PKTSTATUS.PQT_REACHED. This flag asserts
filling the RX FIFO and perform the packet when the received signal exceeds the PQT.
filtering described in Section 15.3 before a
valid sync word has been detected. The sync
word qualifier mode is set by 17.3 RSSI
MDMCFG2.SYNC_MODE and is summarized in
The RSSI value is an estimate of the signal
Table 24. Carrier sense in Table 24 is level in the current channel. This value is
described in Section 17.4. based on the current gain setting in the RX
chain and the measured signal level in the
channel.
MDMCFG2. Sync word qualifier mode
In RX mode, the RSSI value can be read
SYNC_MODE
continuously from the RSSI status register,
000 No preamble/sync until the demodulator detects a sync word
001 15/16 sync word bits detected (when sync word detection is enabled). At that
point, the RSSI readout value is frozen until
010 16/16 sync word bits detected the next time the chip enters the RX state. The
011 30/32 sync word bits detected RSSI value is in dB with ½dB resolution.
100 No preamble/sync, carrier sense If PKTCTRL1.APPEND_STATUS is enabled, a
above threshold
snapshot of the RSSI during the first 8 bytes of
101 15/16 + carrier sense above threshold the packet is automatically added to the end of
110 16/16 + carrier sense above threshold each received packet.
111 30/32 + carrier sense above threshold The RSSI value read from the RSSI status
register is a 2’s complement number. The
Table 24: Sync word qualifier mode following procedure can be used to convert the
RSSI reading to an absolute power level
(RSSI_dBm).
17.2 Preamble Quality Threshold (PQT)
1) Read the RSSI status register
The Preamble Quality Threshold (PQT) sync-
word qualifier adds the requirement that the 2) Convert the reading from a hexadecimal
received sync word must be preceded with a number to a decimal number (RSSI_dec)
preamble with a quality above a programmed
3) If RSSI_dec ≥ 128 then RSSI_dBm =
threshold.
(RSSI_dec - 256)/2 – RSSI_offset
Another use of the preamble quality threshold
4) Else if RSSI_dec < 128 then RSSI_dBm =
is as a qualifier for the optional RX termination
(RSSI_dec)/2 – RSSI_offset
timer. See Section 19.7 on page 37 for details.
The preamble quality estimator increases an
internal counter by one each time a bit is Table 25 gives typical values for the
received that is different from the previous bit, RSSI_offset.
and decreases the counter by 4 each time a
bit is received that is the same as the last bit. Figure 9 shows typical plots of RSSI reading
The counter saturates at 0 and 31. The as a function of input power level for different
threshold is configured with the register field data rates.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 30 of 77

CC2500

Data rate RSSI_offset (decimal)

2.4 kbps 71
10 kbps 69
250 kbps 72
500 kbps 72

Table 25: Typical RSSI_offset values

0.0

-10.0

-20.0

-30.0

-40.0
RSSI readout [dBm]

-50.0

-60.0

-70.0

-80.0

-90.0

-100.0

-110.0

-120.0
-120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0
Input pow er [dBm]

2.4 kbps 10 kbps 250 kbps 250 kbps, reduced current 500 kbps

Figure 9: Typical RSSI value vs. input power level for some typical data rates

17.4 Carrier Sense (CS) search to be performed. The signal can also
be observed on one of the GDO pins and in
The Carrier Sense flag is used as a sync word
the status register bit PKTSTATUS.CS.
qualifier and for CCA. The CS flag can be set
based on two conditions, which can be Other uses of Carrier Sense include the TX-If-
individually adjusted: CCA function (see Section 17.5 on page 32)
and the optional fast RX termination (see
• CS is asserted when the RSSI is above a
Section 19.7 on page 37).
programmable absolute threshold, and de-
asserted when RSSI is below the same CS can be used to avoid interference from e.g.
threshold (with hysteresis). WLAN.
• CS is asserted when the RSSI has
17.4.1 CS Absolute Threshold
increased with a programmable number of
dB from one RSSI sample to the next, and The absolute threshold related to the RSSI
de-asserted when RSSI has decreased value is given by:
with the same number of dB. This setting
THRRSSI = MAGN _ TARGET +
is not dependent on the absolute signal
level and is thus useful to detect signals in CARRIER _ SENSE _ ABS _ THR − GAIN MAX
environments with a time varying noise
The maximum possible gain can be reduced
floor.
using the AGCCTRL2.MAX_LNA_GAIN and
AGCCTRL2.MAX_DVGA_GAIN register fields.
Carrier Sense (CS) can be used as a sync CARRIER_SENSE_ABS_THR is programmable
word qualifier that requires the signal level to in 1 dB steps from -7 dB to + 7dB. Table 26
be higher than the threshold for a sync word and Table 27 show the RSSI readout values

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 31 of 77

CC2500
at the CS threshold at 2.4 kbps and 250 kbps level in the channel into the demodulator.
data rate respectively. The default Increasing this value reduces the headroom
CARRIER_SENSE_ABS_THR = 0 (0 dB) and for blockers, and therefore close-in selectivity.
MAGN_TARGET = 3 (33 dB) have been used.
17.4.2 CS relative threshold
The relative threshold detects sudden changes
MAX_DVGA_GAIN[1:0] in the measured signal level. This setting is not
00 01 10 11 dependent on the absolute signal level and is
thus useful to detect signals in environments
000 -99 -93 -87 -81.5
with a time varying noise floor. The register
MAX_LNA_GAIN[2:0]

001 -97 -90.5 -85 -78.5 field AGCCTRL1.CARRIER_SENSE_REL_THR

010 -93.5 -87 -82 -76 is used to enable/disable relative CS, and to
select threshold of 6 dB, 10 dB or 14 dB RSSI
011 -91.5 -86 -80 -74
change
100 -90.5 -84 -78 -72.5
101 -88 -82.5 -76 -70 17.5 Clear Channel Assessment (CCA)
110 -84.5 -78.5 -73 -67 The Clear Channel Assessment is used to
111 -82.5 -76 -70 -64 indicate if the current channel is free or busy.
The current CCA state is viewable on any of
Table 26: Typical RSSI value in dBm at CS the GDO pins.
threshold with default MAGN_TARGET at 2.4
MCSM1.CCA_MODE selects the mode to use
kbps
when determining CCA.
When the STX or SFSTXON command strobe is
MAX_DVGA_GAIN[1:0] given while CC2500 is in the RX state, the TX
00 01 10 11 state is only entered if the clear channel
requirements are fulfilled. The chip will
000 -96 -90 -84 -78.5 otherwise remain in RX. This feature is called
MAX_LNA_GAIN[2:0]

001 -94.5 -89 -83 -77.5 TX if CCA.

010 -92.5 -87 -81 -75 Four CCA requirements can be programmed:
011 -91 -85 -78.5 -73 • Always (CCA disabled, always goes to TX)
100 -87.5 -82 -76 -70
• If RSSI is below threshold
101 -85 -79.5 -73.5 -67.5
• Unless currently receiving a packet
110 -83 -76.5 -70.5 -65
• Both the above (RSSI below threshold and
111 -78 -72 -66 -60
not currently receiving a packet)
Table 27: Typical RSSI value in dBm at CS
threshold with default MAGN_TARGET at 17.6 Link Quality Indicator (LQI)
250 kbps
The Link Quality Indicator is a metric of the
If the threshold is to be set high, e.g. only current quality of the received signal. If
signals with good strength are wanted, the PKTCTRL1.APPEND_STATUS is enabled, the
threshold should be adjusted upwards by first value is automatically appended to the end of
reducing the MAX_LNA_GAIN value and then each received packet. The value can also be
the MAX_DVGA_GAIN value. This will reduce read from the LQI status register. The LQI is
power consumption in the receiver front end, calculated over the 64 symbols following the
since the highest gain settings are avoided. sync word (first 8 packet bytes for 2-ary
The MAGN_TARGET setting is a compromise modulation). LQI is best used as a relative
between blocker tolerance/selectivity and measurement of the link quality, since the
sensitivity. The value sets the desired signal value is dependent on the modulation format.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 32 of 77

CC2500

18 Forward Error Correction with Interleaving

18.1 Forward Error Correction (FEC) 18.2 Interleaving
CC2500 has built in support for Forward Error Data received through radio channels will
Correction (FEC). To enable this option, set often experience burst errors due to
MDMCFG1.FEC_EN to 1. FEC is employed on interference and time-varying signal strengths.
the data field and CRC word in order to reduce In order to increase the robustness to errors
the gross bit error rate when operating near spanning multiple bits, interleaving is used
the sensitivity limit. Redundancy is added to when FEC is enabled. After de-interleaving, a
the transmitted data in such a way that the continuous span of errors in the received
receiver can restore the original data in the stream will become single errors spread apart.
presence of some bit errors.
CC2500 employs matrix interleaving, which is
The use of FEC allows correct reception at a illustrated in Figure 10. The on-chip
lower SNR, thus extending communication interleaving and de-interleaving buffers are 4 x
range. Alternatively, for a given SNR, using 4 matrices. In the transmitter, the data bits are
FEC decreases the bit error rate (BER). As the written into the rows of the matrix, whereas the
packet error rate (PER) is related to BER by: bit sequence to be transmitted is read from the
columns of the matrix and fed to the rate ½
PER = 1 − (1 − BER) packet _ length convolutional coder. Conversely, in the
receiver, the received symbols are written into
a lower BER can be used to allow longer the columns of the matrix, whereas the data
packets, or a higher percentage of packets of passed onto the convolutional decoder is read
a given length, to be transmitted successfully. from the rows of the matrix.
Finally, in realistic ISM radio environments,
transient and time-varying phenomena will When FEC and interleaving is used, the
produce occasional errors even in otherwise amount of data transmitted over the air must
good reception conditions. FEC will mask such be a multiple of the size of the interleaver
errors and, combined with interleaving of the buffer (two bytes). In addition, at least one
coded data, even correct relatively long extra byte is required for trellis termination.
periods of faulty reception (burst errors). The packet control hardware therefore
automatically inserts one or two extra bytes at
The FEC scheme adopted for CC2500 is the end of the packet, so that the total length
convolutional coding, in which n bits are of the data to be interleaved is an even
generated based on k input bits and the m number. Note that these extra bytes are
most recent input bits, forming a code stream invisible to the user, as they are removed
able to withstand a certain number of bit errors before the received packet enters the RX
between each coding state (the m-bit window). FIFO.
The convolutional coder is a rate 1/2 code with Due to the implementation of the FEC and
a constraint length of m=4. The coder codes interleaver, the data to be interleaved must be
one input bit and produces two output bits; at least two bytes. One byte long fixed length
hence, the effective data rate is halved. packets without CRC is therefore not
supported when FEC/interleaving is enabled.

1) Storing coded 2) Transmitting 3) Receiving 4) Passing on data

data interleaved data interleaved data to decoder
Demodulator
Modulator

Decoder
Encoder

TX RX
Data Data

Transmitter Receiver

Figure 10: General principle of matrix interleaving

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 33 of 77

CC2500

19 Radio Control

SIDLE

SPWD | SWOR
SLEEP
CAL_COMPLETE 0

MANCAL IDLE CSn = 0 | WOR

3,4,5 1
SXOFF
SCAL
CSn = 0
XOFF
SRX | STX | SFSTXON | WOR 2

FS_WAKEUP
6,7
FS_AUTOCAL = 01
&
SRX | STX | SFSTXON | WOR

FS_AUTOCAL = 00 | 10 | 11
& CALIBRATE
SRX | STX | SFSTXON | WOR 8

CAL_COMPLETE
SETTLING
SFSTXON 9,10,11

FSTXON
18
STX SRX | WOR

STX
SFSTXON | RXOFF_MODE = 01
TXOFF_MODE=01

STX | RXOFF_MODE = 10 RXTX_SETTLING ( STX | SFSTXON ) & CCA

21 |
TX RXOFF_MODE = 01 | 10 RX
TXOFF_MODE = 10 RXOFF_MODE = 11
19,20 13,14,15

SRX | TXOFF_MODE = 11 TXRX_SETTLING

16

TXOFF_MODE = 00 RXOFF_MODE = 00
TXFIFO_UNDERFLOW RXFIFO_OVERFLOW
& &
FS_AUTOCAL = 10 | 11 FS_AUTOCAL = 10 | 11

CALIBRATE
TXOFF_MODE = 00 12 RXOFF_MODE = 00
&
&
FS_AUTOCAL = 00 | 01
TX_UNDERFLOW FS_AUTOCAL = 00 | 01 RX_OVERFLOW
22 17

SFTX SFRX

IDLE
1

Figure 11: Complete radio control state diagram

CC2500 has a built-in state machine that is shown in Figure 4 on page 13. The complete
used to switch between different operation radio control state diagram is shown in Figure
states (modes). The change of state is done 11. The numbers refer to the state number
either by using command strobes or by readable in the MARCSTATE status register.
internal events such as TX FIFO underflow. This register is primarily for test purposes.
A simplified state diagram, together with
typical usage and current consumption, is

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 34 of 77

CC2500
19.1 Power-On Start-Up Sequence XOSC will be turned off when CSn is released
(goes high). The XOSC will be automatically
When the power supply is turned on, the
system must be reset. One of the following two turned on again when CSn goes low. The state
sequences must be followed: Automatic machine will then go to the IDLE state. The SO
power-on reset (POR) or manual reset. pin on the SPI interface must be zero before
the SPI interface is ready to be used; as
19.1.1 Automatic POR described in Section 19 on page 20.

A power-on reset circuit is included in the If the XOSC is forced on, the crystal will
CC2500. The minimum requirements stated in always stay on even in the SLEEP state.
Section 4.9 must be followed for the power-on Crystal oscillator start-up time depends on
reset to function properly. The internal power- crystal ESR and load capacitances. The
up sequence is completed when CHIP_RDYn electrical specification for the crystal oscillator
goes low. CHIP_RDYn is observed on the SO can be found in Section 4.4 on page 10.
pin after CSn is pulled low. See Section 10.1
for more details on CHIP_RDYn.
19.3 Voltage Regulator Control
19.1.2 Manual Reset The voltage regulator to the digital core is
controlled by the radio controller. When the
The other global reset possibility on CC2500 is chip enters the SLEEP state, which is the state
the SRES command strobe. By issuing this with the lowest current consumption, this
strobe, all internal registers and states are set regulator is disabled. This occurs after CSn is
to the default, idle state. The manual power-up released when a SPWD command strobe has
sequence is as follows (see Figure 12): been sent on the SPI interface. The chip is
• Set SCLK=1 and SI=0, to avoid potential now in the SLEEP state. Setting CSn low again
problems with pin control mode (see will turn on the regulator and crystal oscillator
Section 11.3 on page 23). and make the chip enter the IDLE state.

• Strobe CSn low / high. When wake on radio is enabled, the WOR
module will control the voltage regulator as
• Hold CSn high for at least 40 µs. described in Section 19.5.
• Pull CSn low and wait for SO to go low
(CHIP_RDYn). 19.4 Active Modes

• Issue the SRES strobe on the SI line. CC2500 has two active modes: receive and
transmit. These modes are activated directly
• When SO goes low again, reset is by the MCU by using the SRX and STX
complete and the chip is in the IDLE state. command strobes, or automatically by Wake
40µs
on Radio.
The frequency synthesizer must be calibrated
CSn
regularly. CC2500 has one manual calibration
SO option (using the SCAL strobe), and three
Unknown/ don't care automatic calibration options, controlled by the
SRES done
MCSM0.FS_AUTOCAL setting:

Figure 12: Power-on reset with SRES • Calibrate when going from IDLE to
either RX or TX (or FSTXON)

19.2 Crystal Control • Calibrate when going from either RX

or TX to IDLE
The crystal oscillator (XOSC) is either
automatically controlled or always on, if • Calibrate every fourth time when going
MCSM0.XOSC_FORCE_ON is set. from either RX or TX to IDLE
In the automatic mode, the XOSC will be The calibration takes a constant number of
turned off if the SXOFF or SPWD command XOSC cycles (see Table 28 for timing details).
strobes are issued; the state machine then When RX is activated, the chip will remain in
goes to XOFF or SLEEP respectively. This receive mode until a packet is successfully
can only be done from the IDLE state. The

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 35 of 77

CC2500
received or the RX termination timer expires IDLE state when the timer expires. After a
(see Section 19.7). Note: the probability that a programmable time in RX, the chip goes back
false sync word is detected can be reduced by to SLEEP, unless a packet is received. See
using PQT, CS, maximum sync word length Section 19.7 for details on how the timeout
and sync word qualifier mode as describe in works.
Section 17. After a packet is successfully
received the radio controller will then go to the CC2500 can be set up to signal the MCU that a
packet has been received by using the GDO
state indicated by the MCSM1.RXOFF_MODE
pins. If a packet is received, the
setting. The possible destinations are:
MCSM1.RXOFF_MODE will determine the
• IDLE behaviour at the end of the received packet.
When the MCU has read the packet, it can put
• FSTXON: Frequency synthesizer on
the chip back into SLEEP with the SWOR strobe
and ready at the TX frequency.
from the IDLE state. The FIFO will lose its
Activate TX with STX.
contents in the SLEEP state.
• TX: Start sending preambles The WOR timer has two events, Event 0 and
• RX: Start search for a new packet Event 1. In the SLEEP state with WOR
activated, reaching Event 0 will turn the digital
regulator and start the crystal oscillator. Event
Similarly, when TX is active the chip will 1 follows Event 0 after a programmed timeout.
remain in the TX state until the current packet The time between two consecutive Event 0 is
has been successfully transmitted. Then the programmed with a mantissa value given by
state will change as indicated by the WOREVT1.EVENT0 and WOREVT0.EVENT0,
MCSM1.TXOFF_MODE setting. The possible and an exponent value set by
destinations are the same as for RX. WORCTRL.WOR_RES. The equation is:
The MCU can manually change the state from
RX to TX and vice versa by using the
command strobes. If the radio controller is 750
currently in transmit and the SRX strobe is t Event 0 = ⋅ EVENT 0 ⋅ 2 5⋅WOR _ RES
f XOSC
used, the current transmission will be ended
and the transition to RX will be done.
If the radio controller is in RX when the STX or The Event 1 timeout is programmed with
SFSTXON command strobes are used, the “TX WORCTRL.EVENT1. Figure 13 shows the
if clear channel” function will be used. If the timing relationship between Event 0 timeout
channel is not clear, the chip will remain in RX. and Event 1 timeout.
The MCSM1.CCA_MODE setting controls the
conditions for clear channel assessment. See
Section 17.5 on page 32 for details. Rx timeout
The SIDLE command strobe can always be
State: SLEEP IDLE RX SLEEP IDLE RX
used to force the radio controller to go to the
IDLE state. Event0 Event1 Event0 Event1
t
tEvent0
19.5 Wake On Radio (WOR) tEvent0
The optional Wake on Radio (WOR) tEvent1 tEvent1
functionality enables CC2500 to periodically
wake up from deep sleep and listen for
incoming packets without MCU interaction. Figure 13: Event 0 and Event 1 relationship
When WOR is enabled, the CC2500 will go to
the SLEEP state when CSn is released after
the SWOR command strobe has been sent on 19.5.1 RC Oscillator and Timing
the SPI interface. The RC oscillator must be The frequency of the low-power RC oscillator
enabled before the WOR strobe can be used, used for the WOR functionality varies with
as it is the clock source for the WOR timer. temperature and supply voltage. In order to
The on-chip timer will get CC2500 back into the

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 36 of 77

CC2500
keep the frequency as accurate as possible, The main use for this functionality is wake-on-
the RC oscillator will be calibrated whenever radio (WOR), but it may be useful for other
possible, which is when the XOSC is running applications. The termination timer starts when
and the chip is not in the SLEEP state. When in RX state. The timeout is programmable with
the power and XOSC is enabled, the clock the MCSM2.RX_TIME setting. When the timer
used by the WOR timer is a divided XOSC expires, the radio controller will check the
clock. When the chip goes to the sleep state, condition for staying in RX; if the condition is
the RC oscillator will use the last valid not met, RX will terminate. After the timeout,
calibration result. The frequency of the RC the condition will be checked continuously.
oscillator is locked to the main crystal
frequency divided by 750. The programmable conditions are:
• MCSM2.RX_TIME_QUAL=0: Continue
19.6 Timing receive if sync word has been found

The radio controller controls most timing in • MCSM2.RX_TIME_QUAL=1: Continue

CC2500, such as synthesizer calibration, PLL receive if sync word has been found or
lock and RT/TX turnaround times. Timing from preamble quality is above threshold (PQT)
IDLE to RX and IDLE to TX is constant,
dependent on the auto calibration setting.
RX/TX and TX/RX turnaround times are If the system can expect the transmission to
constant. The calibration time is constant have started when enabling the receiver, the
18739 clock periods. Table 28 shows timing in MCSM2.RX_TIME_RSSI function can be used.
crystal clock cycles for key state transitions. The radio controller will then terminate RX if
the first valid carrier sense sample indicates
Power on time and XOSC start-up times are no carrier (RSSI below threshold). See Section
variable, but within the limits stated in Table 7. 17.4 on page 31 for details on Carrier Sense.
Note that in a frequency hopping spread
spectrum or a multi-channel protocol the For OOK modulation, lack of carrier sense is
calibration time can be reduced from 721 µs to only considered valid after eight symbol
approximately 150 µs. This is explained in periods. Thus, the MCSM2.RX_TIME_RSSI
Section 30.2. function can be used in OOK mode when the
distance between “1” symbols is 8 or less.
If RX terminates due to no carrier sense when
Description XOSC 26 MHz the MCSM2.RX_TIME_RSSI function is used,
periods crystal
or if no sync word was found when using the
Idle to RX, no calibration 2298 88.4 µs MCSM2.RX_TIME timeout function, the chip
Idle to RX, with calibration ~21037 809 µs will always go back to IDLE if WOR is disabled
and back to SLEEP if WOR is enabled.
Idle to TX/FSTXON, no calibration 2298 88.4 µs
Otherwise, the MCSM1.RXOFF_MODE setting
Idle to TX/FSTXON, with calibration ~21037 809 µs determines the state to go to when RX ends.
TX to RX switch 560 21.5 µs
Note that in wake-on-radio (WOR) mode, the
RX to TX switch 250 9.6 µs WOR state is cleared in the latter case. This
RX or TX to IDLE, no calibration 2 0.1 µs means that the chip will not automatically go
back to SLEEP again, even if e.g. the address
RX or TX to IDLE, with calibration ~18739 721 µs field in the packet did not match. It is therefore
Manual calibration ~18739 721 µs recommended to always wake up the
microcontroller on sync word detection when
Table 28: State transition timing using WOR mode. This can be done by
selecting output signal 6 (see Table 33 on
19.7 RX Termination Timer page 46) on one of the programmable GDO
output pins, and programming the
CC2500 has optional functions for automatic microcontroller to wake up on an edge-
termination of RX after a programmable time. triggered interrupt from this GDO pin.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 37 of 77

CC2500

20 Data FIFO

The CC2500 contains two 64 byte FIFOs, one the corresponding thresholds for the RX and
for received data and one for data to be TX FIFOs. The threshold value is coded in
transmitted. The SPI interface is used to read opposite directions for the RX FIFO and TX
from the RX FIFO and write to the TX FIFO. FIFO. This gives equal margin to the overflow
Section 10.4 contains details on the SPI FIFO and underflow conditions when the threshold
access. The FIFO controller will detect is reached.
overflow in the RX FIFO and underflow in the
A flag will assert when the number of bytes in
TX FIFO.
the FIFO is equal to or higher than the
When writing to the TX FIFO it is the programmed threshold. The flag is used to
responsibility of the MCU to avoid TX FIFO generate the FIFO status signals that can be
overflow. A TX FIFO overflow will result in an viewed on the GDO pins (see Section 28 on
error in the TX FIFO content. page 45).
Likewise, when reading the RX FIFO the MCU Figure 15 shows the number of bytes in both
must avoid reading the RX FIFO past its the RX FIFO and TX FIFO when the threshold
empty value, since an RX FIFO underflow will flag toggles, in the case of FIFO_THR=13.
result in an error in the data read out of the RX Figure 14 shows the flag as the respective
FIFO. FIFO is filled above the threshold, and then
drained below.
The chip status byte that is available on the SO
pin while transferring the SPI address contains
the fill grade of the RX FIFO if the address is a NUM_RXBYTES 53 54 55 56 57 56 55 54 53

read operation and the fill grade of the TX GDO

FIFO is the address is a write operation.

Section 10.1 on page 20 contains more details
on this. NUM_TXBYTES 6 7 8 9 10 9 8 7 6

GDO
The number of bytes in the RX FIFO and TX
FIFO can also be read from the status
Figure 14: FIFO_THR=13 vs. number of bytes
registers RXBYTES.NUM_RXBYTES and
in FIFO (GDOx_CFG=0x00 in Rx and
TXBYTES.NUM_TXBYTES respectively. If
receiving data while reading the last byte in GDOx_CFG=0x02 in Tx)
the RX FIFO, the RX FIFO pointer is not
updated, resulting in a duplication of the last
byte read. FIFO_THR Bytes in TX FIFO Bytes in RX FIFO
0 (0000) 61 4
To avoid this problem one should never empty 1 (0001) 57 8
the RX FIFO before the last byte of the packet 2 (0010) 53 12
is received. The following software fix can be
3 (0011) 49 16
used:
4 (0100) 45 20
1. Read RXBYTES.NUM_RXBYTES 5 (0101) 41 24
6 (0110) 37 28
2. If RXBYTES.NUM_RXBYTES < packet
7 (0111) 33 32
length, read RXBYTES.NUM_RXBYTES-1
8 (1000) 29 36
bytes from the FIFO
9 (1001) 25 40
3. Repeat until RXBYTES.NUM_RXBYTES = 10 (1010) 21 44
number of remaining bytes of the packet 11 (1011) 17 48
12 (1100) 13 52
4. Read the remaining bytes from the FIFO
13 (1101) 9 56
14 (1110) 5 60
The 4-bit FIFOTHR.FIFO_THR setting is used 15 (1111) 1 64
to program threshold points in the FIFOs. Table 29: FIFO_THR settings and the
Table 29 lists the 16 FIFO_THR settings and corresponding FIFO thresholds

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 38 of 77

CC2500

Overflow
margin

FIFO_THR=13

56 bytes

FIFO_THR=13

Underflow
margin 8 bytes

RXFIFO TXFIFO

Figure 15: Example of FIFOs at threshold

21 Frequency Programming

The frequency programming in CC2500 is The base or start frequency is set by the 24 bit
designed to minimize the programming frequency word located in the FREQ2, FREQ1
needed in a channel-oriented system. and FREQ0 registers. This word will typically
To set up a system with channel numbers, the be set to the centre of the lowest channel
desired channel spacing is programmed with frequency that is to be used.
the MDMCFG0.CHANSPC_M and The desired channel number is programmed
MDMCFG1.CHANSPC_E registers. The channel with the 8-bit channel number register,
spacing registers are mantissa and exponent CHANNR.CHAN, which is multiplied by the
respectively. channel offset. The resultant carrier frequency
is given by:

f carrier =
f XOSC
2 16
( (
⋅ FREQ + CHAN ⋅ (256 + CHANSPC _ M ) ⋅ 2 CHANSPC _ E −2 ))

With a 26 MHz crystal the maximum channel Note that the SmartRF® Studio software
spacing is 405 kHz. To get e.g. 1 MHz channel
automatically calculates the optimum
spacing one solution is to use 333 kHz
FSCTRL1.FREQ_IF register setting based on
channel spacing and select each third channel
channel spacing and channel filter bandwidth.
in CHANNR.CHAN.
If any frequency programming register is
The preferred IF frequency is programmed
altered when the frequency synthesizer is
with the FSCTRL1.FREQ_IF register. The IF running, the synthesizer may give an
frequency is given by: undesired response. Hence, the frequency
f XOSC programming should only be updated when
f IF = ⋅ FREQ _ IF the radio is in the IDLE state.
210

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 39 of 77

CC2500

22 VCO
The VCO is completely integrated on-chip. The calibration can be initiated automatically
or manually. The synthesizer can be
automatically calibrated each time the
22.1 VCO and PLL Self-Calibration synthesizer is turned on, or each time the
The VCO characteristics will vary with synthesizer is turned off. This is configured
temperature and supply voltage changes, as with the MCSM0.FS_AUTOCAL register setting.
well as the desired operating frequency. In In manual mode, the calibration is initiated
order to ensure reliable operation, CC2500 when the SCAL command strobe is activated
includes frequency synthesizer self-calibration in the IDLE mode.
circuitry. This calibration should be done
Note that the calibration values are maintained
regularly, and must be performed after turning
in sleep mode, so the calibration is still valid
on power and before using a new frequency
after waking up from sleep mode (unless
(or channel). The number of XOSC cycles for
supply voltage or temperature has changed
completing the PLL calibration is given in
significantly).
Table 28 on page 37.

23 Voltage Regulators

CC2500 contains several on-chip linear voltage If the chip is programmed to enter power-down
regulators, which generate the supply voltage mode, (SPWD strobe issued), the power will be
needed by low-voltage modules. These turned off after CSn goes high. The power and
voltage regulators are invisible to the user, and crystal oscillator will be turned on again when
can be viewed as integral parts of the various CSn goes low.
modules. The user must however make sure
that the absolute maximum ratings and The voltage regulator output should only be
required pin voltages in Table 1 and Table 13 used for driving the CC2500.
are not exceeded. The voltage regulator for
the digital core requires one external
decoupling capacitor.
Setting the CSn pin low turns on the voltage
regulator to the digital core and starts the
crystal oscillator. The SO pin on the SPI
interface must go low before using the serial
interface (setup time is given in Table 16).

24 Output Power Programming

The RF output power level from the device has The power ramping at the start and at the end
two levels of programmability, as illustrated in of a packet can be turned off by setting
Figure 16. Firstly, the special PATABLE FREND0.PA_POWER to zero and then
register can hold up to eight user selected program the desired output power to index
output power settings. Secondly, the 3-bit zero in the PATABLE.
FREND0.PA_POWER value selects the
Table 31 contains recommended PATABLE
PATABLE entry to use. This two-level
settings for various output levels and
functionality provides flexible PA power ramp
frequency bands. See Section 10.5 on page
up and ramp down at the start and end of
22 for PATABLE programming details.
transmission. All the PA power settings in the
PATABLE from index 0 up to the PATABLE must be programmed in burst mode
FREND0.PA_POWER value are used. if you want to write to other entries than
PATABLE[0].

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 40 of 77

CC2500

PATABLE(7)[7:0]
The PA uses this
PATABLE(6)[7:0]
setting.
PATABLE(5)[7:0]
PATABLE(4)[7:0]
Settings 0 to PA_POWER are
PATABLE(3)[7:0] used during ramp-up at start of
transmission and ramp-down at
PATABLE(2)[7:0] end of transmission, and for
PATABLE(1)[7:0] ASK/OOK modulation.

PATABLE(0)[7:0]

Index into PATABLE(7:0)

The SmartRF® Studio software
e.g 6 should be used to obtain optimum
PATABLE settings for various
PA_POWER[2:0] output powers.
in FREND0 register

Figure 16: PA_POWER and PATABLE

Output power, Current consumption,

Default power setting
typical [dBm] typical [mA]
0xC6 -11.8 11.1

Table 30: Output power and current consumption for default PATABLE setting

Output power, PATABLE Current consumption,

typical, +25°C, 3.0 V [dBm] value typical [mA]
(–55 or less) 0x00 8.4
–30 0x50 9.9
–28 0x44 9.7
–26 0xC0 10.2
–24 0x84 10.1
–22 0x81 10.0
–20 0x46 10.1
–18 0x93 11.7
–16 0x55 10.8
–14 0x8D 12.2
–12 0xC5 11.1
–10 0x97 12.2
–8 0x6E 14.1
–6 0x7F 15.1
–4 0xA9 16.2
–2 0xBB 17.7
0 0xFE 21.2
1.5 0xFF 21.5

Table 31: Optimum PATABLE settings for various output power levels (subject to changes)

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 41 of 77

CC2500

25 Selectivity Graphs
Figure 17 to Figure 21 show the typical selectivity performance (adjacent and alternate rejection).

50

40

30
Selectivity [dB]

20

10

0
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

-10
Frequency offset [MHz]

Figure 17: Typical selectivity at 2.4 kbps. IF frequency is 273.9 kHz.

MDMCFG2.DEM_DCFILT_OFF = 1

40

35

30

25

20
Selectivity [dB]

15

10

0
-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
-5

-10
Fre que ncy offse t [M Hz]

Figure 18: Typical selectivity at 10 kbps. IF frequency is 273.9 kHz.

MDMCFG2.DEM_DCFILT_OFF = 1

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 42 of 77

CC2500

50

40

30

Selectivity [dB] 20

10

0
-3 -2 -1 0 1 2 3

-10

-20
Frequency offset [MHz]

Figure 19: Typical selectivity at 250 kbps. IF frequency is 177.7 kHz.

MDMCFG2.DEM_DCFILT_OFF = 0

50

40

30
Selectivity [dB]

20

10

0
-3 -2 -1 0 1 2 3

-10

-20
Frequency offset [MHz]

Figure 20: Typical selectivity at 250 kbps. IF frequency is 457 kHz.

MDMCFG2.DEM_DCFILT_OFF = 1

35

30

25

20

15
Selectivity [dB]

10

0
-3 -2 -1 0 1 2 3
-5

-10

-15

-20
Frequency offset [MHz]

Figure 21: Typical selectivity at 500 kbps. IF frequency is 307.4 kHz.

MDMCFG2.DEM_DCFILT_OFF = 0

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 43 of 77

CC2500

26 Crystal Oscillator
A crystal in the frequency range 26-27 MHz The crystal oscillator is amplitude regulated.
must be connected between the XOSC_Q1 This means that a high current is used to start
and XOSC_Q2 pins. The oscillator is designed up the oscillations. When the amplitude builds
for parallel mode operation of the crystal. In up, the current is reduced to what is necessary
addition, loading capacitors (C81 and C101) to maintain approximately 0.4Vpp signal
for the crystal are required. The loading swing. This ensures a fast start-up, and keeps
capacitor values depend on the total load the drive level to a minimum. The ESR of the
capacitance, CL, specified for the crystal. The crystal should be within the specification in
total load capacitance seen between the order to ensure a reliable start-up (see Section
crystal terminals should equal CL for the 4.4 on page 10).
crystal to oscillate at the specified frequency.
The initial tolerance, temperature drift, aging
1 and load pulling should be carefully specified
CL = + C parasitic in order to meet the required frequency
1 1
+ accuracy in a certain application. By specifying
C81 C101 the total expected frequency accuracy in
SmartRF® Studio together with data rate and
The parasitic capacitance is constituted by pin frequency deviation, the software calculates
input capacitance and PCB stray capacitance. the total bandwidth and compares this to the
Total parasitic capacitance is typically 2.5 pF. chosen receiver channel filter bandwidth. The
The crystal oscillator circuit is shown in Figure software reports any contradictions, and a
22. Typical component values for different more accurate crystal is recommended if
values of CL are given in Table 32. required.

XOSC_Q1 XOSC_Q2

XTAL

C81 C101

Figure 22: Crystal oscillator circuit

Component CL= 10 pF CL=13 pF CL=16 pF

C81 15 pF 22 pF 27 pF
C101 15 pF 22 pF 27 pF

Table 32: Crystal oscillator component values

26.1 Reference Signal

The chip can alternatively be operated with a XOSC_Q1 input. The sine wave must be
reference signal from 26 to 27 MHz instead of connected to XOSC_Q1 using a serial
a crystal. This input clock can either be a full- capacitor. The XOSC_Q2 line must be left un-
swing digital signal (0 V to VDD) or a sine connected. C81 and C101 can be omitted
wave of maximum 1 V peak-peak amplitude. when using a reference signal.
The reference signal must be connected to the

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 44 of 77

CC2500

27 External RF Match

The balanced RF input and output of CC2500 Although CC2500 has a balanced RF
share two common pins and are designed for input/output, the chip can be connected to a
a simple, low-cost matching and balun network single-ended antenna with few external low
on the printed circuit board. The receive- and cost capacitors and inductors.
transmit switching at the CC2500 front-end is
The passive matching/filtering network
controlled by a dedicated on-chip function,
connected to CC2500 should have the following
eliminating the need for an external RX/TX-
differential impedance as seen from the RF-
switch.
port (RF_P and RF_N) towards the antenna:
A few passive external components combined
Zout = 80 + j74 Ω
with the internal RX/TX switch/termination
circuitry ensures match in both RX and TX
mode.

28 General Purpose / Test Output Control Pins

The three digital output pins GDO0, GDO1 and The default value for GDO0 is a 135-141 kHz
GDO2 are general control pins configured with clock output (XOSC frequency divided by 192).
IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG Since the XOSC is turned on at power-on-
and IOCFG2.GDO3_CFG respectively. Table reset, this can be used to clock the MCU in
33 shows the different signals that can be systems with only one crystal. When the MCU
monitored on the GDO pins. These signals can is up and running, it can change the clock
be used as an interrupt to the MCU. GDO1 is frequency by writing to IOCFG0.GDO0_CFG.
the same pin as the SO pin on the SPI An on-chip analog temperature sensor is
interface, thus the output programmed on this enabled by writing the value 128 (0x80h) to the
pin will only be valid when CSn is high. The IOCFG0.GDO0_CFG register. The voltage on
default value for GDO1 is 3-stated, which is the GDO0 pin is then proportional to
useful when the SPI interface is shared with temperature. See Section 4.7 on page 12 for
other devices. temperature sensor specifications.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 45 of 77

CC2500
GDO0_CFG[5:0]
GDO1_CFG[5:0] Description
GDO2_CFG[5:0]
0 (0x00) Associated to the RX FIFO: Asserts when RX FIFO is filled above RXFIFO_THR. De-asserts when RX FIFO is drained
below RXFIFO_THR.
1 (0x01) Associated to the RX FIFO: Asserts when RX FIFO is filled above RXFIFO_THR or the end of packet is reached. De-
asserts when RX FIFO is empty.
2 (0x02) Associated to the TX FIFO: Asserts when the TX FIFO is filled above TXFIFO_THR. De-asserts when the TX FIFO is
below TXFIFO_THR.
3 (0x03) Associated to the TX FIFO: Asserts when TX FIFO is full. De-asserts when the TX FIFO is drained below
TXFIFO_THR.
4 (0x04) Asserts when the RX FIFO has overflowed. De-asserts when the FIFO has been flushed.
5 (0x05) Asserts when the TX FIFO has underflowed. De-asserts when the FIFO is flushed.
6 (0x06) Asserts when sync word has been sent / received, and de-asserts at the end of the packet. In RX, the pin will de-assert
when the optional address check fails or the RX FIFO overflows. In TX the pin will de-assert if the TX FIFO underflows.
7 (0x07) Reserved
8 (0x08) Preamble Quality Reached. Asserts when the PQI is above the programmed PQT value.
9 (0x09) Clear channel assessment. High when RSSI level is below threshold (dependent on the current CCA_MODE setting)
10 (0x0A) Lock detector output
Serial Clock. Synchronous to the data in synchronous serial mode.
11 (0x0B)
Data is set up on the falling edge and is read on the rising edge of SERIAL_CLK when GDOx_INV=0.
12 (0x0C) Serial Synchronous Data Output (DO). Used for synchronous serial mode. The MCU must read DO on the rising edge
of SERIAL_CLK when GDOx_INV=0. Data is set up on the falling edge by CC2500.
13 (0x0D) Serial transparent Data Output. Used for asynchronous serial mode.
14 (0x0E) Carrier sense. High if RSSI level is above threshold.
15 (0x0F) Reserved
16 (0x10) Reserved – used for test.
17 (0x11) Reserved – used for test.
18 (0x12) Reserved – used for test.
19 (0x13) Reserved – used for test.
20 (0x14) Reserved – used for test.
21 (0x15) Reserved – used for test.
22 (0x16) RX_HARD_DATA[1]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
23 (0x17) RX_HARD_DATA[0]. Can be used together with RX_SYMBOL_TICK for alternative serial RX output.
24 (0x18) Reserved – used for test.
25 (0x19) Reserved – used for test.
26 (0x1A) Reserved – used for test.
27 (0x1B) PA_PD. PA is enabled when 0, in power-down when 1. Can be used to control external PA or RX/TX switch.
28 (0x1C) LNA_PD. LNA is enabled when 0, in power-down when 1. Can be used to control external LNA or RX/TX switch.
29 (0x1D) RX_SYMBOL_TICK. Can be used together with RX_HARD_DATA for alternative serial RX output.
30 (0x1E) Reserved – used for test.
31 (0x1F) Reserved – used for test.
32 (0x20) Reserved – used for test.
33 (0x21) Reserved – used for test.
34 (0x22) Reserved – used for test.
35 (0x23) Reserved – used for test.
36 (0x24) Reserved – used for test.
37 (0x25) Reserved – used for test.
38 (0x26) Reserved – used for test.
39 (0x27) Reserved – used for test.
40 (0x28) Reserved – used for test.
41 (0x29) CHIP_RDY
42 (0x2A) Reserved – used for test.
43 (0x2B) XOSC_STABLE
44 (0x2C) Reserved – used for test.
45 (0x2D) GDO0_Z_EN_N. When this output is 0, GDO0 is configured as input (for serial TX data).
46 (0x2E) High impedance (3-state)
47 (0x2F) HW to 0 (HW1 achieved with _INV signal)
48 (0x30) CLK_XOSC/1
49 (0x31) CLK_XOSC/1.5
50 (0x32) CLK_XOSC/2
51 (0x33) CLK_XOSC/3
52 (0x34) CLK_XOSC/4
53 (0x35) CLK_XOSC/6
54 (0x36) CLK_XOSC/8
55 (0x37) CLK_XOSC/12
56 (0x38) CLK_XOSC/16
57 (0x39) CLK_XOSC/24
58 (0x3A) CLK_XOSC/32
59 (0x3B) CLK_XOSC/48
60 (0x3C) CLK_XOSC/64
61 (0x3D) CLK_XOSC/96
62 (0x3E) CLK_XOSC/128
63 (0x3F) CLK_XOSC/192

Table 33: GDO signal selection

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 46 of 77

CC2500

29 Asynchronous and Synchronous Serial Operation

Several features and modes of operation have The CC2500 modulator samples the level of the
been included in the CC2500 to provide asynchronous input 8 times faster than the
backward compatibility with previous Chipcon programmed data rate. The timing requirement
products and other existing RF communication for the asynchronous stream is that the error in
systems. For new systems, it is recommended the bit period must be less than one eighth of
to use the built-in packet handling features, as the programmed data rate.
they can give more robust communication,
significantly offload the microcontroller and
simplify software development. 29.2 Synchronous serial operation
Setting PKTCTRL0.PKT_FORMAT to 1
29.1 Asynchronous operation enables synchronous serial operation mode. In
the synchronous serial operation mode, data is
For backward compatibility with systems transferred on a two wire serial interface. The
already using the asynchronous data transfer CC2500 provides a clock that is used to set up
from other Chipcon products, asynchronous new data on the data input line or sample data
transfer is also included in CC2500. When on the data output line. Data input (TX data) is
asynchronous transfer is enabled, several of the GDO0 pin. This pin will automatically be
the support mechanisms for the MCU that are configured as an input when TX is active. The
included in CC2500 will be disabled, such as data output pin can be any of the GDO pins;
packet handling hardware, buffering in the this is set by the IOCFG0.GDO0_CFG,
FIFO and so on. The asynchronous transfer IOCFG1.GDO1_CFG and IOCFG2.GDO2_CFG
mode does not allow the use of the data fields.
whitener, interleaver and FEC.
Preamble and sync word insertion/detection
Only 2-FSK, GFSK and OOK are supported for may or may not be active, dependent on the
asynchronous transfer. sync mode set by the MDMCFG2.SYNC_MODE.
Setting PKTCTRL0.PKT_FORMAT to 3 If preamble and sync word is disabled, all
enables asynchronous transparent (serial) other packet handler features and FEC should
mode. also be disabled. The MCU must then handle
preamble and sync word insertion and
In TX, the GDO0 pin is used for data input (TX detection in software. If preamble and sync
data). Data output can be GDO0, GDO1 or word insertion/detection is left on, all packet
GDO2. handling features and FEC can be used. The
CC2500 will insert and detect the preamble and
The MCU must control start and stop of
sync word and the MCU will only provide/get
transmit and receive with the STX, SRX and
the data payload. This is equivalent to the
SIDLE strobes. recommended FIFO operation mode.

30 System considerations and Guidelines

30.1 SRD Regulations GHz band, available from the Chipcon
website.
International regulations and national laws
regulate the use of radio receivers and Please note that compliance with regulations
transmitters. Short Range Devices (SRDs) for is dependent on complete system
license free operation are allowed to operate performance. It is the customer’s responsibility
in the 2.45 GHz bands worldwide. The most to ensure that the system complies with
important regulations are EN 300 440 and EN regulations.
300 328 (Europe), FCC CFR47 part 15.247
and 15.249 (USA), and ARIB STD-T66
(Japan). A summary of the most important 30.2 Frequency Hopping and Multi-
aspects of these regulations can be found in Channel Systems
Application Note AN032 SRD regulations for The 2.400 – 2.4835 GHz band is shared by
license-free transceiver operation in the 2.4 many systems both in industrial, office and

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 47 of 77

CC2500
home environments. It is therefore 30.3 Data Burst Transmissions
recommended to use frequency hopping
spread spectrum (FHSS) or a multi-channel The high maximum data rate of CC2500 opens
protocol because the frequency diversity up for burst transmissions. A low average data
makes the system more robust with respect to rate link (say 10 kbps), can be realized using a
interference from other systems operating in higher over-the-air data rate. Buffering the
the same frequency band. FHSS also combats data and transmitting in bursts at high data
multipath fading. rate (say 500 kbps) will reduce the time in
active mode, and hence also reduce the
CC2500 is highly suited for FHSS or multi- average current consumption significantly.
channel systems due to its agile frequency Reducing the time in active mode will reduce
synthesizer and effective communication the likelihood of collisions with other systems,
interface. Using the packet handling support e.g. WLAN.
and data buffering is also beneficial in such
systems as these features will significantly
offload the host controller. 30.4 Continuous Transmissions

Charge pump current, VCO current and VCO In data streaming applications the CC2500
capacitance array calibration data is required opens up for continuous transmissions at 500
for each frequency when implementing kbps effective data rate. As the modulation is
frequency hopping for CC2500. There are 3 done with an I/Q up-converter with LO I/Q-
ways of obtaining the calibration data from the signals coming from a closed loop PLL, there
is no limitation in the length of a transmission.
chip:
(Open loop modulation used in some
1) Frequency hopping with calibration for each transceivers often prevents this kind of
hop. The PLL calibration time is approximately continuous data streaming and reduces the
720 µs. effective data rate.)
2) Fast frequency hopping without calibration
for each hop can be done by calibrating each 30.5 Crystal Drift Compensation
frequency at startup and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values The CC2500 has a very fine frequency
in MCU memory. Between each frequency resolution (see Table 9). This feature can be
hop, the calibration process can then be used to compensate for frequency offset and
replaced by writing the FSCAL3, FSCAL2 and drift.
FSCAL1 register values corresponding to the The frequency offset between an ‘external’
next RF frequency. The PLL turn on time is transmitter and the receiver is measured in the
approximately 90 µs. CC2500 and can be read back from the
3) Run calibration on a single frequency at FREQEST status register as described in
startup. Next write 0hex to FSCAL3[5:4] to Section 14.1. The measured frequency offset
disable the charge pump calibration. After can be used to calibrate the frequency using
the ‘external’ transmitter as the reference. That
writing to FSCAL3[5:4] strobe SRX (or STX)
is, the received signal of the device will match
with MCSM0.FS_AUTOCAL = 1 for each new
the receiver’s channel filter better. In the same
frequency hop. That is, VCO current and VCO way the centre frequency of the transmitted
capacitance calibration is done but not charge signal will match the ‘external’ transmitter’s
pump current calibration. When charge pump signal.
current calibration is disabled the calibration
time is reduced from approximately 720 µs to
approximately 150 µs. 30.6 Spectrum Efficient Modulation
There is a trade off between blanking time and CC2500 also has the possibility to use
memory space needed for storing calibration Gaussian shaped FSK (GFSK). This
data in non-volatile memory. Solution 2) above spectrum-shaping feature improves adjacent
gives the shortest blanking interval, but channel power (ACP) and occupied
requires more memory space to store bandwidth. In ‘true’ FSK systems with abrupt
calibration values. Solution 3) gives frequency shifting, the spectrum is inherently
approximately 570 µs smaller blanking interval broad. By making the frequency shift ‘softer’,
than solution 1). the spectrum can be made significantly
narrower. Thus, higher data rates can be

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 48 of 77

CC2500
transmitted in the same bandwidth using 30.8 Battery Operated Systems
GFSK.
In low power applications, the SLEEP state
with the crystal oscillator core switched off
30.7 Low Cost Systems should be used when the CC2500 is not active.
It is possible to leave the crystal oscillator core
As the CC2500 provides 500 kbps multi- running in the SLEEP state if start-up time is
channel performance without any external
critical.
filters, a very low cost system can be made.
The WOR functionality should be used in low
A differential antenna will eliminate the need power applications.
for a balun, and the DC biasing can be
achieved in the antenna topology, see Figure
3. 30.9 Increasing Output Power
A HC-49 type SMD crystal is used in the In some applications it may be necessary to
CC2500EM reference design. Note that the extend the link range. Adding an external
crystal package strongly influences the price. power amplifier is the most effective way of
In a size constrained PCB design a smaller, doing this.
but more expensive, crystal may be used.
The power amplifier should be inserted
between the antenna and the balun, and two
T/R switches are needed to disconnect the PA
in RX mode. See Figure 23.

Antenna

Filter PA

Balun CC2500

T/R switch T/R switch

Figure 23. Block diagram of CC2500 usage with external power amplifier

31 Configuration Registers

The configuration of CC2500 is done by registers are for test purposes only, and need
programming 8-bit registers. The configuration not be written for normal operation of CC2500.
data based on selected system parameters
There are also 12 Status registers, which are
are most easily found by using the SmartRF®
listed in Table 36. These registers, which are
Studio software. Complete descriptions of the
read-only, contain information about the status
registers are given in the following tables. After
of CC2500.
chip reset, all the registers have default values
as shown in the tables. The two FIFOs are accessed through one 8-bit
register. Write operations write to the TX FIFO,
There are 14 Command Strobe Registers,
while read operations read from the RX FIFO.
listed in Table 34. Accessing these registers
will initiate the change of an internal state or During the address transfer and while writing
mode. There are 47 normal 8-bit Configuration to a register or the TX FIFO, a status byte is
Registers, listed in Table 35. Many of these

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 49 of 77

CC2500
returned. This status byte is described in Table read/write bits on the top. Note that the burst
17 on page 21. bit has different meaning for base addresses
above and below 0x2F.
Table 37 summarizes the SPI address space.
The address to use is given by adding the
base address to the left and the burst and

Address Strobe Description

Name
0x30 SRES Reset chip.
0x31 SFSTXON Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). If in RX (with CCA):
Go to a wait state where only the synthesizer is running (for quick RX / TX turnaround).
0x32 SXOFF Turn off crystal oscillator.
0x33 SCAL Calibrate frequency synthesizer and turn it off (enables quick start). SCAL can be strobed in IDLE
state without setting manual calibration mode (MCSM0.FS_AUTOCAL=0)

0x34 SRX Enable RX. Perform calibration first if coming from IDLE and MCSM0.FS_AUTOCAL=1.

0x35 STX In IDLE state: Enable TX. Perform calibration first if MCSM0.FS_AUTOCAL=1.
If in RX state and CCA is enabled: Only go to TX if channel is clear.
0x36 SIDLE Exit RX / TX, turn off frequency synthesizer and exit Wake-On-Radio mode if applicable.
0x38 SWOR Start automatic RX polling sequence (Wake-on-Radio) as described in Section 19.5.
0x39 SPWD Enter power down mode when CSn goes high.

0x3A SFRX Flush the RX FIFO buffer. Only issue in IDLE, TXFIFO_UNDERFLOW or RXFIFO_OVERFLOW
states.
0x3B SFTX Flush the TX FIFO buffer. Only issue in IDLE, TXFIFO_UNDERFLOW or RXFIFO_OVERFLOW
states.
0x3C SWORRST Reset real time clock.
0x3D SNOP No operation. May be used to pad strobe commands to two bytes for simpler software.

Table 34: Command Strobes

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 50 of 77

CC2500
Preserved in Details on
Address Register Description
SLEEP state page number
0x00 IOCFG2 GDO2 output pin configuration Yes 54

0x01 IOCFG1 GDO1 output pin configuration Yes 54

0x02 IOCFG0 GDO0 output pin configuration Yes 54

0x03 FIFOTHR RX FIFO and TX FIFO thresholds Yes 55
0x04 SYNC1 Sync word, high byte Yes 55
0x05 SYNC0 Sync word, low byte Yes 55
0x06 PKTLEN Packet length Yes 55
0x07 PKTCTRL1 Packet automation control Yes 56
0x08 PKTCTRL0 Packet automation control Yes 57
0x09 ADDR Device address Yes 57
0x0A CHANNR Channel number Yes 57
0x0B FSCTRL1 Frequency synthesizer control Yes 58
0x0C FSCTRL0 Frequency synthesizer control Yes 58
0x0D FREQ2 Frequency control word, high byte Yes 58
0x0E FREQ1 Frequency control word, middle byte Yes 58
0x0F FREQ0 Frequency control word, low byte Yes 58
0x10 MDMCFG4 Modem configuration Yes 59
0x11 MDMCFG3 Modem configuration Yes 59
0x12 MDMCFG2 Modem configuration Yes 60
0x13 MDMCFG1 Modem configuration Yes 61
0x14 MDMCFG0 Modem configuration Yes 61
0x15 DEVIATN Modem deviation setting Yes 62
0x16 MCSM2 Main Radio Control State Machine configuration Yes 62
0x17 MCSM1 Main Radio Control State Machine configuration Yes 63
0x18 MCSM0 Main Radio Control State Machine configuration Yes 64
0x19 FOCCFG Frequency Offset Compensation configuration Yes 64
0x1A BSCFG Bit Synchronization configuration Yes 64
0x1B AGCTRL2 AGC control Yes 65
0x1C AGCTRL1 AGC control Yes 66
0x1D AGCTRL0 AGC control Yes 66
0x1E WOREVT1 High byte Event 0 timeout Yes 66
0x1F WOREVT0 Low byte Event 0 timeout Yes 67
0x20 WORCTRL Wake On Radio control Yes 67
0x21 FREND1 Front end RX configuration Yes 67
0x22 FREND0 Front end TX configuration Yes 68
0x23 FSCAL3 Frequency synthesizer calibration Yes 68
0x24 FSCAL2 Frequency synthesizer calibration Yes 68
0x25 FSCAL1 Frequency synthesizer calibration Yes 68
0x26 FSCAL0 Frequency synthesizer calibration Yes 69
0x27 RCCTRL1 RC oscillator configuration Yes 69
0x28 RCCTRL0 RC oscillator configuration Yes 69
0x29 FSTEST Frequency synthesizer calibration control No 69
0x2A PTEST Production test No 69
0x2B AGCTEST AGC test No 69
0x2C TEST2 Various test settings No 70
0x2D TEST1 Various test settings No 70
0x2E TEST0 Various test settings No 70

Table 35: Configuration Registers Overview

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 51 of 77

CC2500

Address Register Description Details on page number

0x30 (0xF0) PARTNUM Part number for CC2500 70

0x31 (0xF1) VERSION Current version number 70

0x32 (0xF2) FREQEST Frequency Offset Estimate 70
0x33 (0xF3) LQI Demodulator estimate for Link Quality 71
0x34 (0xF4) RSSI Received signal strength indication 71
0x35 (0xF5) MARCSTATE Control state machine state 71
0x36 (0xF6) WORTIME1 High byte of WOR timer 72
0x37 (0xF7) WORTIME0 Low byte of WOR timer 72
0x38 (0xF8) PKTSTATUS Current GDOx status and packet status 72
0x39 (0xF9) VCO_VC_DAC Current setting from PLL calibration module 72
0x3A (0xFA) TXBYTES Underflow and number of bytes in the TX FIFO 72
0x3B (0xFB) RXBYTES Overflow and number of bytes in the RX FIFO 72

Table 36: Status Registers Overview

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 52 of 77

CC2500
Write Read
Single byte Burst Single byte Burst
+0x00 +0x40 +0x80 +0xC0
0x00 IOCFG2
0x01 IOCFG1
0x02 IOCFG0
0x03 FIFOTHR
0x04 SYNC1
0x05 SYNC0
0x06 PKTLEN
0x07 PKTCTRL1
0x08 PKTCTRL0
0x09 ADDR
0x0A CHANNR
0x0B FSCTRL1
0x0C FSCTRL0
0x0D FREQ2
0x0E FREQ1
0x0F FREQ0
0x10 MDMCFG4

R/W configuration registers, burst access possible

0x11 MDMCFG3
0x12 MDMCFG2
0x13 MDMCFG1
0x14 MDMCFG0
0x15 DEVIATN
0x16 MCSM2
0x17 MCSM1
0x18 MCSM0
0x19 FOCCFG
0x1A BSCFG
0x1B AGCCTRL2
0x1C AGCCTRL1
0x1D AGCCTRL0
0x1E WOREVT1
0x1F WOREVT0
0x20 WORCTRL
0x21 FREND1
0x22 FREND0
0x23 FSCAL3
0x24 FSCAL2
0x25 FSCAL1
0x26 FSCAL0
0x27 RCCTRL1
0x28 RCCTRL0
0x29 FSTEST
0x2A PTEST
0x2B AGCTEST
0x2C TEST2
0x2D TEST1
0x2E TEST0
0x2F
0x30 SRES SRES PARTNUM
0x31 SFSTXON SFSTXON VERSION
Command Strobes, Status registers (read only)

0x32 SXOFF SXOFF FREQEST

0x33 SCAL SCAL LQI
0x34 SRX SRX RSSI
0x35 STX STX MARCSTATE
0x36 SIDLE SIDLE WORTIME1
0x37 SAFC SAFC WORTIME0
0x38 SWOR SWOR PKTSTATUS
and multi byte registers

0x39 SPWD SPWD VCO_VC_DAC

0x3A SFRX SFRX TXBYTES
0x3B SFTX SFTX RXBYTES
0x3C SWORRST SWORRST
0x3D SNOP SNOP
0x3E PATABLE PATABLE PATABLE PATABLE
0x3F TX FIFO TX FIFO RX FIFO RX FIFO

Table 37: SPI Address Space

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 53 of 77

CC2500
31.1 Configuration Register Details – Registers with preserved values in sleep state

0x00: IOCFG2 – GDO2 output pin configuration

Bit Field Name Reset R/W Description

7 Reserved R0
6 GDO2_INV 0 R/W Invert output, i.e. select active low (1) / high (0)

5:0 GDO2_CFG[5:0] 41 (0x29) R/W Default is CHIP_RDY (see Table 33 on page 46).
Should be set to 3-state for lowest power down current.

0x01: IOCFG1 – GDO1 output pin configuration

Bit Field Name Reset R/W Description

7 GDO_DS 0 R/W Set high (1) or low (0) output drive strength on the
GDO pins.
6 GDO1_INV 0 R/W Invert output, i.e. select active low (1) / high (0)

5:0 GDO1_CFG[5:0] 46 (0x2E) R/W Default is 3-state (see Table 33 on page 46)

0x02: IOCFG0 – GDO0 output pin configuration

Bit Field Name Reset R/W Description

7 TEMP_SENSOR_ENABLE 0 R/W Enable analog temperature sensor. Write 0 in all other

register bits when using temperature sensor.
6 GDO0_INV 0 R/W Invert output, i.e. select active low (1) / high (0)

5:0 GDO0_CFG[5:0] 63 (0x3F) R/W Default is CLK_XOSC/192 (see Table 33 on page 46).
Should be set to 3-state for lowest power down current.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 54 of 77

CC2500
0x03: FIFOTHR – RX FIFO and TX FIFO thresholds
Bit Field Name Reset R/W Description

7:3 Reserved 0 R/W Write 0 for compatibility with possible future extensions
3:0 FIFO_THR[3:0] 7 (0111) R/W Set the threshold for the TX FIFO and RX FIFO. The threshold
is exceeded when the number of bytes in the FIFO is equal to
or higher than the threshold value.
Setting Bytes in TX FIFO Bytes in RX FIFO
0 (0000) 61 4
1 (0001) 57 8
2 (0010) 53 12
3 (0011) 49 16
4 (0100) 45 20
5 (0101) 41 24
6 (0110) 37 28
7 (0111) 33 32
8 (1000) 29 36
9 (1001) 25 40
10 (1010) 21 44
11 (1011) 17 48
12 (1100) 13 52
13 (1101) 9 56
14 (1110) 5 60
15 (1111) 1 64

0x04: SYNC1 – Sync word, high byte

Bit Field Name Reset R/W Description

7:0 SYNC[15:8] 211 (0xD3) R/W 8 MSB of 16-bit sync word

0x05: SYNC0 – Sync word, low byte

Bit Field Name Reset R/W Description

7:0 SYNC[7:0] 145 (0x91) R/W 8 LSB of 16-bit sync word

0x06: PKTLEN – Packet length

Bit Field Name Reset R/W Description

7:0 PACKET_LENGTH 255 (0xFF) R/W Indicates the packet length when fixed length packets
are enabled. If variable length packets are used, this
value indicates the maximum length packets allowed.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 55 of 77

CC2500
0x07: PKTCTRL1 – Packet automation control
Bit Field Name Reset R/W Description

7:5 PQT[2:0] 0 (000) R/W Preamble quality estimator threshold. The preamble quality
estimator increases an internal counter by one each time a bit is
received that is different from the previous bit, and decreases the
counter by 4 each time a bit is received that is the same as the
last bit. The counter saturates at 0 and 31.
A threshold of 4·PQT for this counter is used to gate sync word
detection. When PQT=0 a sync word is always accepted.
4 Reserved 0 R/W
3 CRC_AUTOFLUSH 0 R/W Enable automatic flush of RX FIFO when CRC in not OK. This
requires that only one packet is in the RXIFIFO and that packet
length is limited to the RX FIFO size.
2 APPEND_STATUS 1 R/W When enabled, two status bytes will be appended to the payload
of the packet. The status bytes contain RSSI and LQI values, as
well as the CRC OK flag.
1:0 ADR_CHK[1:0] 0 (00) R/W Controls address check configuration of received packages.
Setting Address check configuration
0 (00) No address check
1 (01) Address check, no broadcast
2 (10) Address check, 0 (0x00) broadcast
3 (11) Address check, 0 (0x00) and 255 (0xFF) broadcast

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 56 of 77

CC2500
0x08: PKTCTRL0 – Packet automation control
Bit Field Name Reset R/W Description

7 Reserved R0
6 WHITE_DATA 1 R/W Turn data whitening on / off
0: Whitening off
1: Whitening on
5:4 PKT_FORMAT[1:0] 0 (00) R/W Format of RX and TX data
Setting Packet format
0 (00) Normal mode, use FIFOs for RX and TX
Serial Synchronous mode, used for backwards
1 (01)
compatibility. Data in on GDO0

Random TX mode; sends random data using PN9

2 (10) generator. Used for test.
Works as normal mode, setting 0 (00), in RX.

Asynchronous transparent mode. Data in on GDO0

3 (11)
and Data out on either of the GDO pins

3 CC2400_EN 0 R/W Enable CC2400 support. Use same CRC implementation as

CC2400.
2 CRC_EN 1 R/W 1: CRC calculation in TX and CRC check in RX enabled
0: CRC disabled for TX and RX
1:0 LENGTH_CONFIG[1:0] 1 (01) R/W Configure the packet length
Setting Packet length configuration
0 (00) Fixed length packets, length configured in
PKTLEN register
1 (01) Variable length packets, packet length configured
by the first byte after sync word
2 (10) Enable infinite length packets
3 (11) Reserved

0x09: ADDR – Device address

Bit Field Name Reset R/W Description

7:0 DEVICE_ADDR[7:0] 0 (0x00) R/W Address used for packet filtration. Optional broadcast
addresses are 0 (0x00) and 255 (0xFF).

0x0A: CHANNR – Channel number

Bit Field Name Reset R/W Description

7:0 CHAN[7:0] 0 (0x00) R/W The 8-bit unsigned channel number, which is multiplied by the
channel spacing setting and added to the base frequency.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 57 of 77

CC2500
0x0B: FSCTRL1 – Frequency synthesizer control
Bit Field Name Reset R/W Description

7:5 Reserved R0
4:0 FREQ_IF[4:0] 10 (0x0F) R/W The desired IF frequency to employ in RX. Subtracted from FS
base frequency in RX and controls the digital complex mixer in
the demodulator.

f XOSC
f IF = ⋅ FREQ _ IF
210
The default value gives an IF frequency of 254 kHz, assuming
a 26.0 MHz crystal.

0x0C: FSCTRL0 – Frequency synthesizer control

Bit Field Name Reset R/W Description

7:0 FREQOFF[7:0] 0 (0x00) R/W Frequency offset added to the base frequency before being
used by the FS. (2-complement).
14
Resolution is FXTAL/2 (1.59 - 1.65 kHz); range is ±202 kHz to
±210 kHz, dependent of XTAL frequency.

0x0D: FREQ2 – Frequency control word, high byte

Bit Field Name Reset R/W Description

7:6 FREQ[23:22] 1 (01) R FREQ[23:22] is always binary 01 (the FREQ2 register is in the range 85 to
95 with 26-27 MHz crystal)
5:0 FREQ[21:16] 30 R/W FREQ[23:0] is the base frequency for the frequency synthesiser in
16
(0x1E) increments of FXOSC/2 .

f XOSC
f carrier = ⋅ FREQ [23 : 0]
216
The default frequency word gives a base frequency of 2464 MHz,
assuming a 26.0 MHz crystal. With the default channel spacing settings,
the following FREQ2 values and channel numbers can be used:
FREQ2 Base frequency Frequency range (CHAN numbers)
91 (0x5B) 2386 MHz 2400.2-2437 MHz (71-255)
92 (0x5C) 2412 MHz 2412-2463 MHz (0-255)
93 (0x5D) 2438 MHz 2431-2483.4 MHz (0-227)
94 (0x5E) 2464 MHz 2464-2483.4 MHz (0-97)

0x0E: FREQ1 – Frequency control word, middle byte

Bit Field Name Reset R/W Description

7:0 FREQ[15:8] 196 (0xC4) R/W Ref. FREQ2 register

0x0F: FREQ0 – Frequency control word, low byte

Bit Field Name Reset R/W Description

7:0 FREQ[7:0] 236 (0xEC) R/W Ref. FREQ2 register

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 58 of 77

CC2500
0x10: MDMCFG4 – Modem configuration
Bit Field Name Reset R/W Description

7:6 CHANBW_E[1:0] 2 (10) R/W

5:4 CHANBW_M[1:0] 0 (00) R/W Sets the decimation ratio for the delta-sigma ADC input stream
and thus the channel bandwidth.

f XOSC
BWchannel =
8 ⋅ (4 + CHANBW _ M )·2CHANBW _ E
The default values give 203 kHz channel filter bandwidth,
assuming a 26.0 MHz crystal.
3:0 DRATE_E[3:0] 12 (1100) R/W The exponent of the user specified symbol rate

0x11: MDMCFG3 – Modem configuration

Bit Field Name Reset R/W Description

7:0 DRATE_M[7:0] 34 (0x22) R/W The mantissa of the user specified symbol rate. The symbol
rate is configured using an unsigned, floating-point number
th
with 9-bit mantissa and 4-bit exponent. The 9 bit is a hidden
‘1’. The resulting data rate is:

RDATA =
(256 + DRATE _ M ) ⋅ 2 DRATE _ E ⋅ f
XOSC
2 28
The default values give a data rate of 115.051 kbps (closest
setting to 115.2 kbps), assuming a 26.0 MHz crystal.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 59 of 77

CC2500
0x12: MDMCFG2 – Modem configuration
Bit Field Name Reset R/W Description

7 DEM_DCFILT_OFF 0 R/W Disable digital DC blocking filter before demodulator.

0 = Enable (better sensitivity for data rates ≤ 250 kbps)
1 = Disable (reduced current)
The recommended IF frequency changes when the DC
blocking is disabled.
6:4 MOD_FORMAT[2:0] 0 (000) R/W The modulation format of the radio signal
Setting Modulation format
0 (000) 2-FSK
1 (001) GFSK
2 (010) -
3 (011) OOK
4 (100) -
5 (101) -
6 (110) -
7 (111) MSK

3 MANCHESTER_EN 0 R/W Enables Manchester encoding/decoding.

0 = Disable
1 = Enable
2:0 SYNC_MODE[2:0] 2 (010) R/W Combined sync-word qualifier mode.
The values 0 (000) and 4 (100) disables sync word
transmission in TX and sync word detection in RX.
The values 1 (001), 2 (001), 5 (101) and 6 (110)
enables 16-bit sync word transmission in TX and 16-
bits sync word detection in RX. Only 15 of 16 bits need
to match in RX when using setting 1 (001) or 5 (101).
The values 3 (011) and 7 (111) enables repeated sync
word transmission in RX and 32-bits sync word
detection in RX (only 30 of 32 bits need to match).
Setting Sync-word qualifier mode
0 (000) No preamble/sync
1 (001) 15/16 sync word bits detected
2 (010) 16/16 sync word bits detected
3 (011) 30/32 sync word bits detected
4 (100) No preamble/sync, carrier-sense
above threshold
5 (101) 15/16 + carrier-sense above threshold
6 (110) 16/16 + carrier-sense above threshold
7 (111) 30/32 + carrier-sense above threshold

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 60 of 77

CC2500
0x13: MDMCFG1 – Modem configuration
Bit Field Name Reset R/W Description

7 FEC_EN 0 R/W Enable Forward Error Correction (FEC) with interleaving for
packet payload
0 = Disable
1 = Enable
6:4 NUM_PREAMBLE[2:0] 2 (010) R/W Sets the minimum number of preamble bytes to be transmitted
Setting Number of preamble bytes
0 (000) 2
1 (001) 3
2 (010) 4
3 (011) 6
4 (100) 8
5 (101) 12
6 (110) 16
7 (111) 24

3:2 Reserved R0
1:0 CHANSPC_E[1:0] 2 (10) R/W 2 bit exponent of channel spacing

0x14: MDMCFG0 – Modem configuration

Bit Field Name Reset R/W Description

7:0 CHANSPC_M[7:0] 248 (0xF8) R/W 8-bit mantissa of channel spacing (initial 1 assumed). The
channel spacing is multiplied by the channel number CHAN and
added to the base frequency. It is unsigned and has the format:
f XOSC
∆f CHANNEL = ⋅ (256 + CHANSPC _ M ) ⋅ 2 CHANSPC _ E ⋅ CHAN
218
The default values give 199.951 kHz channel spacing (the closest
setting to 200 kHz), assuming 26.0 MHz crystal frequency.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 61 of 77

CC2500

0x15: DEVIATN – Modem deviation setting

Bit Field Name Reset R/W Description

7 Reserved R0
6:4 DEVIATION_E[2:0] 4 (100) R/W Deviation exponent
3 Reserved R0
2:0 DEVIATION_M[2:0] 7 (111) R/W When MSK modulation is enabled:
Sets fraction of symbol period used for phase change.
When FSK modulation is enabled:
Deviation mantissa, interpreted as a 4-bit value with MSB implicit
1. The resulting FSK deviation is given by:

f xosc
f dev = 17
⋅ (8 + DEVIATION _ M ) ⋅ 2 DEVIATION _ E
2
The default values give ±47.607 kHz deviation, assuming 26.0
MHz crystal frequency.

0x16: MCSM2 – Main Radio Control State Machine configuration

Bit Field Name Reset R/W Description

7:5 Reserved R0 Reserved

4 RX_TIME_RSSI 0 R/W Direct RX termination based on RSSI measurement (carrier
sense). For OOK modulation, RX times out if there is no
carrier sense in the first 8 symbol periods.
3 RX_TIME_QUAL 0 R/W When the RX_TIME timer expires the chip stays in RX mode if
sync word is found when RX_TIME_QUAL=0, or either sync
word is found or PQT is set when RX_TIME_QUAL=1.
2:0 RX_TIME[2:0] 7 (111) R/W Timeout for sync word search in RX. The timeout is relative to
the programmed EVENT0 timeout, which means that the duty
cycle can be set in wake-on-radio (WOR) mode. The RX
timeout is scaled by 1 bit less than the EVENT0 timeout with
respect to the WORCTRL.WOR_RES setting, as very long
timeouts probably also will use very low RX duty cycles.
Setting RX timeout Duty cycle, WOR
(3+WOR_RES) WOR_RES
0 (000) TEVENT0 / 2 12.5% / 2
(4+WOR_RES) WOR_RES
1 (001) TEVENT0 / 2 6.25% / 2
(5+WOR_RES) WOR_RES
2 (010) TEVENT0 / 2 3.125% / 2
(6+WOR_RES) WOR_RES
3 (011) TEVENT0 / 2 1.563% / 2
(7+WOR_RES) WOR_RES
4 (100) TEVENT0 / 2 0.781% / 2
(8+WOR_RES) WOR_RES
5 (101) TEVENT0 / 2 0.391% / 2
(9+WOR_RES) WOR_RES
6 (110) TEVENT0 / 2 0.195% / 2
7 (111) Until end of packet N/A (no timeout)
Note that the RC oscillator must be enabled in order to use
setting 0-6, because the timeout counts RC oscillator periods.
WOR mode does not need to be enabled.
The timeout counter resolution is limited: With RX_TIME=0,
the timeout count is given by the 13 MSBs of EVENT0,
decreasing to the 7 MSBs of EVENT0 with RX_TIME=6.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 62 of 77

CC2500
0x17: MCSM1 – Main Radio Control State Machine configuration
Bit Field Name Reset R/W Description

7:6 Reserved R0
5:4 CCA_MODE[1:0] 3 (11) R/W Selects CCA_MODE; Reflected in CCA signal
Setting Clear channel indication
0 (00) Always
1 (01) If RSSI below threshold
2 (10) Unless currently receiving a packet
3 (11) If RSSI below threshold unless currently
receiving a packet

3:2 RXOFF_MODE[1:0] 0 (00) R/W Select what should happen when a packet has been received
Setting Next state after finishing packet reception
0 (00) IDLE
1 (01) FSTXON
2 (10) TX
3 (11) Stay in RX
It is not possible to set RXOFF_MODE to be TX or FSTXON
and at the same time use CCA.
1:0 TXOFF_MODE[1:0] 0 (00) R/W Select what should happen when a packet has been sent (TX)
Setting Next state after finishing packet transmission
0 (00) IDLE
1 (01) FSTXON
2 (10) Stay in TX (start sending preamble)
3 (11) RX

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 63 of 77

CC2500
0x18: MCSM0 – Main Radio Control State Machine configuration
Bit Field Name Reset R/W Description

7:6 Reserved R0
5:4 FS_AUTOCAL[1:0] 0 (00) R/W Automatically calibrate when going to RX or TX, or back to IDLE
Setting When to perform automatic calibration

0 (00) Never (manually calibrate using SCAL strobe)

1 (01) When going from IDLE to RX or TX (or FSTXON)

2 (10) When going from RX or TX back to IDLE
th
3 (11) Every 4 time when going from RX or TX to IDLE
In some automatic wake-on-radio (WOR) applications, using
setting 3 (11) can significantly reduce current consumption.
3:2 PO_TIMEOUT 1 (01) R/W Programs the number of times the six-bit ripple counter must
expire before CHP_RDY_N goes low. Values other than 0 (00)
are most useful when the XOSC is left on during power-down.
Setting Expire count Timeout after XOSC start
0 (00) 1 Approx. 2.3 – 2.7 µs
1 (01) 16 Approx. 37 – 43 µs
2 (10) 64 Approx. 146 – 171 µs
3 (11) 256 Approx. 585 – 683 µs
Exact timeout depends on crystal frequency.
1 PIN_CTRL_EN 0 R/W Enables the pin radio control option
0 XOSC_FORCE_ON 0 R/W Force the XOSC to stay on in the SLEEP state.

0x19: FOCCFG – Frequency Offset Compensation configuration

Bit Field Name Reset R/W Description

7:6 Reserved R0
5:0 FOCCFG[5:0] 54 R/W Frequency offset compensation configuration. The value to use
(0x36) in this register is given by the SmartRF® Studio software.

0x1A: BSCFG – Bit Synchronization configuration

Bit Field Name Reset R/W Description

7:0 BSCFG[7:0] 108 R/W Bit Synchronization configuration. The value to use in this register is
(0x6C) given by the SmartRF® Studio software.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 64 of 77

CC2500
0x1B: AGCCTRL2 – AGC control
Bit Field Name Reset R/W Description

7:6 MAX_DVGA_GAIN[1:0] 0 (00) R/W Reduces the maximum allowable DVGA gain.
Setting Allowable DVGA settings
0 (00) All gain settings can be used
1 (01) The highest gain setting can not be used
2 (10) The 2 highest gain settings can not be used
3 (11) The 3 highest gain settings can not be used

5:3 MAX_LNA_GAIN[2:0] 0 (000) R/W Sets the maximum allowable LNA + LNA 2 gain relative to the
maximum possible gain.
Setting Maximum allowable LNA + LNA 2 gain
0 (000) Maximum possible LNA + LNA 2 gain
1 (001) Approx. 2.6 dB below maximum possible gain
2 (010) Approx. 6.1 dB below maximum possible gain
3 (011) Approx. 7.4 dB below maximum possible gain
4 (100) Approx. 9.2 dB below maximum possible gain
5 (101) Approx. 11.5 dB below maximum possible gain
6 (110) Approx. 14.6 dB below maximum possible gain
7 (111) Approx. 17.1 dB below maximum possible gain

2:0 MAGN_TARGET[2:0] 3 (011) R/W These bits set the target value for the averaged amplitude from
the digital channel filter (1 LSB = 0 dB).
Setting Target amplitude from channel filter
0 (000) 24 dB
1 (001) 27 dB
2 (010) 30 dB
3 (011) 33 dB
4 (100) 36 dB
5 (101) 38 dB
6 (110) 40 dB
7 (111) 42 dB

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 65 of 77

CC2500
0x1C: AGCCTRL1 – AGC control
Bit Field Name Reset R/W Description

7 Reserved R0
6 AGC_LNA_PRIORITY 1 R/W Selects between two different strategies for LNA and LNA 2
gain adjustment. When 1, the LNA gain is decreased first.
When 0, the LNA 2 gain is decreased to minimum before
decreasing LNA gain.
5:4 CARRIER_SENSE_REL_THR[1:0] 0 (00) R/W Sets the relative change threshold for asserting carrier
sense
Setting Carrier sense relative threshold
0 (00) Relative carrier sense threshold disabled
1 (01) 6 dB increase in RSSI value
2 (10) 10 dB increase in RSSI value
3 (11) 14 dB increase in RSSI value

3:0 CARRIER_SENSE_ABS_THR[3:0] 0 R/W Sets the absolute RSSI threshold for asserting carrier
(0000) sense. The 2-complement signed threshold is programmed
in steps of 1 dB and is relative to the MAGN_TARGET
setting.
Setting Carrier sense absolute threshold
(Equal to channel filter amplitude when AGC
has not decreased gain)
-8 (1000) Absolute carrier sense threshold disabled
-7 (1001) 7 dB below MAGN_TARGET setting
… …
-1 (1111) 1 dB below MAGN_TARGET setting
0 (0000) At MAGN_TARGET setting
1 (0001) 1 dB above MAGN_TARGET setting
… …
7 (0111) 7 dB above MAGN_TARGET setting

0x1D: AGCCTRL0 – AGC control

Bit Field Name Reset R/W Description

7:0 AGCCTRL0[7:0] 145 R/W AGC control register. The value to use in this register is given
(0x91) by the SmartRF® Studio software.

0x1E: WOREVT1 – High byte Event0 timeout

Bit Field Name Reset R/W Description

7:0 EVENT0[15:8] 135 (0x87) R/W High byte of Event 0 timeout register

750
t Event 0 = ⋅ EVENT 0 ⋅ 2 5⋅WOR _ RES
f XOSC

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 66 of 77

CC2500

0x1F: WOREVT0 – Low byte Event0 timeout

Bit Field Name Reset R/W Description

7:0 EVENT0[7:0] 107 (0x6B) R/W Low byte of Event 0 timeout register.
The default Event 0 value gives 1.0s timeout, assuming a
26.0 MHz crystal.

0x20: WORCTRL – Wake On Radio control

Bit Field Name Reset R/W Description

7 RC_PD 1 R/W Power down signal to RC oscillator. When written to 0, automatic

initial calibration will be performed
6:4 EVENT1[2:0] 7 (111) R/W Timeout setting from register block. Decoded to Event 1 timeout.
RC oscillator clock frequency equals FXOSC/750, which is 34.7-36
kHz, depending on crystal frequency. The table below lists the
number of clock periods after Event 0 before Event 1 times out.
Setting WOR_AUTOSYNC=0 WOR_AUTOSYNC=1
0 (000) 4 (0.111 – 0.115 ms) 16 (0.44 – 0.46 ms)
1 (001) 6 (0.167 – 0.173 ms) 24 (0.67 – 0.69 ms)
2 (010) 8 (0.222 – 0.230 ms) 32 (0.89 – 0.92 ms)
3 (011) 12 (0.333 – 0.346 ms) 48 (1.33 – 1.38 ms)
4 (100) 16 (0.444 – 0.462 ms) 64 (1.78 – 1.85 ms)
5 (101) 24 (0.667 – 0.692 ms) 96 (2.67 – 2.77 ms)
6 (110) 32 (0.889 – 0.923 ms) 128 (3.56 – 3.69 ms)
7 (111) 48 (1.333 – 1.385 ms) 192 (5.33 – 5.54 ms)

3 RC_CAL 1 R/W Enables (1) or disables (0) the RC oscillator calibration.

Included for debug/test purposes only.
2 Reserved R0
1:0 WOR_RES 0 (00) R/W Controls the Event 0 resolution and maximum timeout of the WOR
module:
Setting Resolution (1 LSB) Max timeout
0 (00) 1 period (28 – 29 µs) 1.8 – 1.9 seconds
5
1 (01) 2 periods (0.89 – 0.92 ms) 58 – 61 seconds
10
2 (10) 2 periods (28 – 30 ms) 31 – 32 minutes
15
3 (11) 2 periods (0.91 – 0.94 s) 16.5 – 17.2 hours
Adjusting the resolution does not affect the resolution of the WOR
time readout registers WORTIME1/WORTIME0.

0x21: FREND1 – Front end RX configuration

Bit Field Name Reset R/W Description

7:0 FREND1[7:0] 166 R/W Front end RX configuration. The value to use in this register
(0xA6) is given by the SmartRF® Studio software.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 67 of 77

CC2500
0x22: FREND0 – Front end TX configuration
Bit Field Name Reset R/W Description

7:6 Reserved R0
5:4 LODIV_BUF_CURRENT_TX[1:0] 1 (01) R/W Adjusts current TX LO buffer (input to PA). The value to
use in this field is given by the SmartRF® Studio software.
3 Reserved R0
2:0 PA_POWER[2:0] 0 (000) R/W Selects PA power setting. This value is an index to the
PATABLE, which can be programmed with up to 8 different
PA settings. The PATABLE settings from index ‘0’ to the
PA_POWER value are used for power ramp-up/ramp-down
at the start/end of transmission in all TX modulation
formats.

0x23: FSCAL3 – Frequency synthesizer calibration

Bit Field Name Reset R/W Description

7:6 FSCAL3[7:6] 2 (10) R/W Frequency synthesizer calibration configuration. The value to write in
this register before calibration is given by the SmartRF® Studio
software.
5:4 CHP_CURR_CAL_EN[1:0] 2 (10) R/W Disable charge pump calibration stage when 0
3:0 FSCAL3[3:0] 9 R/W Frequency synthesizer calibration result register.
(1001) Fast frequency hopping without calibration for each hop can be done
by calibrating upfront for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values. Between each
frequency hop, calibration can be replaced by writing the FSCAL3,
FSCAL2 and FSCAL1 register values corresponding to the next RF
frequency.

0x24: FSCAL2 – Frequency synthesizer calibration

Bit Field Name Reset R/W Description

7:6 Reserved R0
5:0 FSCAL2[5:0] 10 R/W Frequency synthesizer calibration result register.
(0x0A) Fast frequency hopping without calibration for each hop can be done
by calibrating upfront for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values. Between each
frequency hop, calibration can be replaced by writing the FSCAL3,
FSCAL2 and FSCAL1 register values corresponding to the next RF
frequency.

0x25: FSCAL1 – Frequency synthesizer calibration

Bit Field Name Reset R/W Description

7:6 Reserved R0
5:0 FSCAL1[5:0] 32 R/W Frequency synthesizer calibration result register.
(0x20) Fast frequency hopping without calibration for each hop can be done
by calibrating upfront for each frequency and saving the resulting
FSCAL3, FSCAL2 and FSCAL1 register values. Between each
frequency hop, calibration can be replaced by writing the FSCAL3,
FSCAL2 and FSCAL1 register values corresponding to the next RF
frequency.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 68 of 77

CC2500
0x26: FSCAL0 – Frequency synthesizer calibration
Bit Field Name Reset R/W Description

7 Reserved R0
4:0 FSCAL0[6:0] 13 (0x0D) R/W Frequency synthesizer calibration control. The value to use in
this register is given by the SmartRF® Studio software.

0x27: RCCTRL1 – RC oscillator configuration

Bit Field Name Reset R/W Description

7 Reserved 0 R0
6:0 RCCTRL1[6:0] 65 R/W RC oscillator configuration. Do not write to this register.
(0x41)

0x28: RCCTRL0 – RC oscillator configuration

Bit Field Name Reset R/W Description

7 Reserved 0 R0
6:0 RCCTRL0[6:0] 0 R/W RC oscillator configuration. Do not write to this register.
(0x00)

31.2 Configuration Register Details – Registers that lose programming in sleep state

0x29: FSTEST – Frequency synthesizer calibration control

Bit Field Name Reset R/W Description

7:0 FSTEST[7:0] 87 R/W For test only. Do not write to this register.
(0x59)

0x2A: PTEST – Production test

Bit Field Name Reset R/W Description

7 PTEST[7:0] 127 R/W Writing 0xBF to this register makes the on-chip temperature sensor
(0x7F) available in the IDLE state. The default 0x7F value should then be
written back before leaving the IDLE state.
Other use of this register is for test only.

0x2B: AGCTEST – AGC test

Bit Field Name Reset R/W Description

7:0 AGCTEST[7:0] 63 R/W For test only. Do not write to this register.
(0x3F)

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 69 of 77

CC2500

0x2C: TEST2 – Various test settings

Bit Field Name Reset R/W Description

7:0 TEST2[7:0] 152 (0x88) R/W The value to use in this register is given by the SmartRF® Studio
software.

0x2D: TEST1 – Various test settings

Bit Field Name Reset R/W Description

7:0 TEST1[7:0] 49 (0x31) R/W The value to use in this register is given by the SmartRF® Studio
software.

0x2E: TEST0 – Various test settings

Bit Field Name Reset R/W Description

7:0 TEST0[7:0] 11 (0x0B) R/W The value to use in this register is given by the SmartRF® Studio
software.

31.3 Status register details

0x30 (0xF0): PARTNUM – Chip ID

Bit Field Name Reset R/W Description

7:0 PARTNUM[7:0] 128 (0x80) R Chip part number

0x31 (0xF1): VERSION – Chip ID

Bit Field Name Reset R/W Description

7:0 VERSION[7:0] 3 (0x03) R Chip version number.

0x32 (0xF2): FREQEST – Frequency Offset Estimate from demodulator

Bit Field Name Reset R/W Description

7:0 FREQOFF_EST R The estimated frequency offset (two’s complement) of the

14
carrier. Resolution is FXTAL/2 (1.59 - 1.65 kHz); range is ±202
kHz to ±210 kHz, dependent of XTAL frequency.
Frequency offset compensation is only supported for FSK and
MSK modulation. This register will read 0 when using OOK
modulation.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 70 of 77

CC2500

0x33 (0xF3): LQI – Demodulator estimate for Link Quality

Bit Field Name Reset R/W Description

7 Reserved
6:0 LQI_EST[6:0] R The Link Quality Indicator estimates how easily a received signal
can be demodulated. Calculated over the 64 symbols following
the sync word (first 8 packet bytes for 2-ary modulation).

0x34 (0xF4): RSSI – Received signal strength indication

Bit Field Name Reset R/W Description

7:0 RSSI R Received signal strength indicator

0x35 (0xF5): MARCSTATE – Main Radio Control State Machine state

Bit Field Name Reset R/W Description

7:5 Reserved R0
4:0 MARC_STATE[4:0] R Main Radio Control FSM State
Value State name State (Figure 11, page 34)
0 (0x00) SLEEP SLEEP
1 (0x01) IDLE IDLE
2 (0x02) XOFF XOFF
3 (0x03) VCOON_MC MANCAL
4 (0x04) REGON_MC MANCAL
5 (0x05) MANCAL MANCAL
6 (0x06) VCOON FS_WAKEUP
7 (0x07) REGON FS_WAKEUP
8 (0x08) STARTCAL CALIBRATE
9 (0x09) BWBOOST SETTLING
10 (0x0A) FS_LOCK SETTLING
11 (0x0B) IFADCON SETTLING
12 (0x0C) ENDCAL CALIBRATE
13 (0x0D) RX RX
14 (0x0E) RX_END RX
15 (0x0F) RX_RST RX
16 (0x10) TXRX_SWITCH TXRX_SETTLING
17 (0x11) RX_OVERFLOW RX_OVERFLOW
18 (0x12) FSTXON FSTXON
19 (0x13) TX TX
20 (0x14) TX_END TX
21 (0x15) RXTX_SWITCH RXTX_SETTLING
22 (0x16) TX_UNDERFLOW TX_UNDERFLOW
Note: it is not possible to read back the SLEEP or XOFF state
numbers because setting CSn low will make the chip enter the
IDLE mode from the SLEEP or XOFF states.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 71 of 77

CC2500
0x36 (0xF6): WORTIME1 – High byte of WOR time
Bit Field Name Reset R/W Description

7:0 TIME[15:8] R High byte of timer value in WOR module

0x37 (0xF7): WORTIME0 – Low byte of WOR time

Bit Field Name Reset R/W Description

7:0 TIME[7:0] R Low byte of timer value in WOR module

0x38 (0xF8): PKTSTATUS – Current GDOx status and packet status

Bit Field Name Reset R/W Description

7 Reserved
6 CS R Carrier sense
5 PQT_REACHED R Preamble Quality reached
4 CCA R Clear channel assessment
3 SFD R Sync word found
2 GDO2 R Current GDO2 value. Note: the reading gives the non-inverted
value irrespective what IOCFG2.GDO2_INV is programmed
to.
1 Reserved
0 GDO0 R Current GDO0 value. Note: the reading gives the non-inverted
value irrespective what IOCFG0.GDO0_INV is programmed
to.

0x39 (0xF9): VCO_VC_DAC – Current setting from PLL calibration module

Bit Field Name Reset R/W Description

7:0 VCO_VC_DAC[7:0] R Status register for test only.

0x3A (0xFA): TXBYTES – Underflow and number of bytes

Bit Field Name Reset R/W Description

7 TXFIFO_UNDERFLOW R
6:0 NUM_TXBYTES R Number of bytes in TX FIFO

0x3B (0xFB): RXBYTES – Overflow and number of bytes

Bit Field Name Reset R/W Description

7 RXFIFO_OVERFLOW R
6:0 NUM_RXBYTES R Number of bytes in RX FIFO

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 72 of 77

CC2500

32 Package Description (QLP 20)

All dimensions are in millimetres, angles in degrees. NOTE: The CC2500 is available in RoHS
lead-free package only.

Figure 24: Package dimensions drawing

Package type A A1 A2 D D1 D2 E E1 E2 L T b e
Min 0.75 0.005 0.55 3.90 3.65 3.90 3.65 0.45 0.190 0.18

QLP 20 (4x4) Typ. 0.85 0.025 0.65 4.00 3.75 2.40 4.00 3.75 2.40 0.55 0.23 0.50
Max 0.95 0.045 0.75 4.10 3.85 4.10 3.85 0.65 0.245 0.30

Table 38: Package dimensions

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 73 of 77

CC2500
32.1 Recommended PCB layout for package (QLP 20)

Figure 25: Recommended PCB layout for QLP 20 package

Note: The figure is an illustration only and not to scale. There are five 14 mil diameter via holes
distributed symmetrically in the ground pad under the package. See also the CC2500 EM
reference design.

32.2 Package thermal properties

Thermal resistance
Air velocity [m/s] 0
Rth,j-a [K/W] 40.4

Table 39: Thermal properties of QLP 20 package

32.3 Soldering information

The recommendations for lead-free reflow in IPC/JEDEC J-STD-020C should be followed.

32.4 Tray specification

CC2500 can be delivered in standard QLP 4x4mm shipping trays.
Tray Specification
Package Tray Width Tray Height Tray Length Units per Tray
QLP 20 135.9 mm 7.62 mm 322.6 mm 490

Table 40: Tray specification

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 74 of 77

CC2500
32.5 Carrier tape and reel specification
Carrier tape and reel is in accordance with EIA Specification 481.
Tape and Reel Specification
Package Tape Width Component Hole Reel Units per Reel
Pitch Pitch Diameter
QLP 20 12 mm 8 mm 4 mm 13 inches 2500

Table 41: Carrier tape and reel specification

33 Ordering Information

Ordering part number Description Minimum Order Quantity (MOQ)

1167 CC2500 - RTY1 QLP20 RoHS Pb-free 490/tray 490 (tray)

1190 CC2500 - RTR1 QLP20 RoHS Pb-free 2500/T&R 2500 (tape and reel)

1192 CC2500 SK Sample kit 5pcs. 1

10069 CC2500_CC2550 DK Development Kit 1

Table 42: Ordering information

34 General Information

34.1 Document History

Revision Date Description/Changes
1.1 2005-10-20 MDMCFG2[7] used. 26-27 MHz crystal range. Chapter 15: description of the 2 optional
append bytes. Added matching information. Added information about using a reference
signal instead of a crystal. CRC can only be checked by append bytes or
CRC_AUTOFLUSH. Added equation for calculating RSSI in dBm. Selectivity performance
graphs added.
1.0 2005-01-24 First preliminary release.

Table 43: Document history

34.2 Product Status Definitions

Data Sheet Identification Product Status Definition
Advance Information Planned or Under This data sheet contains the design specifications for
Development product development. Specifications may change in
any manner without notice.
Preliminary Engineering Samples This data sheet contains preliminary data, and
and First Production supplementary data will be published at a later date.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
No Identification Noted Full Production This data sheet contains the final specifications.
Chipcon reserves the right to make changes at any
time without notice in order to improve design and
supply the best possible product.
Obsolete Not In Production This data sheet contains specifications on a product
that has been discontinued by Chipcon. The data
sheet is printed for reference information only.

Table 44: Product status definitions

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 75 of 77

CC2500
34.3 Disclaimer
Chipcon AS believes the information contained herein is correct and accurate at the time of this printing. However,
Chipcon AS reserves the right to make changes to this product without notice. Chipcon AS does not assume any
responsibility for the use of the described product; neither does it convey any license under its patent rights, or the rights
of others. The latest updates are available at the Chipcon website or by contacting Chipcon directly.
As far as possible, major changes of product specifications and functionality, will be stated in product specific Errata Notes
published at the Chipcon website. Customers are encouraged to sign up to the Developers Newsletter for the most recent
updates on products and support tools.
When a product is discontinued this will be done according to Chipcon’s procedure for obsolete products as described in
Chipcon’s Quality Manual. This includes informing about last-time-buy options. The Quality Manual can be downloaded
from Chipcon’s website.
Compliance with regulations is dependent on complete system performance. It is the customer’s responsibility to ensure
that the system complies with regulations.

34.4 Trademarks
SmartRF® is a registered trademark of Chipcon AS. SmartRF® is Chipcon's RF technology platform with RF library cells,
modules and design expertise. Based on SmartRF® technology Chipcon develops standard component RF circuits as well
as full custom ASICs based on customer requirements and this technology.
All other trademarks, registered trademarks and product names are the sole property of their respective owners.

34.5 Life Support Policy

This Chipcon product is not designed for use in life support appliances, devices, or other systems where malfunction can
reasonably be expected to result in significant personal injury to the user, or as a critical component in any life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness. Chipcon AS customers using or selling these products for use in such
applications do so at their own risk and agree to fully indemnify Chipcon AS for any damages resulting from any improper
use or sale.

Preliminary Data Sheet (rev.1.1.) SWRS040 Page 76 of 77