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University of Mauritius

This document contains a 6 question exam for an Electronics 1 course. The exam covers topics including Boolean algebra, logic gates, flip-flops, and transistor circuits. It provides students with multiple choice and written response questions to test their understanding of fundamental electronics concepts and analyze various circuit diagrams. The exam is scheduled for May 9th, 2012 and students are instructed to answer all 6 questions within the 3 hour time limit.

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50 views

University of Mauritius

This document contains a 6 question exam for an Electronics 1 course. The exam covers topics including Boolean algebra, logic gates, flip-flops, and transistor circuits. It provides students with multiple choice and written response questions to test their understanding of fundamental electronics concepts and analyze various circuit diagrams. The exam is scheduled for May 9th, 2012 and students are instructed to answer all 6 questions within the 3 hour time limit.

Uploaded by

chets
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 10

UNIVERSITY OF MAURITIUS

FACULTY OF ENGINEERING

SECOND SEMESTER/YEARLY EXAMINATIONS

MAY 2012
PROGRAMME

BEng (Hons) Electronic and Communication Engineering/


BEng (Hons) Electrical and Electronic Engineering

MODULE NAME
DATE

Electronics 1
Wednesday

MODULE CODE

ELEC1002Y(1)

09 May 2012

TIME

13 :30 16:30 Hrs

NO. OF
QUESTIONS SET

INSTRUCTIONS TO CANDIDATES
Answer ALL questions.

DURATION
NO. OF QUESTIONS
TO BE ATTEMPTED

3 hours
6

ELECTRONICS 1 - ELEC 1002Y(1)


Answer ALL questions.
Question 1
(a)

The logic function F(X, Y) implemented by the circuit shown in Figure 1. is


equivalent to the logic function of a 2-input gate. What is this gate? Why?

F(X, Y)

Figure 1.1
[2 marks]
(b)

If {(y+z) = 0}, determine the value of [xy+xz+xw].


[2 marks]

(c)

Express the function f (x 1, x 2, x3) as a Product of Sums.

[2 marks]
(d)

Complete the truth table for the following Boolean functions:

X
0
0
0
0
1
1
1
1

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

[2 marks]
(e)

Simplify the following Boolean function F, together with the dont-care


conditions.
F(x, y, z) = m(0, 1, 2, 3, 4, 6, 12) + d(5, 10, 11, 13)
[4 marks]
(continued next page)

Page 1 of 9

ELECTRONICS 1 - ELEC 1002Y(1)


Question 1 (continued)
(f)

Design a circuit that takes two two-bit binary numbers (A1 and A0, B1 and B0)
and produces a true output when, in binary, A is greater than or equal to B.

(i)

Fill in the truth table.

(ii)

Fill in the Karnaugh map and use it to minimize the output.

(iii)

Draw the corresponding circuit.


[2 + 2 + 2 marks]

Question 2
(a)

(i)

Draw the circuit for a 3-to-8 decoder using AND gates and inverters. It
should have three inputs X, Y, and Z and eight outputs, A0, . . . , A7.

(ii)

Show how to implement an AND gate using just a two-input


multiplexer and constant inputs (0,1) without using additional gates.
[2 + 2 marks]

(b)

Draw a circuit for an eight-input multiplexer using three four-input


multiplexes and no other gates.
[2 marks]

(c)

Show how to implement F XY Z YZ X Y using


(i) a 3-to-8 decoder and an OR gate;
(ii) an 8 input multiplexer; and
(iii) a 4 input multiplexer (whose select inputs are X and Y) and an inverter.
[2 + 2 + 2 marks]
(continued next page)
Page 2 of 9

ELECTRONICS 1 - ELEC 1002Y(1)


Question 2 (continued)
(d)

Implement the function F(w, x, y, z) = m(3, 4, 5, 7, 10, 14) + d(1, 6, 15) using a 4
to 1 multiplexer with w and x as selector inputs.
[2 marks]

(e)

Express the output F of the circuit shown in Figure 2.1.


[2 marks]

Figure 2.1
(f)

What is the output, f(a, b, c, d), for the circuit of Figure 2.2?
[4 marks]

Figure 2.2

Page 3 of 9

ELECTRONICS 1 - ELEC 1002Y(1)


Question 3
(a)

In Figure 3.1, if the current state is Q3 Q2Q1Q0 = 1101, determine the new state
after the next positive edge of the clock signal.
[2 marks]

Figure 3.1
(b)

Show how to build a J-K flip-flop using a T flip-flop and some combinational
logic.
[4 marks]

(c)

Consider the circuit of Figure 3.2. It has two inputs (x and clock), and one
output (z). At reset, the circuit starts with the outputs of all flip-flops at 0.

Figure 3.2
(i)

Is this a Mealy machine or a Moore machine? Explain.

(ii)

Draw the state table for the circuit.

(iii)

Draw the corresponding state diagram.


[1 + 4 +2 marks]

(d)

A sequential circuit has three flip-flops A, B, C; one input x; and one output,
y. The state diagram is shown in Figure 3.3. Use J-K flip-flops to design the
circuit by treating the unused states as dont-care conditions.
[7 marks]

Figure 3.3
Page 4 of 9

ELECTRONICS 1 - ELEC 1002Y(1)


Question 4
(a)

Sketch iR and vo for the network shown of Figure 4.1 for the input shown.
[2 + 2 marks]

Figure 4.1
(b)

Sketch vo for the network shown of Figure 4.2 for the input shown. [4 marks]

Figure 4.2
(c)

Calculate Vo in the circuit of Figure 4.3.

[4 marks]

Figure 4.3
(continued next page)

Page 5 of 9

ELECTRONICS 1 - ELEC 1002Y(1)


Question 4 - (continued)
(d)

Draw an analog computing circuit to solve the following equations:


(i)

Simultaneous Equations:
3x + 2y = - 8
4x 3y = 6

(ii)

Differential Equation:

d3y
dy
3 0.8 , all initial conditions are 0.
3
dt
dx
(e)

[2 + 2 marks]

The output of the regulator circuit in Figure 4.4 is taken across the load
resistor RL. Assume that the zener diode has a nominal breakdown voltage of
12 V and requires a minimum of 20 mA in reverse breakdown. Also, assume
that the source voltage ranges between 16 V and 20 V.
If the load resistance RL varies between 600 and infinity (no load condition),
determine a value for Rs so that the regulator will function properly for all
specified input and output conditions.
[4 marks]

Figure 4.4

Page 6 of 9

ELECTRONICS 1 - ELEC 1002Y(1)


Question 5
(a)

For the circuit of Figure 5.1, determine:


(i)
(ii)
(iii)
(iv)

I B,
I C,
VE and
VCE.
[3 + 1 + 1 + 1marks]

Figure 5.1
(b)

For the voltage feedback circuit Figure 5.2, determine:


(i)
(ii)
(iii)
(iv)

I C,
V C,
VE and
VCE.
[2 + 1 + 1 + 1marks]

Figure 5.2
(continued next page)

Page 7 of 9

ELECTRONICS 1 - ELEC 1002Y(1)


Question 5 - (continued)
(c)

For the amplifier of Figure 5.3,


(i)
(ii)

draw the transfer curve and


determine the values of the trans-conductance, the output impedance
and the voltage gain.
Assume rd = 100 k.
All resistances are in ohms.
[2 + 7 marks]

VDD

3.3k
IDSS= 8mA I
D
Vp= -6V

Vo

Vin
1M
.

Rin

Ro
1k

Figure 5.3

Page 8 of 9

CS

ELECTRONICS 1 - ELEC 1002Y(1)


Question 6
(a)

For the circuit shown in Figure 6.1, determine


(i)
(ii)

the quiescent values IDQ and VGSQ, and


the potentials of the drain (VD) and of the source (VD).
[6 +2 marks]

Figure 6.1
(b)

For the circuit shown in Figure 6.2, determine


(i)
(ii)

the quiescent values IDQ and VGSQ, and


the potentials of the drain (VD) and of the source (VD).
[8 +4 marks]

Figure 6.2
END OF QUESTION PAPER
sg/

Page 9 of 9

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