Course Name: MICROCONTROLLER

Course Code: BEC405A

Course Faculty: Manjunath.M

1
Cours General
e Information

Course Code and Title :BEC405A/Microcontroller

Teaching Hours:: 3 : 0 : 0(L:T:P)
CIE Marks: 50 Marks
SEE :100(Scaled down to 50 Marks)
Total No. of Theory / Tutorial / Other Components :40
Hours
CO Topics to be discussed Hrs
Microcontroller: Microprocessor Vs Microcontroller, Microcontroller and Embedded
S Processors, Processor Architectures-Harvard Vs Princeton & RISC Vs CISC,8051
C245A.1 Architecture- Registers, Pin diagram, I/O ports functions Internal Memory 08
organization. External Memory (ROM & RAM) interfacing. (Text book 1-1.1,Text
book 2-1.0,1.1,3.0,3.1,3.2,3.3 Text book 3-Pg 5-9)
Instruction Set: Addressing Modes, Data Transfer instructions, Arithmetic
C245A.2 instructions, Logical instructions, Jump & Call Instructions Stack & Subroutine 08
Instructions of 8051 (with examples in assembly Language). (Text book 2-
Chapter 5,6,7,8, Additional reading Refer Textbook 3, Chapter 3
Timers/Counters & Serial port programming:
Basics of Timers & Counters, Data types & Time delay in the 8051 using C,
Programming 8051 Timers, Mode 1 & Mode 2 Programming, Counter
C245A.3 Programming (Assembly Language only). (Text book 2- 3.4, Text book 1-7.1, 08
9.1,9.2) Basics of Serial Communication, 8051 Connection to RS232,
Programming the 8051 to transfer data serially & to receive data serially using C.
( Text book 2- 3.5, Text book 1- 10.1,10.2,10.3 except assembly language
programs, 10.5).
Interrupt Programming: Basics of Interrupts, 8051 Interrupts, Programming Timer
C245A.4 Interrupts, Programming Serial Communication Interrupts, Interrupt Priority in 08
8051(Assembly Language only) ( Text book 2- 3.6, Text book 1-11.1,11.2,11.4,
11.5)
I/O Port Interfacing & Programming: I/O Programming in 8051 C, LCD
C245A.5 interfacing, DAC 0808 Interfacing, ADC 0804 interfacing, Stepper motor interfacing,
08
DC motor control & Pulse Width Modulation (PWM) using C only. (Text book 1-
7.2, 12.1, 13.1, 13.2, 17.2, 17.3)
Prerequisite Knowledge
for Course

 Experience in C and C++ is

necessary
 knowledge about Proteus
simulation
 Programming concepts Computer
Concepts
TEXT
BOOKS:
1.“The 8051 Microcontroller and Embedded Systems –
using assembly and C”, Muhammad Ali Mazidi and
Janice Gillespie Mazidi and Rollin D. McKinlay; PHI,
2006 / Pearson, 2006.
2.“The 8051 Microcontroller”, Kenneth J. Ayala, 3rd Edition,
Thomson/Cengage Learning.
3. Programming and Customizing The 8051 Microcontroller”, Myke Predko, Tata Mc.Graw-Hill Edition 1999(reprint 2003)

REFERENCE BOOKS:
1.“The 8051 Microcontroller Based Embedded Systems”,
Manish K Patel, McGraw Hill, 2014, ISBN:978-93-329-
0125-4.
2. “Microcontrollers: Architecture, Programming, Interfacing
and System Design”, Raj Kamal, Pearson Education,
2005.
Course Outcome: Students will be able to as an individual or team

SL No Course Outcomes (CO): Knowledg

e level
Describe the difference K2
C405A.1 between Microprocessors & Microcontrollers,
types of processor architectures
and Architecture of 8051Microcontroer
C405A.2 Discuss the types of 8051 K2
microcontroller addressing modes and
Instructions with Assembly language programs
C405A.3 Explain the programming K2
operation of Timers/Counters and serial port of
8051 Microcontroller
C405A.4 Illustrate the Interrupt structure K3
of 8051 Microcontroller and its programming

C405A.5 Develop C Programs to interface I/O devices K3

with 8051 Microcontroller
Practical Approaches/ Applications.
 Industry requires engineers basics of embedded
with strong and embedded systems
control techniques. is used in Air
 Embedded control via
Washing Machines; conditioners;
Microwave ovens; Traffic Lights;
Vehicle systems
microcontrollers
for gears, automatic window controls, and so on.
Modern cars have more
 Microcontrollers
 than
als use in100
dat microcontroller
communicati in router
controlled
are modules. congestion
Queue managers, o d a ons s,
controllers etc.
Applications of Microcontrollers
Cell Phones Microwave
Pager Oven
Watch Washing
Calculato Machines
r Video Electronic
Games Weight
Alarm Display
Clock Robotic System
3 : HIGH 2: Medium 1:Low
Program Outcomes
Course outcomes

Modern Tool Usage

Problem Analysis
(After completion of the course the student will be able to)

Environment and

Project manage-
Lifelong learning
Investigation of
Development of

Communication
Individual and
Engineer and

Sustainability
Engineering
Knowledge

Design and

Team work
problems
Solution

society

Ethics
Explain the difference between Microprocessors &
Microcontrollers, Architecture of 8051Microcontroller,
C246.1 3 2 2 1
Interfacing of 8051 to external memory and Instruction
set of 8051.
Write 8051 Assembly level programs using 8051
C246.2 instruction set, stacks, subroutines and interfacing of 3 3 3 2 2 1 2 2
simple switches, simple LEDs.
Explain the Interrupt system, operation of
C246.3 Timers/Counters and Serial port of 8051. 3 3 2 2 2 2 2

Write 8051 Assembly language program to generate

timings and waveforms using 8051 timers, to send &
C246.4 3 3 3 2 1 2 2 2 2 2
receive serial data using 8051 serial port and to
generate an external interrupt using a switch.

Write 8051 Assembly language programs to generate

square wave on 8051 I/O port pin using interrupt and
C Programme to send & receive serial data using
8051 serial port.
Interface and write programs to ADC 0804, LCD and
C246.5 3 2 3 2 2 2 2 2 2 2 3
Stepper Motor to 8051 using 8051 I/O ports.
GAP ANALYSIS & CONTENT BEYOND SYLLABUS

Resource Relevance
Date- % of to
Action Person
SN. Gap Month- student POs,
taken with
Year designation s PSOs
4

High level language Planned to conduct Individual

1 programming seminar student
All PO3,PSO1
activity

Extension techniques for how External

Workshop on Higher PO4,5,PSO
2 to use with high speed
Embedded controllers
resource All
2
processor and interfacing person
devices.

Mini Project1:
Measurement of Heart
Rate and Body
June-July, PO6,9,12,P
3 Industry related projects.
Temperature
2025
Group Activity All
SO2
Mini Project2:
RF ID Based object
Identification system
To Max Evidence Course
Tools Frequency
who Marks collected Outcomes
m
Marks Blue
Direct Assessment Methods

Twice books/Assignments
Internal
(Average /MCQ
assessment of two will be 50 1,2,3,4 and 5
/Seminars /Mini
tests computed) projects
+other
assessment
modes
End of course Answer scripts
End term
(Answer any 5 10 Maintained at 1,2,3,4 and 5
examinatio 0,s
Students out of 10 University
n cal
questions)
ing
to 1,2 and 4
Indirect Assessment

Middle of the
50- Feedback forms Delivery of the
course
ma course
Methods

rks 2 and 3
Surveys effectiveness of
Delivery of
End of course - Questionnaire
instructions and
Assessment
methods
Computer Internal Architecture

Source: https://automateinfra.com/category/computer/
MODULE 1: 8051 Microcontroller
1.1: Microprocessor Versus Microcontroller

MICROPROCESSORS
 CPU for Computers Source: (Image: Intel) (Howley)

 Microprocessor CPU Chip has no RAM,ROM,I/O and Timers

on Chip

Data Bus Many chips

Many chips on
on mother
mother board
boar
CPU
General- Serial
Purpose RAM ROM I/O Timer COM
Micro- Port Port
processor
Address Bus
• Intel’s x86: 8086,8088,80386,80486, Pentium
• Motorola’s 680x0: 68000, 68010, 68020,68030,6040

10
Microcontroller Internal Architecture

Source: https://www.iceeet.com/microcontroller/#google_vignette
Example: Peripheral Interface Controller (PIC) is
microcontroller developed by Microchip

Source: https://www.electronicshub.org/pic-microcontroller-architecture/
Microcontroller
 As technology moved from LSI to VLSI, it became possible to
build the microprocessor, memory and I/O devices on a single
chip.
 This came to be known as the ‘Microcontroller.
 A single-chip computer
 On-chip RAM, ROM, I/O ports...
 Example ： Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X
A single chip

CPU RAM

I/O Timer COM

ROM

Microcontroller
Serial
11 Port Port
Microcontroller :
• A microcontroller contains a
microprocessor and also one or more of the
following components.
 Memory
 Analog to Digital (A/D) converter
 Digital to Analog (D/A) converter
 Parallel I/O interface
 Serial I/O interface
 Timers and Counters
Microprocessor vs. Microcontroller
Microprocessor Microcontroller
• CPU is stand-alone, • CPU, RAM, ROM, I/O and timer
RAM, ROM, I/O, timer are all on a single chip
• are separate • fixed amount of on-chip ROM,
Designer
amount ofcan decide
ROM, RAMonand
theI/O RAM, I/O ports
ports.
• for applications in which cost,
• Expensive, versatility power and space are critical
• general-purpose
• single-purpose (control-
• High processing power
• oriented)
• High power consumption
• Low processing power
• Instruction sets focus on
• Low power consumption
processing-intensive
• Bit-level operations
• operations
Instruction sets focus on control
• Typically 32/64 – bit
Typically deep pipeline (5-20 • and bit-level operations
stages) • Typically 8/16 bit
13 Typically single-cycle/two-stage
pipeline
1.2 The Typical Embedded System
FPGA/ASIC/DSP/SoC
Microprocessor/controller Embedded
Firmware

Memory

Communication Interface

System
I/p Ports Core O/p Ports
(Sensors)
(Actuators)

Other supporting
Integrated Circuits &
subsystems

Embedded System

Real World
Microcontroller for EMBEDDED SYSTEM

• An embedded system can be defined as a

combination of computer hardwar and
e
software that does a specific job.

•The embedded software that is executed for specific job is

called firmware.

• Embedded systems are used in consumer electronics,

food processing industry, chemical plants, cement plants,

biomedical equipment's, telecommunication and security.
EMBEDDED SYSTEM ARCHITECTURE
 Embedded system is a dedicated computer-based
system for an application.
 The software is embedded in read only memory.
the
The hardware of an embedded system consists of the
following six main components:
a. Central processing unit
b. Memory

c. Input unit

d. Output unit

e. Application specific circuitry

f. Communication channels
Examples
 Personal information products: Cell phone, pager,
watch, pocket recorder, calculator
 Laptop components: mouse, keyboard, modem, fax
card, sound card, battery charger
 Home appliances: door lock,
alarm clock, thermostat, air
conditioner, TV remote, hair
 dryer, video
Toys: VCR, games,
small refrigerator,
cars, dolls, etc., cars are about 20-
exercise equipment,
30% silicon today, mostly microcontrollers ($4b/yr)

washer/dryer, microwave
Smart cards [credit cardsoven
plus]
 Usually anything with a keypad [simple calculators
however have dedicated calculator chips]
1.2: microcontrollers and embedded processors

• The main difference between

the microcontrollers and embedded processors is
makeup and integration!
• Embedded processors, while in a sense controlling the
system they are a part of, however, they require external
resources such as RAM and registers in order to do so.
In the other case, a processor is not a control system!
• Microcontrollers, on the other hand, contain everything
required to control a system in every single chip.
A microcontroller might contain an embedded processor as
part of its makeup, but most importantly it also combines
other computer parts, such as memory and signal registers,
in a single chip.
1.3: Harvard V/s Von-Neumann Processor/Controller
Architecture

 The terms Harvard and Von-Neumann refers to the processor architecture design.
 Microprocessors/controllers based on the Von-Neumann architecture shares a single
common bus for fetching both instructions and data. Program instructions and data are
stored in a common main memory
 Microprocessors/controllers based on the Harvard architecture will have separate data bus
and instruction bus. This allows the data transfer and program fetching to occur
simultaneously on both buses
 With Harvard architecture, the data memory can be read and written while the program
memory is being accessed. These separated data memory and code memory buses allow
one instruction to execute while the next instruction is fetched (“Pre-fetching”)

I/O CPU Memory

Program
CPU Data Memory
Memory

Single shared Bus

Harvard Architecture
Von-Neumann Architecture

Prefetching
1.3: Harvard V/s Von-Neumann Processor/Controller Architecture

Harvard Architecture Von-Neumann Architecture

Separate buses for Instruction and Single shared bus for Instruction and Data
Data fetching fetching
Easier to Pipeline, so high Low performance Compared to Harvard
performance can be achieved Architecture
Comparatively high cost Cheaper
No memory alignment problems Allows self- modifying codes
Since data memory and program Since data memory and program memory
memory are stored physically in are stored physically in same chip, chances
different locations, no chances for for accidental corruption of program
accidental corruption of program memory
memory
RISC vs CISC
1.4: RISC V/s CISC Processors/Controllers
CISC RISC

Greater no. of Instructions Lesser no. of instructions

Generally, no instruction pipelining feature Instruction Pipelining and increased execution
speed
Non-Orthogonal Instruction Set (All instructions Orthogonal Instruction Set (Allows each
are not allowed to operate on any register and instruction to operate on any register and use
use any addressing mode. It is instruction any addressing mode)
specific)
Operations are performed on registers or Operations are performed on registers only,
memory depending on the instruction the only memory operations are load and store
Limited no. of general purpose registers Large number of registers are available
Instructions are like macros in C language. A Programmer needs to write more code to
programmer can achieve the desired execute a task since the instructions are
functionality with a single instruction which in simpler ones
turn provides the effect of using more simpler
single instructions in RISC
Variable length Instructions Single, Fixed length Instructions
More silicon usage since more additional Less Silicon usage and pin count
decoder logic is required to implement the
complex instruction decoding.
Can be Harvard or Von-Neumann Architecture With Harvard Architecture ( separate buses for
data and instruction fetching)
IMPORTANT FEATURES -
MICROCONTROLLERS
IMPORTANT FEATURES
1.5: FEATURES OF 8051
 A microcomputer is a computer implemented on a very large scale
integration chip.
 The 8051 is the first microcontroller of the MCS-51 family, introduced
by Intel Corporation at the end of the 1980s.
 The 8051 family with its many enhanced members enjoys the largest
market share, estimated to be about 40%, among the various
microcontroller architectures.

 The salient features of the 8051 microcontroller are

 8 bit CPU

 On-chip clock oscillator

 4 Kbytes of on-chip program memory

 256 bytes of on-chip data random access memory

FEATURES OF 8051

 64K - 4K bytes of extended program memory address space

 64 Kbytes of extended data memory address space

 32 bidirectional I/O lines can be either used as four 8 bit ports or 32

individually addressable I/O lines

 Two 16 bit timers/counters(8051) & 3 timers/counters in 8052

 16 bit address bus multiplexed with port 0 and port 2

 8 bit data bus multiplexed with port 0

 Full duplex asynchronous receiver transmitter

 Five-vector interrupt structure with two priority levels

BLOCK DIAGRAM OF 8051 MICROCONTROLLER
1.5 Architecture of 8051
Source: https://www.righto.com/2017/02/reverse-engineering-surprisingly.html
ARCHITECTURE OF 8051

 The processor includes arithmetic and logic unit,

instruction decoder and timing generation unit
 Accumulator (A or Acc), B register and status
register(PSW)
 Arithmetic and Logic Unit: The Arithmetic and Logic Unit
(ALU) performs the computing functions.
 The accumulator is an 8 bit register. In arithmetic and
logical operations, one of the operands is in ‘A’
 register.
After the arithmetic/logical operations, are performed,
the result is stored in ‘A’ register and this affects
various flags namely Carry (C), Auxiliary Carry (AC),
Overflow (O), and Parity (P) of status register.
INSTRUCTION DECODER AND CONTROL

 The instruction decoder and control are parts of the

timing and control unit. When an instruction is fetched
from program memory, it is loaded in the instruction
register.
 The decoder decodes the instruction and establishes the
sequence of events to follow.
 The instruction register is not programmable and cannot
be accessed through any instruction.
 The timing generation and control unit synchronizes all
the microcontroller operations with the clock and
generates control signals necessary for communication
between the processor and peripherals.
ALU INSIDE
CPU REGISTERS
 ‘A’ Register (E0H):8051 has an 8 bit Reg.
A accumulator is used in all arithmetic and
 logical operations.
During arithmetic & logical operations, one
of the operands is stored in the accumulator.
 After the operation is performed, the result is
stored in the A.
In multiplication operation, one of the 8 bit
 operands is stored in
‘A’ register. After the operation, it stores the
lower byte of the

product in ‘A’ register.
In division operation, it holds an 8 bit
dividend and after the operation, the
CPU
REGISTERS
 ‘B’ Register (F0H): The 8 bit ‘B’ register is used
during multiply and divide operations.
 In multiplication operation, one of the 8 bit operands is
stored in ‘B’
register. After the operation, it stores the higher byte of
the
 In result operation,
division in it holds 8 bit divisor and after th
‘B’ register.
the operation e
 remainder is stored in ‘B’ register.
For other instructions, it can be used as an 8 bit
general purpose
 register.
Program‘B’ is bit Word
Status addressable
(D0H) register.
The 8 bit Program Status Word
(PSW) register contains the arithmetic status of the ALU
and the bank selects bits for the data memory.
PROGRAM STATUS WORD (D0H)

 After the arithmetic and logic operations, the C, AC, P,

and O flags of PSW register are set or reset
according to the result. In subtraction, the C and
AC bits operate as borrow and digit borrow flag
respectively. PSW is bit addressable register
CY PSW.7 Carry Flag
AC PSW.6 Auxiliary Carry Flag
F0 PSW.5 Flag 0 available to user for general purpose.
RS1 PSW.4 Register Bank selector bit 1
RS0 PSW.3 Register Bank selector bit 0
OV PSW.2 Overflow Flag
- PSW.1 User definable FLAG
Parity FLAG. Set/ cleared by hardware during instruction cycle
P PSW.0
to indicate even/odd number of 1 bit in accumulator.

We can select the corresponding Register Bank bit using RS0

and RS1 bits.
RS1 RS2 Register Bank Address
0 0 0 00H-07H
0 1 1 08H-0FH
1 0 2 10H-17H
1 1 3 18H-1FH
• CY, the carry flag − This carry flag is set (1) whenever there is
a carry out from the D7 bit. It is affected after an 8-bit addition
or subtraction operation. It can also be reset to 1 or 0 directly
by an instruction such as "SETB C" and "CLR C" where
"SETB" stands for set bit carry and "CLR" stands for clear
carry.
• AC, auxiliary carry flag − If there is a carry from D3 and D4
during an ADD or SUB operation, the AC bit is set; otherwise, it
is cleared. It is used for the instruction to perform binary coded
decimal arithmetic.
• P, the parity flag − The parity flag represents the number of
1's in the accumulator register only. If the A register contains
odd number of 1's, then P = 1; and for even number of 1's, P =
0.
• OV, the overflow flag − This flag is set whenever the result of
a signed number operation is too large causing the high-order
bit to overflow into the sign bit. It is used only to detect errors in
signed arithmetic operations.
Example

Show the status of CY, AC, and P flags after the addition of
9CH and 64H in the following instruction.

MOV A, #9CH
ADD A, # 64H

Solution: 9C 1001 1100

+64 0110 0100

1 0000 0000

CY = 1 since there is a carry beyond D7 bit

AC = 1 since there is a carry from D3 to D4

1.6: Programming Model
 Col lection of 8-bit,16-bit registers and
8-bit memory locations.
 These registers and memory locations b
can be made to use software y
instructions.
 Some special function registers makes
microcomputer as
microcontroller called SFR.
 Each register is assigned with a 8 bit
address except PC.
 Registers with * are byte/bit addressable.
8051 Programming Model
MEMOR
Y
 General Purpose RAM (30H to 7FH) bytes of internal
These 80 RAM
memory are available for storage. Access
general-purpose data
instructions with single area
byte of
operands to this
use thisarea
the main
for storage.
memory is fast as compared to memory, and
access to
 However, the system stack uses these 80 bytes and in
practice, little
space is left for general storage. The general
purpose RAM can be accessed using direct or
indirect addressing modes.
 The SFR registers are located within the internal
memory in the
address range 80H to FFH. Not all locations
within this range are defined. Each SFR has a
MEMORY
SFR REGISTER
 They have an address (within the range 80H to FFH) and a name,
which reflects the purpose of the SFR.

 Although 128 bytes of the SFR address space is defined, yet only 21
SFR registers are defined in the standard 8051.

 Undefined SFR addresses should not be accessed, as this might lead

to some unpredictable results.

 Note that some of the SFR registers are bit addressable. SFRs are
accessed just like normal internal RAM locations.

 CPU and internal peripheral modules use special function registers

for controlling the desired operation of the device. The special
function registers contain input and output ports, control register for
interrupts, timers, serial ports, etc.
INTERNAL RAM ORGANIZATION
BIT ADDRESS OF INTERNAL RAM
SPECIAL FUNCTIONREGISTERS
RESET VALUES OF THE SFRS
INTERNAL ROM MEMORY
MEMORY ORGANISATION
 The 8051 devices have 4 Kbytes of on-chip program memory and
256 bytes of on-chip data random access memory.

 In addition to internal memory, 64 Kbytes of program memory and 64

Kbytes of data memory can be interfaced with 8051 using port 0, port
2,
port 3.6, port 3.7, PSEN and EA pins.
 Program memory is accessed using the program counter (PC) and A, or
DPTR and A.

 Data memory is accessed using DPTR, R0 and R1 register.

 In 8051, port 0 and port 2 provide 16 bit address to access external

memory. Port 0 provides the lower 8 bit address (A0–A7) and 8 bit
data (D0–D7). This is called address/data multiplexing.

 Port 2 provides the upper 8 bit address (A8–A15).

 ALE pin of 8051 and 74LS373 latch are used to demultiplex AD0– AD7.
DATA AND ADDRESS MULTIPLEXING USING
ALE
ALTERNATE FUNCTIONS OF PORT
3
EXTERNAL
ROM
 When EA is connected to the ground, 8051 fetches
instructions from external ROM by using PSEN. Then, the
address of external ROM is 0000H to FFFFH.

 When EA is connected to Vcc, then it fetches instructions

from on-chip ROM 4 Kbytes.

 The address of on-chip ROM is 0000 to 0FFFH.

 For address 1000H to FFFFH, it fetches instructions from

external ROM. In this mode, 60 Kbytes of external ROM
can be interfaced with 8051 microcontroller

 The data can be stored both in internal and 64 Kbytes of

external data memory
DATA BUS, ADDRESS BUS AND CONTROL
SIGNALS
ON-CHIP AND OFF –CHIP MEMORY
DIGITAL I/O PORT AND
PERIPHERALS
• It contains four 8 bit parallel ports, named as port 0, port
1, port 2, and port 3.
• Ports are used to send or receive the data. Each bit of
the port can be configured as an input or an output and
also port 0 is used as low order address and data pins
(AD0–AD7).
• Port 2 is used as high order address pins (A8–A15) and
• port 3 is used by timers, serial port, external interrupt and
for sending control signals (RD, WR) to external data
memory.
• It contains two versatile timers—timer 0 and timer 1. Both
are 16 bit timers/counters and each timer consists of two
8 bit registers.
• It supports serial data transmission using universal
asynchronous receiver transmitter
PIN DIAGRAM OF
8051
 The 8051 microcontroller is a 40 pin DIP

 The crystal frequency is the basic clock

frequency of the microcontroller.
 The 8051 a +5V single suppl an is
requires
designed powerclock frequency
for 1 MHz minimum y d to
16 MHz
maximum clock frequency.
1.7 Pin diagram of 8051Microcontroller

• Pins 1 to 8 (Port 1): These pins are a bi-directional I/O port that can be
used for interfacing with external devices.
• Pin 9 (RESET): This pin is used to reset the microcontroller to its initial
values.
• Pins 10 to 17 (Port 3): These pins have multiple functions including
serving as interrupt inputs, timer inputs, control signals, and serial
communication signals.
• Pins 18 & 19 (XTAL1 & XTAL2): These pins are used for connecting
an external crystal oscillator that provides the clock signal for the
microcontroller.
• Pin 20 (VCC): This pin provides the power supply voltage (typically
+5V) to the microcontroller.
• Pin 21 to 28 (Port 2): These pins are another bi-directional I/O port that
can be used for various purposes.
• Pin 29 (PSEN): This pin is the Program Store Enable signal and is used
during the process of fetching instructions from program memory.
• Pin 30 (EA): This pin is the External Access input and is used to enable
or disable external memory interfacing.
• Pins 32 to 39 (Port 0): This is a bi-directional I/O port that also serves as
the lower order address bus for memory access.
• Pin 40 (GND): This pin is the ground connection for the
microcontroller.
8051 CONNECTED TO 12MHZ
CRYSTAL
AND RESET CIRCUIT
 Ceramic oscillator-low cost but frequency stability and
accuracy is less compare to crystal oscillator.
 Smallest time in μC is pulse. This Smallest time
accomplishes any simple instruction/complex instruction.
 2 pulses=1 state(sub operations: fetch/ decode/ execute/
write data)
 6 states= 1 machine cycle.
 Any instruction execution time is

 C= no. of machine cycles 8051 instruction uses.

 Crystal frequency:11.0592 M Hz to support for
different baud rates.
8051 CONNECTED TO 12MHZ
CRYSTAL
AND RESET CIRCUIT
EXTERNAL MEMORY
INTERFACING
 The 8051 devices have only 256 bytes of on-chip
data random access memory.
 In applications where large amount
of data random access memory is required, the
external data random access memory is
interfaced with
8051.
 Address, data, RD (P3.7) and WR (P3.6) pins
are used to interface data RAM.
 P3.7 and P3.6 are connected to RD and WR pins
of data RAM
CONNECTION TO EXTERNAL DATA
RAM
FIGURE 2.8 External Memory Connections
EA
•I 31 16
17
WR
RD
-----------------------------12272
II 29 PSEN - ..... 22
26 --26
Al3
25 A12 - 2 2
=
C"'-1
24 All - 23 23
C1._ 23 AlO --21 21
22 A9 - 24 24 6264
21 AB - 25 25 SK
C> 27128 RAM
18 19. A7 3 16K 3
17 16 • A6 4 EPROM 4
14 15 AS 5 5
13 373 12 • A4 6 6
8031 3 Latch 2 A3 7 7

-
-
4 5 A2 a a
7 6 Al 9 9
a l 11 9 AO 10 1 8 1 6 13 1 1 I01a 16 13 11
I 19 17 15 12 19 17 15 12
30 ALE
C) •
= C 32 AD7
oi. AD6
33
> 34 AD5
35 AD4
36 AD3
37 AD2
38 ADl
39 ADO

FIGURE 2.9 External Memory Timing

Port 0 =>( A_o_-A_7---1!~X

oo_-o_7 j_X
Port 2 => : AS A>5
: x _
ALE Pulse
< t Latch Address

Elllternal Mem<ffY Addressing

PSEN Pulse

Reading ROM Usina PSEN

PS
E naI ble

EN ' R OM

Read Pulse
I
Enable
RD
Read
I
I
I
Write Pulse
I
Enable
WR
Write
I
Accessina RAM Usina RD or WR
8051 Ports:
Introduction
• Number of 8051 ports : The ha fou
microcontroller
port P0,P1,P &8051P3.Th fou ports are s r
s 2
operations. Out ofe the 40r pin,32
require
pins are set fo i/o
aside for r fou
• ports P0,P1,P2&P3. Each port takes 8 th r
pins. e an
• When zero is written to a port , it becomes
All the ports
output. To are configured as input upon
Reset.
configure it as an input port, 1 needs to be sent to
the port.
PORT STRUCTURES AND
OPERATION
•These I/O pins allow the 8051 to monitor and
control other devices.

•Port 0, port 2 and port 3 pins are multiplexed with

an alternate function.

•Each port consists of a D latch, an output driver

and an input buffer.
PORT STRUCTURES AND
OPERATION
•To access external program and data memory
the
output driver of port 0 and port 2, and the input
•In thisofapplication,
buffer low order address lines (A7–
port 0 are used.
A0) and data bus(D7–D0) are multiplexed on
port 0. Port2 outputs the high-order address
lines(A15–A8).

•Port 3 pins are used as external interrupt, for

serial transfer, timer and external memory
control
signals
PORT STRUCTURES AND
OPERATION-PORT0
Port 0
 Port 0 is multi functioned port of microcontroller

 8051.
 Its SFR address is 80H.It is bit addressable
port.
 Function and use : It can be used as
simple input
/ output mode or for generating data
and lower
order address bus for external
memory (AD0 –AD7).
 In order to use the pins of the port 0 as
input and output each pin must be
connected to 10KΩ pull up resistor as shown
Port
0
Port 0 as Simple input port
 When port 0 is used as an input port, ‘1’ must be
written to the zer latch
correspondi will cause th outpu
ng
transistor to oswitch
thatoff and theboth e t in a
pin “floats”
high impedance
state. When configured input port the
microcontroller provides two facilities :
1. Read logic level on physical pin by asserting
read pin signal.
2. Read contents of internal latch by asserting
the
read latch signal. The latch is read when the
instruction is read- modify-write type
instruction. A read-modify-write signal is one,
wherein the instruction reads the data from
Port 0 as simple
output
 When port 0 is configured as an output port, the
latch pins
that are programmed to 0 will cause the
lower FET to turn
ON and pin is grounded.
 If a ‘1’ is written on to the latch pin the FET
will turn off and
the pin is pulled HIGH by external pull up
resistors.
PORT -
1
Port 1
 Port 1 is a one bit simple i/o port of microcontroller.
 Its SFR address is 90H.It does not have any extra
/alternate function like port 0.
Port 1 as simple input port
 When port 1 is used as an input port, ‘1’ must be th
written to e
corresponding port 1 latch bit. This causes off
the lower FET turn The pin and input to pin .
• buffer are pulled to logic HIGH by internal th
pull up load. e
Port is called as ‘quasi-
bidirectional’ port as its
output is pulled high with pull up
Port 1 as simple output
port
 When port 1 is used as an output port, the latch
pins that are
programmed to 0, will cause the lower FET
• turn on, the internal pull up to turn off and
input to the circuit is logic 0.
If ‘1’ is written onto the latch pin then it
will drive the input of external circuit high
through the pull up. The lower FET turns
off.
PORT
2
PORT
3
ALTERNATE
FUNCTIONS
BIT ADDRESS OF THE
PORTS
STACK
 A stack is a last-in-first-out (LIFO) memory.
SThe stack allows
all read and write operations to be carried

out through one

end and hence, the information that goes in
last will come
out first.
The stack can be implemented in hardware
or by software.
 Hardware stack is designed
PIC microcontroller containsby using a stack
hardware set
of
and high-speed
in the 8051registers in order to provide
a fast response. The disadvantage of this
microcontroller,
approach is that thethe stack isthe
size of implemented
stack is by
 A software stack is a last-in-first-out
software.
limited.
data structure
implemented by using a number of
 The
RAMsoftware stack provides an unlimited
locations.
stack size, that
STACK
POINTER
 The address of the stack is contained in a
register called the
stackstack
 The pointer.
pointer in bit register.The 8051
8051is an 8 has only
 128
Two bytes of internal
instructions, namely can
and be
POPused
are as stack
usually
SRAM
stack and
PUSH space.
used in
operations. The PUSH operation is
defined as writing to
the top or bottom of the stack, whereas the

POP operation
means reading from the top or bottom of
the stack.
When stack is accessed from the bottom,
the stack pointer is
incremented in a push and decremented
after a pop operation
STACK AND STACK POINTER
 SP=07h on RESET, data write and read is
illustrated as below.
CONTENTS OF THE STACK AFTER 3
PUSH INSTRUCTIONS
CONTENTS OF MEMORY AND STACK POINTER
AFTER 2 POP INSTRUCTIONS
8052 MICROCONTROLLER
 The 8052 is an enhanced version of 8051
microcontroller. The pin diagram and
instruction set of 8051 and 8052 are
practically the same.
 The 8052 differs from 8051 by internal
memory size and number of on-chip
timers.
 The number of timers/counters in 8052 is
three.
 The 8052 has 8 Kbytes of on-chip program
memory. The program memory can be
extended upto 64 Kbytes with external
PROGRAM MEMORY ORGANIZATION OF 8052
DATA MEMORY ORGANIZATION OF
8052
805
2
 The 8052 has two on-chip data RAM. In addition to 256
bytes of on-
chip data RAM of 8051, the 8052 has another
 128 bytes of data RAM
with address 80H–FFH.
The address of second data RAM has the same
 address assigned to special function registers.
Direct addressing mode is used to access
special function registers.
To differentiate parallel address space, indirect
 addressing mode is used to access second data
RAM. Registers R0 and R1 are used as pointers
and instructions MOV A, @R0 and MOV @R0, A
or MOV A, @R1 and MOV @R1, A are used to
access second data RAM.
Assignment -2
1. Describe the internal architecture of 8051
microcontroller with
2. block diagram. of
Explain the various flags in the PSW register.
3. discuss the function
each flag.
4. Explain the oscillator circuit and
5 timing of the 8051 microcontroller.
. What is stack? Explain the stack
6 operation with example. to
. Explain the
8051.The Internal
starting RAM
address of structure of and ROM
RAM is 05000h
7
8. 8051.
is 0B000h.
. List special function registers of 8051 including bit
What
a)ALare the functions
b)PSEN c) of the following 8051
addressable.
pins?
E EA
Interface 16 K Bytes of RAM and 32 K Bytes of
UNIT2
8051 INSTRUCTION SET

After you have completed this chapter, you

should be able to
 Explain the instruction syntax and data of
types
th 805
e 1
 Define a subroutine and Explain
its uses
 th addressing modes of the
Explain e 8051
 th instruction timings of the
Explain e 8051
 th instruction set of the
Explain e 8051
INSTRUCTION
SYNTAX
 Label :The label is the name/symbolic address for the
instruction. As the
program is assembled, the label will be given the
value of the address in
 This
whichfacilitates referencing
the instruction of the instruction at any
is stored.
point in the given program. Of course, not all
instructions will have labels.
 It is not necessary to define a symbol for the address
of an instruction,
unless that address is needed by a branch statement
elsewhere in the
A label can be any combination of upto 8 letters (A– Z),
 program.
numbers (0–9)
 and period (.).
any instruction will have
Label: Instruction ;comment
s
INSTRUCTION
SYNTAX
 Opcode: The opcode field contains a symbolic
representation of the operation. The operation tells the
assembler what action the statement has to perform.
 The 8051 assembler converts the opcode into a unique
machine language
(binary code) that can be acted on by the 8051 internal
circuitry.
 Operand: The opcode specifies what action to perform,
whereas the operand indicates where to perform the
action. The operand field contains the address of the
operand or the operand.
 Comment: To improve program clarity, a programmer uses
comments throughout the program. A comment always
begins with a semicolon (;) and wherever we code it, the
assembler assumes that all characters to its right are
comments.
 Any instruction will have the following
format
destinatio
Mnemonic(opcode) n,
source
8051 DATA
TYPES
ADDRESSING
MODES
 A microcontroll provide
for convenien of th
er
programmer, s,
various the cefor accessing
methods e
data needed in
the execution of an instruction.
 The various methods of accessing data are
called addressing
modes. The 8051 addressing modes can be
1. classified into the
following
2 Registercategories
addressing
.
Direct addressing
Immediate addressing
3
Indirect
.
addressing
4
. Indexed
5 addressing
. Absolute
6 addressing
. Long addressing
10
IMMEDIATE ADDRESSING
 Immediate addressing means that the
data is provided as part of the instruction
(which immediately follows the
instruction opcode).
 The mnemonic for immediate data is
#(pound) sign
 Any immediate data must start with (0-9)
otherwise 8051 treats this as label.
 Examples to illustrate immediate and Reg.
AM
REGISTER ADDRESSING
 Register addressing mode involves the use of
registers to hold the data to be manipulated.
 The lowest 32 bytes of the 8051 internal RAM are
organized as four banks of eight registers. Only one
bank is active at a time. Using names, R0 to R7 can
access any active register. One of the eight general
registers (R0 to R7) can be specified as the
instruction operand.
 The assembly language documentation refers to a
register generically as
Rn.
 A, DPTR and R0 to R7 are used. when R0 to R7 are
used other operand is to A data transfers only.
 Direct addressing mode is provided to allow us access to
internal data
memory, including Special Function Register
(SFR).
 In direct addressing, an 8 bit internal data
memory address is specified as part of the
instruction and hence, it can specify the address
only in the range of 00H to FFH. In this addressing
mode, data is obtained directly from the memory.
INDIRECT
ADDRESSING
 Indirect addressi provide a powerfu addressi
ng
capabili whic needs to be appreciated.
l ngindirec
ty, h s
mode uses The
a register to hold the tactual
address address
that will be used in data movement.
 ing
Registers R0, R1, and DPTR are the only
registers that can be used as data
pointers. Indirect addressing cannot be
used to refer to SFR registers. Both R0 and
R1 can hold 8 bit address and DPTR can
hold 16 bit address.
 @ symbol is the mnemonic of Indirect
Addressing Mode.
Example
s.
INDEXED ADDRESSING
 In indexed addressing, a separate register—
either the program counter (PC), or the data
pointer (DTPR) is used to hold the base
address, and the A is used to hold the offset
address.
 Adding the value of the base address to the
value of the offset address forms the
effective address.
 Indexed addressing is used with JMP or
MOVC instructions.
Look up tables are easily implemented with the
help of index
addressing.
RELATIVE
ADDRESSING
 Relative addressing is used only with conditional
jump
instructions. The relative address, often
referred to as an offset, is
an 8 bit signed number, which is
automatically added to the PC
to make the address of the next instruction.
 The 8 bit signed offset value gives an address
range of +127 to –
128 locations. The jump destination is usually
specified using a
label and the assembler calculates the jump offset
accordingly.
RELATIVE ADDRESSING
ABSOLUTE ADDRESSING
 Absolute addressing is used only by the AJMP (Absolute
Jump) and ACALL (Absolute Call) instructions.

 These are 2 bytes instructions. The absolute addressing

mode specifies the lowest 11 bit of the memory address
as part of the instruction.

 The upper 5 bit of the destination address are the upper

5 bit of the current program counter.

 Hence, absolute addressing allows branching only within

the current 2 K byte page of the program memory.

Ex.: AJMP loop1

ACALL loop2
LON ADDRESSING AND BIT INHERENT
G ADDRESSING
 The long addressing mode within the 8051 is used
with the instructions LJMP and LCALL. These are 3
byte instructions.
 The address specifies a full 16 bit destination
address so that a jump or a call can be made to a
location within a 64 K byte code memory space.
LCALL 5000h
LJMP 6000h
Bit Inherent: In this addressing, the address of the
flag which contains the operand, is implied in the
opcode of the instruction
Ex: CLR C
BIT DIRECT
ADDRESSING
 The RAM space 20H to 2FH and most of the special
function registers
are bit addressable. Bit address values are
between
Ex: MOV 00H to 7FH.
7Fh,C
SETB
00h
MOV
C,00h
8051 INSTRUCTIONS
 8051 instructions consist of 1 byte of opcode and 0 to 2 bytes of
operands.
 The instructions use 8 bit registers A, B, R0, R1, R2, R3, R4,
R5, R6,
R7 and also 16 bit registers, DPTR (data pointer) and PC
 The instructions of 8051 can be broadly classified under the following
(program
headings:
counter).
 Data transfer instructions

 Logical instructions

 Arithmetic instructions

 Branch instructions

 Subroutine instructions

 Bit manipulation instructions

DATA TRANSFER INSTRUCTIONS
 In this group, the instructions operatio of th
perform data transfer ns e
following types.
 NONE OF THE FLAG BITS
AFFECTED.
MOV destination, source
 Move the contents of a register
A to Rn
MOV R2,A
 Move an immediate 8 bit data to register A or to
 Move the contents of a register
Rn or to a
Rn to A
memory location
MOV A,R5
MOV
NOTE - MOV A,#78H, that
instructions MOV R3,#
are 86H,
not SFRs MOVin errors.
results
- Moving data 90H,#0AAH
:
to a direct address itself is not
predictable leads to errors.
DATA TRANSFER INSTRUCTIONS
 Move the contents of a memory location to A or A to
a memory location using direct and indirect
addressing
MOV A,60H
MOV 45H,A
MOV R0,#
60H
MOV A,@R0
 Move the contents of a memory location to Rn or
Rn to a memory location using direct addressing
MOV R6,60H
MOV 45H,R1
MOV 90H,60H
 Move the contents of memory location to
another memory location using direct and indirect
addressing
MOV 90H,60H
MOV
R1,#60H
MOV A,@R1
DATA TRANSFER
INSTRUCTIONS
 Move the contents of an external to or to a extern
memory A A n al
memory
MOVX destination,
source
MOVX A,@DPTR
MOVX A,@R0
MOVX
NOTE: only@DPTR,A
registers R0 ar used in
MOVXandA,@R0
R1 e indirect
 Move addressing
the contents of program memory to A
mode.
MOVC A,@A+PC
MOVC A,@A+DPTR
NOTE: - Data transfer from code only
memory to A register .
- 4K of Internal and 64 K of
DATA TRANSFER
INSTRUCTIONS
 and Pop instructions
Push PUSH source
POP
destinati
on
Note PUSH 0A0H
: POP 02H
When SP reaches 0ffh it rolls over
to 00h.
Only direct addressing mode regist nam
and no
RAM ends at 7Fh,pushes aboveer e.
 Exchange
resultsinstructions
in errors. SP is usually set
XCH
abovedestination, source
Register banks address.
XCH
A,R4
XCHD A,60h
Note: All exchanges are
internal only.
ARITHMETIC INSTRUCTIONS
 The8051 has powerful instructions in the arithmetic group
compared to other microcontrollers. It can perform addition,
subtraction, multiplication and division operations on 8 bit
numbers.
 ADD Group of Instructions
ADD dst, src
ADDC dst, src
 In this group, we have
instructions
- Addtothe contents of A with immediate data with or
without carry.
ADD A, #n
ADDC A, #n
- Add the contents of A with register Rn with or
without carry.
ADD A, #n
NOTE: C,AC,OV,PADDC
FLAGSA, #n
out of which C & affecte
AC get d.
All 8 bit contents overflows from
0FFh to 00h
DPTR overflow from 0FFFFH to
ARITHMETIC
INSTRUCTIONS wit or withou
carr the
 Add usincontents
direct and with contents of h
indirect
of A t
y
memory g addressing.
ADD A,
ADDR
ADDC A,
ADDR
 Increment
instructions ADD A, @Rp
ADDC A, @Rp
INC destination
Unsigned & Signed
Addition
Unsigned Consid
Addition:
95 = er
d 01011111b
+18 =
9d 1011110
284 1b
 The C Flag is set to 1 to forthe out from the
d =1
account
 The program could add the carryflagsum.
carry to another
00011100
that forms
b the
second byte
C of a larger number.
Example – 16-bit
Addition
CLR C to 56CAH
Add 1E44H ; Clear the CY
MOV A, flag
#44H ; The lower 8-bits of the
1st number
ADD A,
; The lower 8-bits of the
#CAH MOV
MOV A, #1EH ;The upper 8-bits of the 1st
number
2nd number
R1, A ; The result 0EH will be in R1.
ADDC A, #56H
MOV R2, ;The
;The upper
result of 8-bits
the of the 2nd
addition
CY = 1.
number
A is 75H

The overall result: 750E H will be in R2:R1.

CY = 0.
Signe Additio Consid
d n: er
- =
001d 11111111b
+02 =
7d 0001101
284
•Here 1b
There is a Carry bit 7 so the C is set to
fromisdalso=carry from bit6
and Flagand OV flag 1
is 0.
00011010b
•This condition tells, no action needed to
correct the sum.
Arithmetic
Instructions
DA A
– Decimal adjust the
accumulator. 2 digit packed
 Format the accumulator BCD
into a proper number.
 Operates
 only
Works only onthe
after the ADD
accumulator.
instruction.
 Add to 49
34 BCD ; Clear the CY
 CLR C flag in A
 MOV
A, A, ; ; Place 1st ADD
#49H #34HAdd number the 2nd
number.
;A =
7DH
DA A;
A = 83H
SUBTRACTION GROUP OF
INSTRUCTIONS
SUBB DST,SRC
 In this group, we have instructions to Subtract
the immediate data and
the contents of carry flag from A and
store the result in A.
SUBB
A,#45H
 Subtract the contents of register
Rn and the contents of carry flag from A and
store the result in A.
SUBB A,
Rn
 Subtract the contents of memory and the
contents of carry flag from
 SUBB

 – Subtract with Borrow.

 Subtract an operand and the previous
value of the borrow
 (carry)
A A - flag from the- accumulator.
<operand> CY.
 result is always saved in the
The accumulator.
 The CY flag is set/reset appropriately.
INC
– Increment the operand by one.
The operand can be a register, a direct
address,
an indirect address, the data pointer.
DEC
– Decrement the operand by one.
•The operand can be a register, a address,
direct
an indirect address.
Arithmetic Instructions
MUL AB
 Multiply A by B and place result in A:B
 Multiply the unsigned number in R3 by
Unsigned
by Por 2 number
Stor th resul in Extern RAM location
10h(MSB)
t . e ande t al s
11h(LSB)
Solution: MOV
A,0A0H
MOV 0F0H,R3
MUL AB
MOV R0,#11H
MOV @R0,A
DEC R0
MOV A,0F0
MOV @R0,A
Arithmetic
Instructions
DIV B
Divide A by B and place
EX.: result
Divide in th
A:Bunsigned in R3 by Unsigne
number by e Port 2.
number th result in d RAM
Store e External
locations
Solutio an 11h(quotient)
MOV A,0A0H
n:10h(remainder)
MOV 0F0H,R3 d
DIV B
MOV R0,#11H
MOV @R0,A
DEC R0
MOV A,0F0
MOV @R0,A
Logical
Operations
ANL / ORL: Work on byte sized operands or the CY flag.

• ANL A, Rn
• ANL A, direct
• ANL A, @Ri
• ANL A, #data
• ANL direct, A
• ANL direct, #data

• ANL C, bit
• ANL C,
/bit
Logical
Operations
XRL – Works on bytes only.
•XRL A, Rn
•XRL A, direct
•XRL A, @Ri
•XRL A, #data
• XRL direct, A
• XRL direct, #data

CPL / CLR
– Complement / Clear.
 – Work on the accumulator or a bit.
Ex: CLR P1.2
Logical Operations
RL / RLC / RR / RRC
– Rotate
the
accumul
• RL and RR without the carry
ator.

• RLC and RRC rotate through the carry.

• SWAP A
– Swap the upper and lower nibbles of the
• accumulator.
– No compare instruction.
Built into conditional branching instructions.
FIGURE 4.2 Register A Rotate Operations
7 6 5 4 3 2 lo
I
+ + + ± + + +--
·I- I
RLA

c 7 6 5 4 3 2 lo

--I · I ± ± 3: ± 3: 3"
Carry Flag
± RLCA
·I
[, ± + ± :E ± ± ± I • I
7 6 5 4 3 2 1 0

RRA

~
7

F
6

++
5 4

£ F
3 2

++
l 0

H
c
I• I
RRCA Carry Flag

7 6 5 4 3 2 l 0
High Nibble Low Nibble
I
I • . I
.
SWAP A
Bit Manipulation Instructions
 This group of instructions is associated with
the single-bit operations of the 8051.
 This group allows manipulating
the individual bits of bit addressable registers
and memory locations as well as the CY flag.
 The P, OV, and AC flags be directly
cannot
altered.
 • This group includes:
move.
 Set, clear, and, or complement,
 Conditional jumps.
Bit Manipulation Instructions
CLR – Clear a bit or the CY flag.
• CLR P1.1
• CLR C
SETB – Set a bit or the CY flag.
• SETB A.2
• SETB C
CPL – Complement a bit or the CY flag.

CPL 40H ; Complement bit 40 of the bit memor

addressable y
Bit Manipulation Instructions
ORL / ANL
– OR / AND a bit with the CY flag.
• ORL C, 20H ; OR bit 20 of bit addressable memory
with the CY flag
• ANL C, /34H ; AND complement of bit 34 of bit
addressable memory with the CY flag.
MOV
– transfer between a bit and the CY flag.
•Data
MOV C, 3FH ; Copy the CY flag to bit 3F the bit
of addressable memory.
• MOV P1.2, C ; Copy the CY flag to bit 2 of P1.
Bit Manipulation Instructions
JC / JNC
– Jump to a relative address if CY is set / cleared.
• JB / JNB
– Jump to a relative address if a bit is set / cleared.
• JB ACC.2, <label>

• JBC
– Jump to a relative address if a bit is set and clear
the bit.