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Programmable Dma Controller 8257

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kavya gogulamudi
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285 views

Programmable Dma Controller 8257

Uploaded by

kavya gogulamudi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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PROGRAMMABLE DMA

CONTROLLER 8257

G.SRI KAVYA
21P61A0206
CONTENTS
 Introduction

 Featuresof 8257
 8257 DMA Architecture

 8257 DMA pin diagram

 Advantages

 Disadvantages
INTRODUCTION
 DMA stands for Direct Memory Access.
 It is designed by intel tp transfer data at the
fastest rate.
 It allows the device to transfer the data directly
to/from memory without any interference of the
CPU.
 Using a DMA controller,the device requests the
CPU to hold its data,address and control bus,so
the device is free to transfer data directly to/from
the memory.
FEATURES OF 8257
Here is a list of some of the prominent pf features of 8257
 It has four channels which can be used over four I/O
devices.
 Each channel has 165-bit address and 14-bit counter.

 Each channel can transfer data upto 64 KB.

 Each channel can be programmed independently.

 Each channel can perform read,write and verify transfer


operations.
 It generates MARK signal to the peripheral device that
128 bytes have been transeferred.
 It operates in 2 modes,i.e,Master mode,Slave mode.
8257 DMA ARCHITECTURE
8257 PIN DIAGRAM
 DRQ0-DRQ3: These are the four individual channel
DMA request inputs,which are used by the peripheral
devices for using DMA services.When the fixed priority
mode is selected,yhe DRQ0 has the highest priority and
DRQ3 has the lowest priority among them.
 DACK0-DACK3:These are the active-low DMA
acknowledge lines,which updates the requesting
peripheral about the status of their request bu the
CPU,These lines can balso act as strobe lines for the
requesting devices.
 D0-D7: These are bidirectional,data lines which are used
to interface the system bus with the internal data bus of
DMA controller.
 LOW : It is active low bidirection tri-state line,which is
used to load the contents of the data bus to the 8-bit mode
register upper/lower byte of a 16-bit DMA address
register or terminal count register.
 CLK: It is a clock frequency signal which is required for
the internal operation of 8257.
 A0-A3: These are four least significant address lines.IN
these slave mode,they act as an input,which select one of
the registers to be read or written.In these master
mode,they are the four least significant memoty address
output lines generated by 8257.
 CS: It is an active –low chip select line.In the slave
mode,it enables the read/write operations to/from 8257.
 A4-A7: These are the higher nibble of the lower by
address generated by DMA in the master mode.
 READY: It is an active-high asynchronous input
signal,which makes DMA ready by inserting wait
states.
 HRO: The signal is used to receive the hold request
signal from the output device, In the slave mode,it is
connected with a DRQ input line 8257. in mastr mode,
it is connected with HOLD input of the CPU.
 HLDA: It is the hold acknowledgement signal which
indicates the DMA controlling peripheral by the CPU
when it is set to 1.
 MEMR: It is the low memory read signal,which is used to
read the data from the addressed memory locations during
DMA read cycles.
 MEMW: It is the active_low three state signal which is uesd
to write the data to the addressed memory location during
DMA write operation.
 AEN : This signal is used to disable the address bus/data bus.

 TC: It stands for ‘Terminal Count’,which indicates the


present DMA cycle to the present peripheral devices.
 MARK: The mark will be activated after each 128 cycles or
integral multiplies of it from the beginning .It indicates the
current DMA cycle is the 128th cycle since the previous
MARK output to the selected peripheral device.
 Vcc: It is the power signal which is required for the operation
of the circuit.
ADVANTAGES:
 Transferring the data without the involvement of the
processor will speed up the read-write task.
 DMA reduces the clock cycle requires to read or write a
block of data.
 Implementing DMA also reduces the overhead of the
processor.
DISADVANTAGES:
 As it is a hardware unit,it would cost to implement a
DMA controller in the system.
 Key-clustering problem can cover while using DMA
controller.

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