8051 Interfacing
8051 Interfacing
[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay]
Figure 5.6.1 shows how to access or interface ROM to 8051.
Port 0 is used as multiplexed data & address lines. It gives lower order (A7-A0) 8
bit address in initial T cycle & higher order (A8-A15) used as data bus.
8 bit address is latched using external latch & ALE signal from 8051.
Port 2 provides higher order (A15-A8) 8 bit address.
PSEN is used to activate the output enable signal of external ROM/EPROM.
[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay]
Figure 5.6.2 shows how to connect or interface external RAM (data memory) to 8051.
Port 0 is used as multiplexed data & address lines.
Address lines are decoded using external latch & ALE signal from 8051 to provide
lower order (A7-A0) address lines.
Port 2 gives higher order address lines.
RD & WR signals from 8051 selects the memory read & memory write operations
respectively.
Note:RD & WR signals: generally P3.6 & P3.7 pins of port 3 are used to generate
memory read and memory write signals. Remaining pins of port 3 i.e. P3.0-P3.5 can be
used for other functions.
Solved Examples:
Example 1: Design a μController system using 8051 to Interface the external RAM of
size 16k x 8.
Solution: Given, Memory size: 16k
Which means, we require 2n=16k: n address lines
Here n=14: A0 to A13 address lines are required.
A14 and A15 are connected through OR gate to CS pin of external RAM.
When A14 and A15 both are low (logic ‘0’), external data memory (RAM) is
selected.
Start 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
H
End 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FF
FH
Figure 5.6.3 shows interfacing of 16k x 8 RAM to 8051.
Start 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
H
End 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FF
FH
Start 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000
H
End 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FF
FH
Start 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000
H
End 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFF
FH
Figure 5.6.5 shows the interfacing of 16Kx8 Memory (ROM) and 32Kx8 RAM with 8051
Figure 5.6.5 16Kx8 Memory (ROM) and 32Kx8 RAM Interfacing with 8051
[Source: “The 8051Microcontroller and Embedded Systems: Using Assembly and C” by Mohamed Ali Mazidi,
Janice Gillispie Mazidi, Rolin McKinlay, pg.no.320]