Module 2: 8051 Assembly Language Programming (08 Hrs )

Reference-1, 2, 3 (Books) M. A. Mazidi, C. Kenneth J. Ayala, Satish Shah

2.1 Instruction set

2.2 Addressing mode

2.3 Assembler directives

2.4 Programs related to: arithmetic,

logical, delay, input, output port, serial
communication and interrupts
2.2 Addressing Modes
Definition:
1. A way to specify an address of the data/code to be searched.
2. Data/Code may be residing at any of the four places.

Instruction Register Memory I/O device

2.2 Addressing Modes of 8051
Addressing Modes

Direct Register Immediate External

Indirect

Register
Specific
Code Data
Addressing using MOV, MOVX and MOVC
Addressing Modes
 Direct

 Indirect
 Register

 Register specific
 Immediate
 External

a) Code access
b) Data access
Direct Addressing Mode
Definition:
• Data is available in the memory and the address of that memory is specified
in an instruction.

Examples: Internal
• MOV A,40H RAM
39H
• MOV R2,14H

Accumulator 40H

41H
Direct Addressing Mode
 Entire 128 bytes of RAM can be accessed using direct
addressing mode.
 It is most often used to access RAM loc. 30H – 7FH
(General Purpose RAM area).
 SFR address range from 80 – FFH
 MSB 0 = GP RAM and MSB 1= SFRs

 MOV R0, 7FH

 MOV R0, 80H
 MOV 56H, A
 MOV A, 4 ; MOV A, R4
 MOV 6, 2 ; copy R2 to R6
 MOV R6,R2 is invalid !
caution
There are gaps in the address of the SFR’s these address are
not in order.
All the numbers must start with 0-9 or assembler assumes
the number as label.
MOV instruction that refer to direct address above 7FH
that are not SFR’s result in error.
The SFR’s are physically on chip while all other addresses
above 7FH are not physically exist.
Moving data to port (write) changes the port latch and
moving data from a port gets data from port pins.
Moving data from a direct address to itself is not
predictable and could lead in errors.
Indirect Addressing Mode (@)
Definition:
• Data is available in the memory and the address of that memory is available in R0
or R1 and that register is specified in an instruction.

Examples:
• MOV A,@R0

• MOV @R0,A
Internal
RAM
39H

R0
Accumulator 40H
40H
41H
Caution
The numbers in the register must be a RAM address.
Only register R0 or R1 may used for indirect addressing.
Register ADDRESSING MODE

 The 8 or 16-bit address of the source or destination is

specified in registers
1) Uses registers R0 or R1 for 8-bit address:
 MOV PSW, #00 ; use register bank 0
 MOV R0, #0X3C ; R0 = 3CH
 MOV @R0, #3 ; memory at 3C gets #3
; M[3C]  3
2) Uses DPTR register for 16-bit addresses:
 MOV DPTR, #0X9000 ; DPTR  9000H
 MOVX A, @DPTR ; A  M[9000]
 Note that 9000 is an address in external Data memory
Register Addressing Mode
Definition:
• Data is available in the register and that register is specified in an instruction.

Examples:
• MOV A,R2

• MOV R2,A

Accumulator R2
Register Addressing Mode
 Each register bank consist of registers R0 to R7.

 MOV Rn, A ;n=0,..,7

 ADD A, Rn
 MOV DPL, R6

 MOV DPTR, A
 MOV Rm, Rn
caution
It is impossible to have immediate data as a destination.
All the numbers must start with 0-9 or assembler assumes the number as label.
Register to register moves using the register addressing mode occur between A register and R0
to R7
Register Specific Addressing Mode
Definition:
• Data is available in the specific register such as A register or DPTR.

Examples:
• SWAP A

• RR A

• DA A
Immediate Addressing Mode (#)
Definition:
• Data is available in the instruction itself.

Examples:
• MOV A,#30H

• MOV DPTR,#1234H

• MOV R0,#54H
Accumulator 30H
Immediate Addressing Mode
 Specify data by its value

 MOV A, #00 ; put 0 in the A register

; A = 00000000

 MOV R4, #11H ; put 11hex in the R4 register

; R4 = 00010001

 MOV B, #11 ; put 11 decimal in b register

; B = 00001011

 MOV DPTR, #7521H ; put 7521 hex in DPTR

; DPTR = 0111010100100001
caution
It is impossible to have immediate data as a destination.
All the numbers must start with 0-9 or assembler assumes the number as label.
External Data Memory Addressing Mode

Definition:
• Data is available in the external Data
memory and the address of that memory is
either in R0, R1 or DPTR.
Examples:
• MOVX A,@R0
• MOVX A,@DPTR
External Addressing Mode

Data access (External RAM access)

 MOVX A, @R0
 MOVX A, @DPTR
 MOVX @R0, A
 MOVX @DPTR, A
caution
All the external data moves must involve the
A register.
R0 can address 256Bytes (FFH) and
DPTR can access 64KB
MOVX is normally used with external RAM or I/O addresses.
External code Memory Addressing Mode

Code access (External ROM access)

 MOVC A, @A+DPTR
 MOVC A, @A+PC
caution
PC is incremented by 1 (to point next instruction)
before it is added to A register to form final address of code byte.
All the data move from code memory to A register.
MOVC is normally used with internal or external ROM and can address 4KB internal
& 64KB external code access.
Push and pop op codes

SP + 2 Y SP
PUSH Y POP Y
SP + 1 X SP - 1
PUSH X POP X

SP SP - 2

Increment Internal RAM Decrement

before (above 07H) after POPing
PUSHing
Caution
When SP reaches to FFH it “Rolls over” to 00H(R0).
RAM ends at address 7FH PUSH after 7FH result in error.
The SP is usually set at addresses above resister bank
(30-7FH)
Data exchange
XCH A,Rr
XCH A,40H
XCH A, @R0
XCHD A, @R0
caution
All exchanges are internal to 8051.
All exchanges uses register A.
 when using XCHD upper nibble of register A and R do not change.
2.1 Instruction Set
Instructions treat different types of operands uniformly. Register, memory and
immediate operands may be specified in most instructions.

The instruction set is divided into number of groups of functionally related

instructions.
2.1 Instruction Set

 Instruction set is divided into following groups

1) Data transfer group
2) Arithmetic group
3) Logical group
4) Bit manipulation group
5) Program transfer & Machine control group
Data transfer group
MOV: No flags of PSW are affected.
1) MOV A,Rn
2) MOV A,direct --- MOV A,40H
3) MOV A,@Ri
4) MOV A,#data
5) MOV Rn,A
6) MOV Rn,direct
7) MOV Rn,#data
8) MOV direct,A
9) MOV direct,Rn
Data transfer group…
MOV:
10)MOV direct,direct --- MOV 20H,30H
11)MOV direct,@Ri --- MOV 20H,@R0
12)MOV direct,#data --- MOV 20H,#20H
13)MOV @Ri,A
14)MOV @Ri,direct --- MOV @R1,20H
15)MOV @Ri,#data
Data transfer group…

MOV:
• 16 bit data transfer involving the
DPTR
 MOV DPTR,#1234h
Data transfer group…
MOVC:
Move Code Byte
Load the A register with a byte from program memory.
Must use indexed addressing

MOVC A, @A+DPTR
MOVC A, @A+PC
Data transfer group…
MOVX:
Data transfer between the A register and
a byte from external data memory.
MOVX A, @Ri
MOVX A, @DPTR
MOVX @Ri, A
MOVX @DPTR, A
Data transfer group…
PUSH/POP:
Push and Pop a data byte onto the stack.
The data byte is identified by a direct
address from the internal RAM locations.
PUSH DPL
POP 40H
Data transfer group…
 XCH:
Exchange A register and a byte variable
XCH A, Rn
XCH A, direct
XCH A, @Ri

XCHD:
Exchange lower digit of A register with the lower digit of the
memory location specified.
XCHD A, @Ri

The lower 4-bits of the A register are exchanged with the lower 4-bits of
the internal memory location identified indirectly by the index register.
The upper 4-bits of each are not modified.
Data Transfer Group
MOV <dest-byte >, < src-byte > ; dest  source
Instruction Example Operation Addressing Bytes Machine Clock Flags
Mode Cycle pulses
MOV A, Rn MOV A, R1 A = R1 Register 1 1 12 No
MOV Rn, A MOV R5, A R5 = A Register 1 1 12 No
MOV A, Direct MOV A, 40H A = (40) Direct 2 1 12 No
MOV direct, A MOV 80H, A (80) = A Direct 2 1 12 No
MOV A, @Ri MOV A, @R0 A = ((R0)) Register 1 1 12 No
indirect
MOV A, # data MOV A, #30 A = 30 Immediate 2 1 12 No
MOV Rn, Direct MOV R3, 30H R3 = (30) Direct 2 2 24 No
MOV Rn, # data MOV R7, #25H R7 = 25 Immediate 2 1 12 No
MOV direct, Rn MOV 30H, R5 (30) = R5 Direct 2 2 24 No
MOV direct, direct MOV 20H, 30H (20) = (30) Direct 3 2 24 No
MOV direct, @Ri MOV 20H, @R1 (20) = ((R1)) Register 2 2 24 No
indirect
MOV direct, # data MOV 20H, #10H (20) = 10 Immediate 3 2 24 No
Data Transfer Group
Instruction Example Operation Addressing Bytes Machine Clock Flags
Mode Cycle pulses

MOV @Ri, A MOV @R0, A ((R0)) = A Indirect 1 1 12 No

MOV @Ri, Direct MOV @R0, 30H ((R0)) = (30) Direct 2 2 24 No
MOV @Ri, # data MOV @R0, #30H ((R0)) = 30 Immediate 2 1 12 No
MOV DPTR, # data 16 MOV DPTR, # 1234H DPTR = 1234 Immediate 3 2 24 No
MOVC A, @A+ MOVC A, @A+DPTR A = ((A) Indirect 1 2 24 No
< base register > MOVC A, @A+PC +DPTR))
MOVX < dest-byte >, MOVX A, @R0 A = ((R0)) Register 1 2 24 No
< src-byte > indirect
MOVX A, @DPTR A = (DPTR)
MOVX @Ri, A ((R0)) = A
MOVX @DPTR, A (DPTR) = A
Data Transfer Group
Instruction Example Operation Addressing Bytes Machine Clock Flags
Mode Cycle pulses
PUSH < direct > PUSH DPL (DPL)  (SP+1) Direct 2 2 24 No
PUSH DPH (DPH)  (SP+2)
POP < direct > POP DPL (SP)  DPL Direct 2 2 24 No
SP = SP - 1
XCH A, < byte variable> XCH A, Rn Register 1 1 12 No
XCH A, R1 (A) (R1)
XCH A, direct Direct 2 1 12 No
XCH A, 10H (A) (10)
XCH A, @Ri Register 1 1 12 No
XCH A, @R0 (A) ((R1))
XCHD A, @Ri XCHD A, @R0 (A)(3-0) Register 1 1 12 No
((R0(3-0))) indirect
Arithmetic group

CY, AC and OV flags of PSW are affected.

ADD:
1) ADD A,Rn
2) ADD A,direct
3) ADD A,@Ri
4) ADD A,#data
ADDC:
5) ADDC A,Rn
6) ADDC A,direct
7) ADDC A,@Ri
8) ADDC A,#data
Arithmetic group…
SUBB:
1) SUBB A,Rn
2) SUBB A,direct
3) SUBB A,@Ri
4) SUBB A,#data
Arithmetic group…
INC:
1) INC Rn
2) INC direct
3) INC @Ri DEC DPTR
4) INC DPTR IS
DEC: INVALID
5) DEC Rn
6) DEC direct
7) DEC @Ri
Arithmetic group…
MUL AB:
• Multiply A by B and place result in B:A.

DIV AB:
• Divide A by B and place result as follows:
• Quotient in A
• Remainder in B
DA A:
• Decimal adjust A register for addition.
Arithmetic Group

Instruction Example Addressing Bytes Machine Clock Flags

Mode Cycle pulses
ADD A, < src-byte >
ADD A, Rn ADD A, R0 Register 1 1 12 All
ADD A, direct ADD A, 20H Direct 2 1 12 All
ADD A, @Ri ADD A, @R0 Register indirect 1 1 12 All
ADD A, # data ADD A, # 40H Immediate 2 1 12 All

ADDC A, < src-byte >  Add with Carry

ADDC A, Rn ADDC A, R1 Register 1 1 12 All
ADDC A, direct ADDC A, 20H Direct 2 1 12 All
ADDC A, @Ri ADDC A, @R0 Register indirect 1 1 12 All
ADDC A, # data ADDC A, # 40H Immediate 2 1 12 All
Arithmetic Group
Instruction Example Addressing Bytes Machine Clock Flags
Mode Cycle pulses
SUBB A, < src-byte >  Subtract with Borrow
SUBB A, Rn SUBB A, R0 Register 1 1 12 All
SUBB A, direct SUBB A, 20H Direct 2 1 12 All
SUBB A, @Ri SUBB A, @R0 Register indirect 1 1 12 All
SUBB A, # data SUBB A, # 40H Immediate 2 1 12 All

INC < byte >  Increment

INC Rn INC R4 Register 1 1 12 No
INC < direct > INC 30H Direct 2 1 12 No
INC @Ri INC @R1 Register indirect 1 1 12 No
INC DPTR INC DPTR Register 1 2 24 No
Arithmetic Group
Instruction Example Addressing Bytes Machine Clock Flags
Mode Cycle pulses
DEC < byte >  Decrement
DEC Rn DEC R4 Register 1 1 12 No
DEC < direct > DEC 30H Direct 2 1 12 No
DEC @Ri DEC @R1 Register indirect 1 1 12 No

Other Arithmetic Operations

MUL AB MUL AB Register 1 4 48 All
A = Lower Byte
B = Higher Byte
DIV AB DIV AB Register 1 4 48 All
A = Quotient
B = Remainder
DA A DA A Register Specific 1 1 12 All
ex.
OVF
Logical Group
For AND,OR,EX-OR & SWAP No flags of PSW are affected.
ANL/ORL/XRL:
1) ANL A,Rn
2) ANL A,direct
3) ANL A,@Ri Same for
4) ANL direct,A ORL and
5) ANL A,#data
6) ANL direct,#data XRL
Logical Group…
CLR A:
◦ A register is loaded with ZERO.

CPL A:
◦ Complement of A is loaded in A.

SWAP A:
◦ Low order nibble and high order nibble of A will be
interchanged.
Logical Group…

RR – RL – RRC – RLC A

RR:

C
RRC:

RL:

C
RLC:
Logical Group
Instruction Example Addressing Bytes Machine Clock Flags
Mode Cycle pulses
ANL < dest-byte >, < src-byte >
ANL A, Rn ANL A, R3 Register 1 1 12 No
ANL A, Direct ANL A, 50H Direct 2 1 12 No
ANL A, @Ri ANL A, @R2 Register indirect 1 1 12 No
ANL Direct, A ANL 30H, A Direct 2 1 12 No
ANL A, # data ANL A, #45H Immediate 2 1 12 No
ANL Direct, # data ANL 54H, #33H Immediate 3 2 24 No
Logical Group
Instruction Example Addressing Bytes Machine Clock Flags
Mode Cycle pulses
ORL < dest-byte >, < src-byte >
ORL A, Rn ORL A, R3 Register 1 1 12 No
ORL A, Direct ORL A, 50H Direct 2 1 12 No
ORL A, @Ri ORL A, @R2 Register indirect 1 1 12 No
ORL Direct, A ORL 30H, A Direct 2 1 12 No
ORL A, # data ORL A, #45H Immediate 2 1 12 No
ORL Direct, # data ORL 54H, #33H Immediate 3 2 24 No
Logical Group
Instruction Example Addressing Bytes Machine Clock Flags
Mode Cycle pulses
XRL < dest-byte >, < src-byte >
XRL A, Rn XRL A, R3 Register 1 1 12 No
XRL A, Direct XRL A, 50H Direct 2 1 12 No
XRL A, @Ri XRL A, @R2 Register indirect 1 1 12 No
XRL Direct, A XRL 30H, A Direct 2 1 12 No
XRL A, # data XRL A, #45H Immediate 2 1 12 No
XRL Direct, # data XRL 54H, #33H Immediate 3 2 24 No
Logical Group

Instruction Example Operation Addressing Bytes Machine Clock Flags

Mode Cycle pulses
CLR A CLR A Clear Accumulator Register Specific 1 1 12 No
CPL A CPL A Complement Register Specific 1 1 12 No
Accumulator
RL A RL A Rotate A to left Register Specific 1 1 12 No
RLC A RLC A Rotate A to left through Register Specific 1 1 12 Only
Carry Cy
RR A RR A Rotate A to right Register Specific 1 1 12 No
RRC A RRC A Rotate A to right Register Specific 1 1 12 Only
through Carry Cy
SWAP A SWAP A (A3-0) (A7-4) Register Specific 1 1 12 No
Bit Level Operations
1) ANL C,bit
2) ANL C,/bit
3) ORL C, bit
4) ORL C,/bit
5) MOV bit,C
6) MOV C,bit
7) CLR bit
8) CLR C
9) SETB bit
10)SETB C
11)CPL bit
12)CPL C
Bit Manipulation Group
Instruction Example Addressing Bytes Machine Clock Flags
Mode Cycle pulses
CLR Bit CLR C Register 1 Only Cy
1 12
CLR P2.3 Direct 2 No

SETB Bit SETB C Register 1 Only Cy

1 12
SETB P2.3 Direct 2 No

CPL Bit CPL C Register 1 Only Cy

1 12
CPL P2.4 Direct 2 No

ANL C, < src-bit > ANL C, ACC.4 Direct 2 2 24 Only Cy

ORL C, < src-bit > ORL C, ACC.4 Direct 2 2 24 Only Cy

MOV < dest-bit >, < src-bit >

MOV bit, C MOV ACC.3, C Direct 2 2 24 No
MOV C, Bit MOV C, ACC.4 Direct 2 1 12 Only Cy
Branch Operations
1)SJMP relative offset
 Offset is 8 bit long.
2)AJMP addr11
 Lower 11 bits of PC will be replaced with
addr11.
3)LJMP addr16
 New value of PC will be addr16.
4)JMP @A+DPTR
 (PC) = (A) + (DPTR)
Branch Operations
Program Transfer & Machine Control Group
Instruction Operation Example Bytes Machine CLK
Cycle pulses
Short Jump:- (-128
byte to +127 byte) (PC) = ((PC) +2) SJMP SUB 2 2 24
SJMP rel (8-bit (PC) = (PC) + rel
address)
Absolute Jump:-
(within 2K) (PC) = ((PC) +2) AJMP Back 2 2 24
AJMP addr 11 (Opcode (PC10-0) = Page
21) address

Long Jump:- (within (PC) = ((PC) +3)

64K) (PC15-0) = LJMP Back 3 2 24
LJMP addr 16 Address15-0

JMP @A+DPTR (PC) = JMP 1 2 24

(A) + (DPTR) @A+DPTR
Branch Operations…
1) JZ rel If A = 0
2) JNZ rel If A ≠ 0
3) JC rel
4) JNC rel
5) JB bit,rel
6) JNB bit,rel
7) JBC bit,rel
Program Transfer & Machine Control Group
Instruction Operation Example Bytes Machine Clock
Cycle pulses
JZ rel (Jump if ACC is 0) (PC) = (PC) + 2 JZ Back 2 2 24
IF A = 0
THEN (PC) = (PC) + rel

JNZ rel (Jump if ACC is (PC) = (PC) + 2 JNZ Back 2 2 24

not 0) IF A is not equal to 0
THEN (PC) = (PC) + rel

JC rel (Jump if carry is (PC) = (PC) + 2 JC Back 2 2 24

set) IF C = 1
THEN (PC) = (PC) + rel

JNC rel (Jump if carry is (PC) = (PC) + 2 JNC Back 2 2 24

not set) IF C = 0
THEN (PC) = (PC) + rel
Program Transfer & Machine Control Group
Instruction Operation Example Bytes Machine Clock
Cycle pulses
JB bit, rel (Jump if bit set) (PC) = (PC) + 3 JB P2.1, Back 3 2 24
IF (bit) = 1
THEN (PC) = (PC) + rel

JNB bit, rel (Jump if bit (PC) = (PC) + 3 JNB P2.1, Back 3 2 24
not set) IF (bit) = 0
THEN (PC) = (PC) + rel

JBC bit, rel (Jump if bit set (PC) = (PC) + 3 JBC P2.1, Back 3 2 24
& clear bit) IF (bit) = 1
THEN
Bit= 0 and
(PC) = (PC) + rel
Subroutine Operations

 ACALL addr11
 Lower 11 bits of PC will be replaced with addr11.
 LCALL addr16
 New value of PC will be addr16.
 RET
 Top two bytes from stack will be popped and loaded in PC.
 RETI
 Return from interrupt routine.
Program Transfer & Machine Control Group
Instruction Operation Example Bytes Machine Clock
Cycle pulses
Absolute Call:- (within 2K) (PC) = ((PC) +2)
ACALL addr 11 (Opcode 31) (SP) = (SP) + 1 ACALL 2 2 24
Delay
((SP)) = (PC7-0)
(SP) = (SP) + 1
((SP)) = (PC15-8)
(PC10-0) = Page address

Long Call:- (within 64K) (PC) = ((PC) +3)

LCALL addr 16 (SP) = (SP) + 1 LCALL 3 2 24
((SP)) = (PC7-0) Delay
(SP) = (SP) + 1
((SP)) = (PC15-8)
(PC15-0) = Address15-0
Program Transfer & Machine Control Group
Instruction Operation Example Bytes Machine Clock
Cycle pulses
RET (PC15-8) = ((SP)) RET 1 2 24
(SP) = (SP) - 1
(PC7-0) = ((SP))
(SP) = (SP) – 1

RETI (PC15-8) = ((SP)) RETI 1 2 24

(SP) = (SP) - 1
(PC7-0) = ((SP))
(SP) = (SP) – 1
Compare and Branch Operations
1) CJNE A, direct,rel
2) CJNE A,#data,rel
3) CJNE Rn,#data,rel
4) CJNE @Ri,#data,rel
5) DJNZ Ri,rel
6) DJNZ direct,rel
Program Transfer & Machine Control Group
Instruction Operation Example Bytes Machine Clock
Cycle pulses
CJNE < dest-byte >, < src-byte >, rel (Compare and Jump if not equal)
CJNE A, direct, rel (PC) = (PC) + 3 CJNE A, 60H, Back 3 2 24
IF
(dest-byte) < > (src-byte)
THEN
(PC) = (PC) + rel
If (dest-byte) < (src-byte)
THEN
C=1
ELSE
C=0
CJNE A, # data, rel Same as Above CJNE A, #60, Back 3 2 24
CJNE Rn, # data, rel Same as Above CJNE R2, #60H, Back 3 2 24

CJNE @Ri, # data, rel Same as Above CJNE @R1, #98, Back 3 2 24
Program Transfer & Machine Control Group
Instruction Operation Example Bytes Machine Clock
Cycle pulses
DJNZ < byte >, < ret-addr > (Decrement specified memory location/register by 1 and jump if not
zero)
DJNZ < byte >, < ret-addr > (PC) = (PC) + 2 DJNZ R5, SUB 2 2 24
(byte) = (byte) – 1
If (byte) < > 0
Then
(PC) = (PC) + rel
NOP No Operation NOP 1 1 12
2.3 Assembler Directives
ORG-Originate
The ORG directive allows us to set the beginning address.
The number after ORG may be Hex or Decimal.
If it is decimal assembler converts into Hex.
Ex : ORG 0000H.
Dbit
This directive defines bit type variable.
Ex
Name DBitInitial value
Num1 DBit 0 or 1.
Db- define byte
This directive defines byte type variable.
DB is used to define binary, decimal, hexadecimal and ASCII numbers.
Ex
Name DB Initial value Data type.
Num1 DB 24 Decimal
Num2 DB 00110011B Binary
Num3 DB 24H Hexadecimal
Num4 DB “237” ASCII
Equ- Equate
It is used to give a name to some value or symbol in the program.
EQU is used to define constant without occupying a memory location.
Each time when the assembler finds that name in the program it replaces that name
by assigned value.
Ex XYZ EQU 40H.
DS
This directive declares 24byte stack in data segment that starts at internal RAM
location 08H.
Public and Extrn
These directive are used where the source file start.
 The directive public declares the variables defined in a specific file that can be used in
the other source file.
The directive extrn declares the variables that are used in the present source file but
are defined in some other source file.
END
This directive is placed at the end of source and it acts the last statement of program.
The END directive terminate the entire program.
University Questions (EXTC)
 Dec-2009
1) Explain the difference between SJMP, AJMP and LJMP instructions of
8051. (05 Marks)
 May-2010
2) Explain any four bit level instructions of 8051. (04 Marks)

 May-2011
3) Explain the following instructions of 8051 (10 Marks)
(a) LCALL
(b) MOV @R0, iram addr
(c) MUL
(d) CJNE @Rp, #n, radd
(e) DJNZ Rn, radd
University Questions
 May-2011
1) Explain following assembler directives of ASM51. (05 Marks)
1. DBIT 2. DS 3.EXTRN 4. PUBLIC 5. ORG
2) Explain addressing modes of 8051 with examples. (10 Marks)

 Nov-2011
3) Explain following assembler directives of ASM51. (05 Marks)
1. DBIT 2. DS 3.EXTRN 4. PUBLIC 5. ORG
4) Explain addressing modes of 8051 with examples. (10 Marks)

 May-2012
5) Explain following instructions :- (04 Marks) 1.
XCHD A, @Ri 2. RETI

 May-2013
6) Explain different assembly directives of 8051. (05
University Questions (EXTC)
 May-2015
7) Explain 8051 assembler directives. (05 Marks)
8) For an 8051 system of 11.0592MHz. Find how long it takes to (10
Marks)
execute each of following instructions.
a) MOV R3,#55H
b) DJNZ R2,TARGET
c) LJMP
d) SJMP
e) MUL AB
9) Explain operations of PUSH and POP instructions with example. (05 Marks)