Verilog HDL

Unit 1. Chapter 1.

Overview of Digital Design with Verilog HDL

Sujay S N
Assistant Professor
Dept. of ECE
Dr. AIT, Bangalore

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Chapter-1 Syllabus

Overview of Digital Design with Verilog HDL

Evolution of CAD, emergence of HDLs, typical HDL-flow, why
Verilog HDL?, trends in HDLs. (Text1)

Ref:
Samir Palnitkar, “Verilog HDL: A Guide to Digital Design and Synthesis”,
Pearson Education, Second Edition.

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Evolution of Computer-Aided Digital Design
 The earliest digital circuits were designed with vacuum tubes
and transistors.
 Integrated circuits were then invented where logic gates were
placed on a single chip.
SSI (Small Scale Integration)
MSI (Medium Scale Integration)
LSI (Large Scale Integration)
VLSI (Very Large Scale Integration)
ULSI (Ultra Large Scale Integration)
GSI (Giant Scale integration)
 Designers could put thousands of gates on a single chip.
 Electronic Design Automation (EDA) techniques began to
evolve.
 The circuits were still tested on the breadboard and the
layout was done on paper or by hand on a graphic computer
terminal. 3
 Computer-Aided Design (CAD) tools refers to back-end
tools that perform functions related to place and route, and
layout of the chip .
 Computer-Aided Engineering (CAE) tools refers to tools
that are used for front-end processes such HDL simulation,
logic synthesis, and timing analysis.
 Designers used the terms CAD and CAE interchangeably.
 Refer to all design tools as EDA tools.

 complexity of circuits, it was not possible to verify these

circuits on a breadboard. Computer aided techniques
became critical for verification and design of VLSI digital
circuits.

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Emergence of HDLs
FORTRAN, Pascal, and C were being used to describe computer
programs that were sequential in nature.
Designers felt the need for a standard language to describe
digital circuits. Thus, Hardware Description Languages (HDLs)
came into existence.
HDLs allowed the designers to model the concurrency of
processes found in hardware elements.
Hardware description languages such as Verilog HDL and VHDL
became popular.
Verilog HDL originated in 1983 at Gateway Design Automation.
Later, VHDL was developed under contract from DARPA.
Both Verilog and VHDL simulators to simulate large digital
circuits quickly gained acceptance from designers.

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Still designers had to manually translate the HDL-based design
into a schematic circuit with interconnections between gates.

The advent of logic synthesis in the late 1980s changed the

design methodology.

Digital circuits could be described at a Register Transfer Level

(RTL) by use of an HDL.

The details of gates and their interconnections to implement

the circuit were automatically extracted by logic synthesis tools
from the RTL description.

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HDLs also began to be used for system-level design.

HDLs were used for simulation of system boards, interconnect

buses, FPGAs (Field Programmable Gate Arrays), and PALs
(Programmable Array Logic).

A common approach is to design each IC chip, using an HDL,

and then verify system functionality via simulation.

Verilog HDL is an accepted IEEE standard.

In 1995, the original standard IEEE 1364-1995 was approved.

IEEE 1364-2001 is the latest Verilog HDL standard that made

significant improvements to the original standard.

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Typical Design Flow

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In any design, specifications are written first. Specifications
describe abstractly the functionality, interface, and overall
architecture of the digital circuit to be designed.
At this point, the architects do not need to think about how they
will implement this circuit.
The behavioral description is manually converted to an RTL
description in an HDL.
From this point onward, the design process is done with the
assistance of EDA tools.
Logic synthesis tools convert the RTL description to a gate-level
netlist.
A gate-level netlist is a description of the circuit in terms of gates
and connections between them.

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 Logic synthesis tools ensure that the gate-level netlist meets
timing, area, and power specifications.
 The gate-level netlist is input to an Automatic Place and Route
tool, which creates a layout. The layout is verified and then
fabricated on a chip.
 Most digital design activity is concentrated on manually
optimizing the RTL description of the circuit.
 After the RTL description is frozen, EDA tools are available to
assist the designer in further processes.
 Designing at the RTL level has shrunk the design cycle times
from years to a few months.
 Behavioral synthesis tools have begun to emerge recently.
These tools can create RTL descriptions from a behavioral or
algorithmic description of the circuit.

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Importance of HDLs
HDLs have many advantages compared to traditional schematic-
based design.

Designs can be described at a very abstract level by use of HDLs.

Designers can write their RTL description without choosing a
specific fabrication technology.
If a new technology emerges, designers do not need to redesign
their circuit.
They simply input the RTL description to the logic synthesis tool .
The logic synthesis tool will optimize the circuit in area and
timing for the new technology.
Modify the RTL description until it meets the desired
functionality. Most design bugs are eliminated at this point. This
cuts down design cycle time.
 Designing with HDLs is analogous to computer programming.
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Popularity of Verilog HDL
Verilog HDL is a general-purpose hardware description
language that is easy to learn and easy to use. It is similar in
syntax to the C programming language.
Verilog HDL allows different levels of abstraction to be mixed
in the same model.
Most popular logic synthesis tools support Verilog HDL. This
makes it the language of choice for designers.
All fabrication vendors provide Verilog HDL libraries for
postlogic synthesis simulation.
The Programming Language Interface (PLI) is a powerful
feature that allows the user to write custom C code to interact
with the internal data structures of Verilog.

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Trends in HDLs

The most popular trend currently is to design in HDL at an

RTL level, because logic synthesis tools can create gate-level
netlists from RTL level design.
Formal verification and assertion checking techniques have
emerged. Formal verification applies formal mathematical
techniques to verify the correctness of Verilog HDL
descriptions and to establish equivalency between RTL and
gate-level netlists.
For very high-speed and timing-critical circuits like
microprocessors, the gate-level netlist provided by logic
synthesis tools is not optimal. In such cases, designers often
mix gate-level description directly into the RTL description to
achieve optimum results.

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https://veriloghdl15ec53.blogspot.com/

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