UNIT - IV

MICROCONTROLLER

Title Contents

Unit – IV Contents Architecture of 8051

Special Function
Registers(SFRs) I/O Pins Ports
and Circuits Instruction set
Addressing modes
Assembly language programming.
Text books: 1. Yu-Cheng Liu, Glenn A.Gibson, ―Microcomputer
Systems: The 8086 / 8088 Family- Architecture,
Programming and Design‖, Second Edition,
Prentice Hall of India, 2007.
2. Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin
McKinlay, ―The 8051 Microcontroller and Embedded
Systems: Using Assembly and C‖, Second Edition,
Pearson Education, 2011
Reference books: 1. Doughlas V.Hall, ―Microprocessors and
Interfacing, Programming and Hardware‖, TMH,2012

Prepared By Verified By

Dr.Venkatesh kanna T./Asst.Prof / ECE

Mrs.C.Rajani Assit.Prof/ ECE

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Intel 8051 Microcontroller

4.1 Introduction to microcontrollers

The powerful component is actually very simple in its essence. It was built using the
tested solutions and ingredients by the following recipe:

1. Processor was removed from the simplest of computers to be used as the

"brain" for the upcoming system.
2. Depending on the manufacturers' taste, some memory was added, a
few A/D converters, timers, I/O communication lines, etc.
3. It was all placed in a standard casing.
4. Simple software that everybody could learn was developed for controlling the
thing.

There are three decisive facts responsible for such a success of microcontrollers:
1. Their powerful, cleverly chosen electronics is able to control a variety of
processes and devices (industrial automatics, voltage, temperature, engines,
etc) independently or by means of I/O instruments such as switches, buttons,
sensors, LCD screens, relays
2. Their low cost makes them suitable for installing in places which
attracted no such interest in the past. This is the fact accountable for today's
market being swamped with cheap automatons and "intelligent" toys. 3.
Writing and loading a program into microcontroller requires practically no
previous schooling. All that is required is: any PC (software is very friendly and
intuitive) and one simple device (programmer) for loading a written program into
microcontroller.

4.2 Microprocessors Vs. Microcontrollers

Microprocessor

• CPU is stand-alone, RAM, ROM, I/O, timer are separate

• Designer can decide on the amount of ROM, RAM and I/O ports.
• Expansive
• Their instructions operate on nibbles, bytes, words, or even double words.
• Addressing modes provide access to large arrays of data using pointers and offsets.

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• Versatility
• General-purpose

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Microcontroller

• CPU, RAM, ROM, I/O and timer are all on a single chip
• Fix amount of on-chip ROM, RAM, I/O ports
• They have instructions to set and clear individual bits and perform bit operations.
• They have instructions for input/output operations, event timing, enabling and setting
priority levels for interrupts caused by external stimuli
• For applications in which cost, power and space are critical
• Single-purpose

CPU RAM ROM

A single chip

I/O Timer Serial

Port

4.3 Introduction to 8051 Microcontroller

The 8051 is one of the most popular microcontrollers in use today. Many
derivative microcontrollers have since been developed that are based on and
compatible with the 8051. Thus, the ability to program an 8051 is an important
skill for anyone who plans to develop products that will take advantage of
microcontrollers.

4.4 Features of the standard 8051

– 4K bytes internal ROM (program)

– 128 bytes internal RAM (data)

– Four 8-bit I/O ports

– Two 16-bit timers

– Serial interface

– 64K external code memory space

– 64K external data memory space

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– 210 bit-addressable locations

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4.5 Block diagram of 8051

External interrupts
On-chip Timer/Counter

Interrupt ROM for On-chip Timer 1 Counter

Control program RAM Inputs
Timer 0
code

CPU

Serial
Bus 4 I/O Ports
OSC Port
Control

P0 P1 P2 P3 TxD RxD
Address/Data

Figure 1 : Block diagram of 8051

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Architecture of 8051

Figure 2 : Architecture of 8051

Architecture of 8051

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Accumulator (ACC) :

The accumulator register act as an operand register, in case of some

instructions
.This may either be implicit or specified in the instruction. The Acc register has
been allotted and address in the on chip special function register bank.

B Register :

The register in used to store one of the operands for multiply and divide
instructions . In other instructions, it may just be used as a scratch pad. This
register is considered as a special faction register.

Program status word (PSW)

This set of flags contains the status information and is considered as one
on of the special registers.

Stack pointer (Sp) :

This 8 bit wide register is incremented before the data is stored on to the
stack using push or call instructions. The register contains 8 bit stack top
address. This stack may be defined anywhere in the on chip 128 by the RAM.
After reset, the SP register is initialized to
07. After each write to stack operation, the 8 bit contents of the operand are
stored on to the stack after incrementing the SP register by one . Thus if SP
contains 07H, the forthcoming PUSH operation will store the data at address 08
H in the internal RAM .The SP content will be incremented to 08.The 8051 stack
is not a top down data structure, like other Intel processors This register has also
been allotted an address in the special function register bank .

Data Pointer (DTPR)

This 16 bit register contains a higher byte (DPH) and the lower byte (DPL)
of a 16 bit external data RAM address. It is accessed as a 16 bit register or two
8bit register as specified above. It has been allotted two address in the special
Function register bank for its two bytes DPH and DPL

Port 0 to 3 latches and Drivers:

These four latches and drivers pairs are allotted to each of the four on chip
I/O Ports. These latches have been allotted addresses in the special function
8
register bank using the allotted address the user can communicate with these
ports. These are identified as P0, P1, P2 and P3

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Serial data buffer:

The serial data buffer internally contains two independent registers. one
of them is a transmit buffer which is necessarily a parallel .

Timing and control unit :

This unit derives all the necessary timing and control signal required for
the internal operation of the circuit It also derives control signal required for
controlling the external system bus oscillator : This circuit generates the basic
timing clock signal for the operation of the circuit using crystal oscillator .

Instruction Register :

This register decodes the opcode of an instruction to be executed and

gives information to the timing and control unit to generate necessary signals
for the execution of the instruction

EPROM and Program Address Register :

These blocks provide an on chip EPROM and a mechanism to internally

adders it Note that EPROM is not available in all 8051 versions.

RAM and RAM address Register .

This block provide internal 128 bytes of RAM and mechanism to address it
internally .

ALU :

The arithmetic and logic unit performs 8 bit arithmetic and logical
operations over the operands held by the temporary registers TMPI and
TMP2 .Users cannot access these temporary registers .

SFR Register Bank :

This is a set of special function registers which can be addressed using

their respective address which lie in the range 80 H to FFH . Finally the interrupt ,
serial port and timer units control and perform their special functions under the
control of the timing and control unit in serial out register . The other is called
receive butter which in a serial in parallel out register. Loading a byte to the
transmit buffer initiates serial transmission of that byte. The serial data butter in
identified as SBUF and is one of the special function registers. If a byte is written
10
to SBUF, it initiates serial transmission and if the SBUF is read, it reads received
serial data .

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Timer Register :

These two 16 bit register can be accessed as their lower and upper bytes.
For example TL0 represents the lower byte of the timing register 0, while TH0
represents higher bytes of the timing register 0. Similarly TL1 and TH1
represents lower and higher bytes of timing register 1. All these registers can be
accessed using the 4 addresses allotted to them which lies in the special
function registers. SFR address range, ie 80H to FFH .

Control Registers :

The special function registers IP, IE, TMOD, TCON, SCON and PCON contain
control and status information for interrupt timer/ counters and serial port.These
register have been allotted address in the SFR bank of 8051 .

Program Status Word Register(PSW): -

D7 D6 D5 D4 D3 D2 D1 D0

CY AC F0 RS1 RS0 OV ---- PF

It contains several status bits that reflect the current state of the CPU. Besides, this register
contains four mathematical flags (Carry flag, Auxiliary Carry, Overflow flag, parity bit) two
register bank select bits (RS1 & RS0), and one user-definable status flag (F0) and one bit is
not defined.

P - Parity bit: - If a number stored in the accumulator A contains even number of 1’s then
this bit will be automatically set (1), otherwise it will be cleared (0). It is mainly used during
data transmit and receive via serial communication.

OV Overflow: - Overflow occurs when the result of an arithmetical operation is larger than
255 and cannot be stored in one register. Overflow condition causes the OV bit to be set
(1). Otherwise, it will be cleared (0).

RS0, RS1 - Register bank select bits. These two bits are used to select one of four
register banks of RAM. By setting and clearing these bits, registers R0-R7 are stored in one
of four banks of RAM.

RS1 RS0 Space in RAM

0 0 Bank0 (00H-07H)
0 1 Bank1 (08H-0FH)
1 0 Bank2 (10H-17H)
1 1 Bank3 (18H-1FH)

F0 - Flag 0. This is a general-purpose user defined flagtheuse of this flag is decided by

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the user.

AC - Auxiliary Carry Flag: - It is used for BCD operations only. This flag is set to ‘1’ when
in the addition operation the carry is generated at bit position D3 or in subtraction operation
borrow is needed at the bit position D3.

CY - Carry Flag: - This flag is set to ‘1’ when in the addition operation the final carry is
generated or in subtraction operation the Minuend is less than the Subtrahend.

PC (Program Counter): -It addresses the next instruction byte address in the program
memory. Program memory is on chip i.e. is 0000H to 0FFFH, external to the chip for
addresses that exceeds 0FFFH or total external memory 0000h to 0FFFFH. The content of the
PC is automatically incremented after fetching of the instruction byte from the memory and
some instructions also change the value in the PC. The specialty of this register is it doesn’t
have any internal address.

DPTR (Data Pointer): - It is made up of two 8-bit registers those are DPH & DPL. This
register gives the memory addresses for internal and external code access and external data
access. The DPTR has two independent internal addresses, one for DPL and another for
DPH.

Internal Memory: - The 8051 Microcontroller has internal program memory (ROM) and
internal data memory (RAM). Due to this 8051 has a Harvard architecture, which uses a same
address in different memories, for code and data.

Internal RAM: - The 8051 microcontroller has 128 bytes of internal RAM, its address range
from 00H to 07FH. From 80H to 0FFH addresses are assigned to SFRs (Special Function
Registers). The internal RAM 128Bytes can divide into three parts. Those are

1. Register Banks – 32 Bytes (00H – 1FH)

2. Bit/Byte addressable memory – 16 Bytes (20H – 2FH)
3. User memory or General purpose memory—80 Bytes (30H – 7FH)

4.6 Memory Organization

The 8051 microcontroller utilizes the Harvard architecture, with separate

code and data spaces. Memory organization in 8051 is similar to that of the
industry standard 8051. There are three memory areas, as shown in Figure 3:

•Program Memory (Internal RAM, External RAM, or External ROM)

•External Data Memory (External RAM)

•Internal Data Memory (Internal RAM)

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Figure 3: 8051 Memory Map

4.6.1 Program Memory

8051 can address up to 64kB of program memory space, from 0000H to

FFFFH. The External Bus Interface services program memory when the MEMPSRD
signal is active. Program memory is read when the CPU performs fetching
instructions or MOVC. After reset, the CPU starts program execution from
location 0000H. The lower part of the program memory includes interrupt and
reset vectors. The interrupt vectors are spaced at eight-byte intervals, starting
from 0003H. Program memory can be implemented as Internal RAM, External
RAM, External ROM, or a combination of all three.

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Figure 4: Program memory

4.6.2 External Data Memory

8051 can address up to 64kB of external data memory space, from 0000H
to FFFFH. The External Bus Interface services data memory when the MEMRD
signal is active. Writing to external program memory is only supported in debug
mode using the OCI logic block and external debugger hardware and software.
8051 writes into external data memory when the CPU executes MOVX @Ri ,A or
MOVX @DPTR,A instructions. The external data memory is read when the CPU
executes MOVX A, @Ri or MOVX A,@DPTR instructions. There is improved
variable length of the MOVX instructions to access fast or slow external RAM and
external peripherals. The three low-ordered bits of the CKCON register control
stretch memory cycles. Setting CKCON stretch bits to logic 1 values enables
access to very slow external RAM or external peripherals.

There are two types of instructions; one provides an 8-bit address to the
external data RAM, the other a 16-bit indirect address to the external data RAM.
In the first instruction type, the contents of R0 or R1 in the current register bank
provide an 8-bit address. The eight high ordered bits of address are stuck at
zero. Eight bits are sufficient for external l/O expansion decoding or a relatively

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small RAM array. For somewhat larger arrays, any output port pins can be used
to output higher-order address bits. These pins are controlled by an output
instruction preceding the MOVX. In the second type of MOVX

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instructions, the data pointer generates a 16-bit address. This form is faster and
more efficient when accessing very large data arrays (up to 64kB), since no
additional instructions are needed to set up the output ports. In some situations,
it is possible to mix the two MOVX types. A large RAM array, with its high-order
address lines, can be addressed via the data pointer or with code to output high-
order address bits to any port followed by a MOVX instruction using R0 or R1.

4.6.3 Internal Data Memory

The internal data memory interface services up to 256 bytes of off-core

data memory. The internal data memory address is always one byte wide. The
memory space is 256 bytes large (00H to FFH) and can be accessed by direct or
indirect addressing. The SFRs occupy the upper 128 bytes. This SFR area is
available only by direct addressing. Indirect addressing accesses the upper 128
bytes of internal RAM. The lower 128 bytes contain work registers and bit
addressable memory. The lower 32 bytes form four banks of eight registers (R0-
R7). Two bits on the program memory status word (PSW) select which bank is in
use. The next 16 bytes form a block of bit-addressable memory space at bit
addressees 00H-7FH. All of the bytes in the lower 128 bytes are accessible
through direct or indirect addressing. The internal data memory is not
instantiated in 8051. The user may use internal memory resources if the
ProASICPLUS or Axcelerator families are used. The SX-A and RTSXS-S families
have no internal memory resources, thus the user would need to either create
and instantiate a distributed RAM or use an external memory device.

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Lower 128 Bytes of Internal RAM Upper 128 Bytes
of Internal RAM

Figure 5: Internal Data Memory

4.6.4 On-Chip Memory.

The 8051 includes a certain amount of on chip memory. On-chip memory is

really one of two (SFR) memory. The layout of the 8051's internal memory is
presented in the following memory map:

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Figure 6 : On-Chip Memory

As is illustrated in this map, the 8051 has a bank of 128 bytes of Internal RAM.
This Internal RAM is found on-chip on the 8051 so it is the fastest RAM available,
and it is also the most flexible in terms of reading, writing, and modifying it‘s
contents. Internal RAM is volatile, so when the 8051 is reset this memory is
cleared. The 128 bytes of internal ram is subdivided as shown on the memory
map. The first 8 bytes (00h - 07h) are "register bank 0". By manipulating certain
SFRs, a program may choose to use register banks 1, 2, or 3. These alternative
register banks are located in internal RAM in addresses 08h through 1Fh. We'll
discuss "register banks" more in a later chapter. For now it is sufficient to know
that they "live" and are part of internal RAM. Bit Memory also lives and is part of
internal RAM. Bit memory actually resides in internal RAM, from addresses 20h
through 2Fh. The 80 bytes remaining of Internal RAM, from addresses 30h
through 7Fh, may be used by user variables that need to be accessed frequently
or at high-speed. This area is also utilized by the microcontroller as a storage
area for the operating stack. This fact severely limits the 8051‘s stack since, as
illustrated in the memory map, the area reserved for the stack is only 80 bytes
and usually it is less since this 80 bytes has to be shared between the stack and
user variables.

4.6.5 Bit Memory

The 8051, being a communications oriented microcontroller, gives the user

the ability to access a number of bit variables. These variables may be either 1 or
0. There are 128 bit variables available to the user, numbered 00h through 7Fh.
The user may make use of these variables with commands such as SETB and
CLR. It is important to note that Bit Memory is really a part of Internal RAM. In
fact, the 128 bit variables occupy the 16 bytes of Internal RAM from 20h through
2Fh. Thus, if you write the value FFh to Internal RAM address 20h you‘ve
effectively set bits 00h through 07h. But since the 8051 provides special
instructions to access these 16 bytes of memory on a bit by bit basis it is useful
to think of it as a separate type of memory. However, always keep in mind that it
is just a subset of Internal RAM—and that operations performed on Internal RAM
can change the values of the bit variables.

Bit variables 00h through 7Fh are for user defined functions in their
programs. However, bit variables 80h and above are actually used to access
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certain SFRs on a bit-by- bit basis.

4.6.6 Special Function Register (SFR) Memory

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Special Function Registers (SFRs) are areas of memory that control specific
functionality of the 8051 processor. For example, four SFRs permit access to the
8051‘s 32 input/output lines. Another SFR allows a program to read or write to
the 8051‘s serial port. Other SFRs allow the user to set the serial baud rate,
control and access timers, and configure the 8051‘s interrupt system. When
programming, SFRs have the illusion of being Internal Memory. When using this
method of memory access (it‘s called direct address), any instruction that has an
address of 00h through 7Fh refers to an Internal RAM memory address; any
instruction with an address of 80h through FFh refers to an SFR control register.

4.7 8051 SFRs

What Are SFRs?

The 8051 is a flexible microcontroller with a relatively large number of

modes of operations. Your program may inspect and/or change the operating
mode of the 8051 by manipulating the values of the 8051's Special Function
Registers (SFRs). SFRs are accessed as if they were normal Internal RAM. The
only difference is that Internal RAM is from address 00h through 7Fh whereas
SFR registers exist in the address range of 80h

through FFh. Each SFR has an address (80h through FFh) and a name. The
following chart provides a graphical presentation of the 8051's SFRs, their
names, and their address.

As you can see, although the address range of 80h through FFh offer 128
possible addresses, there are only 21 SFRs in a standard 8051. All other
addresses in the SFR range (80h through FFh) are considered invalid. Writing to
or reading from these registers may produce undefined values or behavior

4.7.1 SFR Types

As mentioned in the chart itself, the SFRs that have a blue background are
SFRs related to the I/O ports. The 8051 has four I/O ports of 8 bits, for a total of
32 I/O lines. Whether a given I/O line is high or low and the value read from the
line are controlled by the SFRs in green. The SFRs with yellow backgrounds are
SFRs which in some way control the operation or the configuration of some
aspect of the 8051. For example, TCON controls the timers, SCON controls the
serial port. The remaining SFRs, with green backgrounds, are "other SFRs." These
SFRs can be thought of as auxiliary SFRs in the sense that they don't directly
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configure the 8051 but obviously the 8051 cannot operate without them. For
example, once the serial port has been configured using SCON, the program may
read or write to the serial port using the SBUF register.

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Figure 7 : SFR

4.7.1.1 SFR Descriptions

This section will endeavor to quickly overview each of the standard SFRs
found in the above SFR chart map. It is not the intention of this section to fully
explain the functionality of each SFR--this information will be covered in separate
chapters of the tutorial. This section is to just give you a general idea of what
each SFR does.

4.7.1.2 P0 (Port 0, Address 80h, Bit-Addressable):

This is input/output port 0. Each bit of this SFR corresponds to one of the
pins on the microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is pin
P0.7. Writing a value of 1 to a bit of this SFR will send a high level on the
corresponding I/O pin whereas a value of 0 will bring it to a low level.

4.7.1.3 SP (Stack Pointer, Address 81h):

This is the stack pointer of the microcontroller. This FR indicates where

the next value to be taken from the stack will be read from in Internal RAM. If
you push a value onto the stack, the value will be written to the address of SP +
1. That is to say, if SP holds the value 07h, a PUSH instruction will push the value
onto the stack at address 08h. This SFR is modified by all instructions which
modify the stack, such as PUSH, POP, LCALL, RET, RETI, and whenever interrupts
are provoked by the microcontroller.
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4.7.1.4 DPL/DPH (Data Pointer Low/High, Addresses 82h/83h):

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The SFRs DPL and DPH work together to represent a 16-bit value called
the Data Pointer. The data pointer is used in operations regarding external RAM
and some instructions involving code memory. Since it is an unsigned two-byte
integer value, it can represent values from 0000h to FFFFh (0 through 65,535
decimal).

4.7.1.5 PCON (Power Control, Addresses 87h):

The Power Control SFR is used to control the 8051's power control
modes. Certain operation modes of the 8051 allow the 8051 to go into a type of
"sleep" mode which requires much less power. These modes of operation are
controlled through PCON. Additionally, one of the bits in PCON is used to double
the effective baud rate of the 8051's serial port.

4.7.1.6 TCON (Timer Control, Addresses 88h, Bit-Addressable):

The Timer Control SFR is used to configure and modify the way in which
the 8051's two timers operate. This SFR controls whether each of the two timers
is running or stopped and contains a flag to indicate that each timer has
overflowed. Additionally, some non-timer related bits are located in the TCON
SFR. These bits are used to configure the way in which the external interrupts
are activated and also contain the external interrupt flags which are set when an
external interrupt has occurred.

Timer/Counter Control Register (TCON)

Table displays the TCON register flags.

MSB LSB

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

Table • TCON Register Bit Functions

Bit Symbol Function

Timer 1 overflow flag. This flag is set when Timer 1 overflows.

7 TF1 This flag
should be cleared by the user‘s software.
6 TR1 Timer 1 Run control bit. If cleared, Timer 1 stops.
Timer 0 overflow flag. This flag is set when Timer 0 overflows.
5 TF0 This flag
should be cleared by the user‘s software.
4 TR0 Timer 0 Run control bit. If cleared, Timer 0 stops.
3 IE1 Interrupt 1 edge flag. This flag is set when a falling edge on the
external pin
int1 is observed. This flag is cleared when an interrupt is
processed.
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2 IT1 Interrupt 1 type control bit. This bit selects whether a falling edge
or a low
level on input pin int1 causes an interrupt.
1 IE0 Interrupt 0 edge flag. This flag is set when a falling edge on the
external pin
int0 is observed. This flag is cleared when an interrupt is
processed.
0 IT0 Interrupt 0 type control bit. This bit selects whether a falling edge
or a low
level on input pin int0 causes an interrupt.

4.7.1.7 TMOD (Timer Mode, Addresses 89h):

The Timer Mode SFR is used to configure the mode of operation of each
of the two timers. Using this SFR your program may configure each timer to be a
16-bit timer, an 8- bit auto reload timer, a 13-bit timer, or two separate timers.
Additionally, you may configure the timers to only count when an external pin is
activated or to count "events" that are indicated on an external pin.

Timer/Counter Mode Control Register (TMOD)

MSB LSB

GATE C/T M1 M0 GATE C/T M1 M0

< Timer 1  < Timer 1 

Table • TMOD Register Bits Description

Bit Symbol Function

7,3 GATE If set, enables external gate control (pin int0 or int1 for Counter 0
or Counter 1, respectively). When int0 or int1 is high, and the trx
bit is set (see TCON register), the counter is incremented every
falling edge on the t0 or
t1 input pin.
6, 2 C/T Selects Timer or Counter operation. When set to logic 1, a Counter
operation is performed. When cleared to logic 0, the
corresponding register
will function as a Timer.
5, 1 M1 Selects the mode for Timer/Counter 0 or Timer/Counter 1.
4, 0 M0 Selects the mode for Timer/Counter 0 or Timer/Counter 1.
Table provides timer and counter mode descriptions.

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M1 M0 Mode Function
0 0 Mod 13-bit Counter/Timer, with five lower bits in the tl0 or tl1
e0 register and eight bits in the th0 or th1 register (for Timer 0
and Timer 1, respectively). The three high order bits of the
tl0 and tl1 registers are
held at zero.
Mode
0 1 16-bit Counter/Timer
1
1 0 Mode2 8-bit auto-reload Counter/Timer. The reload value is kept in o
the TH0 TH1 register, while the tl0 or tl1 register is r
incremented every machi cycle. When the tl0 or tl1 registerne
overflows, the value in the th0 or th1
register is copied to the tl0 or tl1 register, respectively.
1 1 Mode3 If the M1 and M0 bits in Timer 1 are set to logic 1, Timer 1 he
stops. If t
M1 and M0 bits in Timer 0 are set to logic 1, Timer 0 acts
as two independent 8-bit Timers/Counters.
4.7.1.8 TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Bh):

These two SFRs, taken together, represent timer 0. Their exact behavior
depends on how the timer is configured in the TMOD SFR; however, these timers
always count up. What is configurable is how and when they increment in value.

4.7.1.9 TL1/TH1 (Timer 1 Low/High, Addresses 8Ch/8Dh):

These two SFRs, taken together, represent timer 1. Their exact behavior
depends on how the timer is configured in the TMOD SFR; however, these timers
always count up. What is configurable is how and when they increment in value.

4.7.1.10 P1 (Port 1, Address 90h, Bit-Addressable):

This is input/output port 1. Each bit of this SFR corresponds to one of the
pins on the microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin
P1.7. Writing a value of 1 to a bit of this SFR will send a high level on the
corresponding I/O pin whereas a value of 0 will bring it to a low level.

4.7.1.11 SCON (Serial Control, Addresses 98h, Bit-Addressable):

The Serial Control SFR is used to configure the behavior of the 8051's on-
board serial port. This SFR controls the baud rate of the serial port, whether the
serial port is activated to receive data, and also contains flags that are set when
a byte is successfully sent or received.

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4.7.1.12 SBUF (Serial Control, Addresses 99h):

The Serial Buffer SFR is used to send and receive data via the on-board
serial port. Any value written to SBUF will be sent out the serial port's TXD pin.
Likewise, any value which the 8051 receives via the serial port's RXD pin will be
delivered to the user program via SBUF. In other words, SBUF serves as the
output port when written to and as an input port when read from.

4.7.1.13 P2 (Port 2, Address A0h, Bit-Addressable):

This is input/output port 2. Each bit of this SFR corresponds to one of the
pins on the microcontroller. For example, bit 0 of port 2 is pin P2.0, bit 7 is pin
P2.7. Writing a value of 1 to a bit of this SFR will send a high level on the
corresponding I/O pin whereas a value of 0 will bring it to a low level.

4.7.1.14 IE (Interrupt Enable, Addresses A8h):

The Interrupt Enable SFR is used to enable and disable specific interrupts.
The low 7 bits of the SFR are used to enable/disable the specific interrupts,
where as the highest bit is used to enable or disable ALL interrupts. Thus, if the
high bit of IE is 0 all interrupts are disabled regardless of whether an individual
interrupt is enabled by setting a lower bit.

4.7.1.15 P3 (Port 3, Address B0h, Bit-Addressable):

This is input/output port 3. Each bit of this SFR corresponds to one of the
pins on the microcontroller. For example, bit 0 of port 3 is pin P3.0, bit 7 is pin
P3.7. Writing a value of 1 to a bit of this SFR will send a high level on the
corresponding I/O pin whereas a value of 0 will bring it to a low level.

4.7.1.16 IP (Interrupt Priority, Addresses B8h, Bit-Addressable):

The Interrupt Priority SFR is used to specify the relative priority of each
interrupt. On the 8051, an interrupt may either be of low (0) priority or high (1)
priority. An interrupt may only interrupt interrupts of lower priority. For example,
if we configure the 8051 so that all interrupts are of low priority except the serial
interrupt, the serial interrupt will always be able to interrupt the system, even if

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another interrupt is currently executing. However, if a serial interrupt is
executing no other interrupt will be able to interrupt the serial interrupt routine
since the serial interrupt routine has the highest priority.

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4.7.1.17 PSW (Program Status Word, Addresses D0h, Bit-Addressable):

The Program Status Word is used to store a number of important bits that
are set and cleared by 8051 instructions. The PSW SFR contains the carry flag,
the auxiliary carry flag, the overflow flag, and the parity flag. Additionally, the
PSW register contains the register bank select flags which are used to select
which of the "R" register banks are currently selected.

4.7.1.18 ACC (Accumulator, Addresses E0h, Bit-Addressable):

The Accumulator is one of the most used SFRs on the 8051 since it is
involved in so many instructions. The Accumulator resides as an SFR at E0h,
which means the instruction MOV A,#20h is really the same as MOV E0h,#20h.
However, it is a good idea to use the first method since it only requires two
bytes whereas the second option requires three bytes.

4.7.1.19 B (B Register, Addresses F0h, Bit-Addressable):

The "B" register is used in two instructions: the multiply and divide
operations. The B register is also commonly used by programmers as an
auxiliary register to temporarily store values.

4.8 8051 Basic Registers

4.8.1 Accumulator

If you‘ve worked with any other assembly languages you will be familiar
with the concept of an Accumulator register. The Accumulator, as it‘s name
suggests, is used as a general register to accumulate the results of a large
number of instructions. It can hold an 8- bit (1-byte) value and is the most
versatile register the 8051 has due to the shear number of instructions that
make use of the accumulator. More than half of the 8051‘s 255 instructions
manipulate or use the accumulator in some way. For example, if you want to add
the number 10 and 20, the resulting 30 will be stored in the Accumulator. Once
you have a value in the Accumulator you may continue processing the value or
you may store it in another register or in memory.

4.8.2 "R" registers

The "R" registers are a set of eight registers that are named R0, R1, etc.
up to and including R7. These registers are used as auxiliary registers in many
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operations. The use of the "R" registers as a way to store values temporarily.

7.8.3 "B" Register

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The "B" register is very similar to the Accumulator in the sense that it may
hold an 8- bit (1-byte) value. The "B" register is only used by two 8051
instructions: MUL AB and DIV AB. Thus, if you want to quickly and easily multiply
or divide A by another number, you may store the other number in "B" and make
use of these two instructions. Aside from the MUL and DIV instructions, the "B"
register is often used as yet another temporary storage register much like a
ninth "R" register.

4.8.4 Data Pointer (DPTR)

The Data Pointer (DPTR) is the 8051‘s only user-accessible 16-bit (2-byte)
register. The Accumulator, "R" registers, and "B" register are all 1-byte values.
DPTR, as the name suggests, is used to point to data. It is used by a number of
commands which allow the 8051 to access external memory. When the 8051
accesses external memory it will access external memory at the address
indicated by DPTR. While DPTR is most often used to point to data in external
memory, many programmers often take advantage of the fact that it‘s the only
true 16- bit register available. It is often used to store 2- byte values which have
nothing to do with memory locations.

4.8.5 Program Counter (PC)

The Program Counter (PC) is a 2-byte address which tells the 8051 where
the next instruction to execute is found in memory. When the 8051 is initialized
PC always starts at 0000h and is incremented each time an instruction is
executed. It is important to note that PC isn‘t always incremented by one. Since
some instructions require 2 or 3 bytes the PC will be incremented by 2 or 3 in
these cases. The Program Counter is special in that there is no way to directly
modify it‘s value. That is to say, you can‘t do something like PC=2430h. On the
other hand, if you execute LJMP 2340h you‘ve effectively accomplished the same
thing. It is also interesting to note that while you may change the value of PC (by
executing a jump instruction, etc.) there is no way to read the value of PC.

4.8.6 Stack Pointer (SP)

The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit
(1-byte) value. The Stack Pointer is used to indicate where the next value to be
removed from the stack should be taken from. When you push a value onto the
stack, the 8051 first increments the value of SP and then stores the value at the
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resulting memory location. When you pop a value off the stack, the 8051 returns
the value from the memory location

indicated by SP, and then decrements the value of SP. This order of operation is
important. When the 8051 is initialized SP will be initialized to 07h. If you
immediately push a value

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onto the stack, the value will be stored in Internal RAM address 08h. This makes
sense taking into account what was mentioned two paragraphs above: First the
8051 will increment the value of SP (from 07h to 08h) and then will store the
pushed value at that memory address (08h). SP is modified directly by the 8051
by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI. It is also used
intrinsically whenever an interrupt is triggered

4.9 8051 Addressing Modes(8 mark)

An Addressing Mode indicates how the data is represented in the

instruction. 8051 supports 6 types of Addressing Modes, those are

1. Immediate Addressing mode

2. Register Addressing Mode
3. Register Indirect Addressing Mode
4. Direct Addressing Mode
5. Indexed Addressing Mode
6. Implicit Addressing Mode

1. Immediate Addressing Mode: -In these addressing mode instructions the data is
directly placed in the source operand field of the instruction, and a ‗#‘ symbol
must prefix for the data. Ex: -MOV A, #38H

ADD A, #67H

2. Register Addressing Mode: -In these addressing mode instructions the data is
directly placed in the operand field of the instruction through a GPR (General
Purpose Register).

EX: - MOV A, B

ADD A, R0

3. Register Indirect Addressing Mode: -In these addressing mode instructions the
address of the data is indirectly placed in the operand field of the instruction
through a GPR (General Purpose Register) R0 or R1.

Ex: - MOV A, @R0

ADD A, @R1

4. Direct Addressing Mode: - In these addressing mode instructions the address of

the data is directly placed in the operand field of the instruction. The address is
the internal RAM or internal SFR (Special Function Register).

Ex: - MOV A, 20H

MOV R1, 70H

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5. Indexed Addressing Mode: -In these addressing mode instructions the
address of the data is indirectly placed in the operand field of the instruction
through combination ‗A‘ register PC or DPTR.

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Ex: - MOVC A, @A+DPTR

MOVC A, @A+PC

6. Implied Addressing Mode: -In this addressing mode instruction the operand is
implicitly represented in the operation code of the instruction.

Ex: - NOP, RET, RETI

4.9 8051 Addressing Modes( 12Mark)

Definition:
The different ways in which a source operand in an instruction are known
as the addressing modes.
The 8051 provides a total of five distinct addressing modes
Immediate Addressing mode
Register Addressing mode
Direct Addressing mode
Register Indirect Addressing mode
Indexed Addressing mode

4.9.1 Immediate Addressing mode

In this addressing mode the source operand is constant. In immediate
addressing mode, when the instruction is assembled, the operand comes
immediately after the op-code.
The immediate data must be preceded by ‗#‘ sign.
This addressing mode can be used to load information into any of the
register, including the DPTR

Example:
MOV A,
#25H MOV
R4, #62
MOV B,
#40H
MOV DPTR, #4521H
Although the DPTR register is 16-bit, it can also be accessed as two 8-bit
registers, DPH and DPL, where DPH is the high byte and DPL is the low byte.

4.9.2 Register addressing mode

Register addressing mode involves the use of registers to hold the data to be
manipulated.

Example:

MOV A, R0 ;copy the contents of R0 into A

MOV R2, A ;copy the contents of A in to R2
ADD A, R5 ;add the contents of R5 to
contents of A ADD A, R7 ;add the contents of R7 to
contents of A MOV R6, A;save accumulator in R6

It should be noted that the source and destination registers must match in size

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4.9.3 Direct Addressing mode
The RAM has been assigned addresses 00 to 7FH. The following is a summary of
the allocation of these 128 bytes

RAM location 00 - 1FH are assigned to the register banks and stack

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RAM location 20 - 2FH are set aside as bit-addressable space to
save single-bit data.
RAM location 30 - 7FH are available as a place to save byte-sized data.

Although the entire 128 bytes of RAM can be accessed using direct
addressing modem it is most often used to access RAM locations 30 – 7FH. This
is due to the fact that register bank locations are accessed by the register names
of R0-R7, but there is no such name for other RAM locations

4.9.4 Register Indirect Addressing mode

In the register indirect addressing mode, a register is used as a pointer to the
data. If the data is inside the CPU, only registers R0 and R1 are used for this
purpose. When R0 and R1are used as pointers, that is, when they hold the
addresses of RAM locations, they must be preceded by the ―@‖sign.
Example:

MOV A, @R0 ;move contents of RAM location whose address is held

by R0 into A
MOV @R1, B ;move contents of B into RAM location whose
address is held by R1

Notice that R0 is preceded by the ―@‖ sign. In the absence of the ―@‖
sign, MOV will be interpreted as an instruction moving the contents of register R0
to A, instead of the contents of the memory location pointed to by R0.
Advantages:
One of the advantages of register indirect addressing mode is that it
makes accessing data dynamic rather than static as in the case of direct
addressing mode.

4.9.5 Indexed Addressing mode

In these addressing mode used access the program memory only.In these
addressing mode instructions the address of the data is indirectly placed in the
operand field of the instruction through combination ‗A‘ register PC or DPTR.

Ex: - MOVC A, @A+DPTR

MOVC A, @A+PC

4.9.6.Implied Addressing Mode: -In this addressing mode instruction the operand is
implicitly represented in the operation code of the instruction.

Ex: - NOP, RET, RETI

4.10 I/O PINS PORTS AND CIRCUITS

There are four ports P0, P1, P2 and P3 each use 8 pins, making them 8-
bit ports. All the ports upon RESET are configured as output, ready to be
used as output ports. To use any of these ports as an input port, it must
be programmed.

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Pin configuration of 8051/8031 microcontroller.

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Fig 4.2: Pin configuration of 8951

Port 0
Port 0 occupies a total of 8 pins (pins 32-39) .It can be used for input
or output. To use the pins of port 0 as both input and output ports
Each pin must be connected externally to a 10K ohm pull-up
resistor. Due to the fact that P0 is an open drain, unlike P1, P2,
and P3.
Open drain is a term used for MOS chips in the same way that open
collector is used for TTL chips. With external pull-up resistors connected
upon reset, port 0 is configured as an output port.
Example:

The following code will continuously send out to port 0 the alternating values
55H and AAH BACK:MOV A,#55H
MOV P0,A
ACALL DELAY
MOV

A,#0AAH MOV
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P0,A
ACALL DELAY
SJMP BACK

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Port 0 as Input
With resistors connected to port 0, in order to make it an input, the port
must be programmed by writing 1 to all the bits.
In the following code, port 0 is configured first as an input port by writing
1′s to it, and then data is received from the port and sent to P1.

MOV A,#0FFH ; A = FF hex

MOV P0,A ; make P0 an input
port BACK: MOV A,P0 ; get data from P0
MOV P1,A ; send it to port 1
SJMP BACK ; keep doing it

Fig 4.3: Port 0 with pull-up resistors

Dual role of port 0
Port 0 is also designated as AD0-AD7, allowing it to be used for both
address and data.
When connecting an 8051/31 to an external memory, port 0 provides both
address and data.
The 8051 multiplexes address and data through port 0 to save pins.
Port 1
Port 1 occupies a total of 8 pins (pins 1
through 8). It can be used as input or
output.
In contrast to port 0, this port does not need any pull-up resistors since it
already has pull-up resistors internally.
Upon reset, Port 1 is configured as an input port.

Example
The following code will continuously send out to port1 the alternating values
55H &
AAH
MOV A,#55H
BACK: MOV P1,A
ACALL
DELAY CPL A
SJMP BACK

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Port 1 as input
Port1 an input port, it must programmed as such by writing 1 to all its bits.

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In the following code port1 is configured first as an input port by writing
1‘s to it, then data is received from the port and saved in R7 ,R6 & R5.
MOV A,#0FFH ; A=FF HEX
MOV P1,A ; make P1 an input port by writing all
1‘s to it
MOV A,P1 ; get data from P1
MOV R7,A ; save it in register R7
ACALL DELAY ; wait
MOV A,P1 ; get another data from P1
MOV R6,A ; save it in register R6
ACALL DELAY ; wait
MOV A,P1 ; get another data from P1
MOV R5,A ; save it in register R5
Port 2
Port 2 occupies a total of 8 pins (pins
21- 28). It can be used as input or
output.
Just like P1, P2 does not need any pull-up resistors since it already has
pull-up resistors internally.
Upon reset, Port 2 is configured as an output port.
Example:

The following code will send out continuously to port 2 the alternating values 55h
and AAH. That is all the bits of port 2 toggle continuously.
MOV A,#55
H
BACK: MOV P2,A
ACALL DELAY
CPL A
SJMP BACK

Port 2 as input
To make port 2 an input, it must programmed as such by writing 1 to
all its bits. In the following code, port 2 is configured first as an input
port by writing 1‘s to it. Then data is received from that port and is
sent to P1 continuously.
Example:
MOV A,#0FFH ;A=FF hex
MOV P2,A ;make P2 an input port by writing all
1‘s to it BACK: MOV A,P2 ;get data
from P2
MOV P1,A ;send it to Port1
SJMP BACK ;keep doing that

Dual role of port 2

In systems based on the 8751, 8951, and DS5000, P2 is used as simple I/O.
in 8031-based systems, port 2 must be used along with P0 to provide
the 16-bit address for the external memory.
While P0 provides the lower 8 bits via A0-A7, it is the job of P2 to provide
bits A8-A15 of the address.
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In other words, when 8031 is connected to external memory.
P2 is used for the upper 8 bits of the 16 bit address, and it cannot be used for
I/O.

Port 3
Port 3 occupies a total of 8 pins, pins 10 through 17.

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It can be used as input or output. P3 does not need any pull-up resistors,
the same as P1 and P2 did not.
Although port 3 is configured as an output port upon reset.
Port 3 has the additional function of providing some extremely important
signals such as interrupts.
This information applies both 8051 and 8031 chips.

P3 BIT FUNCTION PIN

P3.0 RXD 10
P3.1 TXD 11
P3.2 INT0 12
P3.3 INT1 13
P3.4 T0 14
P3.5 T1 15
P3.6 WR 16
P3.7 RD 17

Table 4.3: Functions of port 3

P3.0 and P3.1 are used for the RxD and TxD serial communications
signals. Bits P3.2 and P3.3 are set aside for external interrupts.
Bits P3.4 and P3.5 are used for timers 0 and 1.
Finally P3.6 and P3.7 are used to provide the WR and RD signals of
external memories connected in 8031 based systems.

4.11 INSTRUCTION SET

Instruction Set of 8051 Microcontroller: -All instructions of 8051 can be divided in to Four
different groups, those are

1. Data Transfer Instructions

2. Arithmetic Instructions
3. Logical Instructions
4. Branching Instructions

1. Data Transfer Instructions: -Data transfer instructions are also called as Data
Movement Instructions or Data Copying Instructions. Data transfer instruction
execution doesn‘t effect on the Mathematical flags in PSW. In this group of
instructions the Xerox copy of data is transferred from source to destination,
because of this after execution of the instruction the content of source is equal
to the content of destination. In this microcontroller data transfer instruction
three types.

A. Move Related Instructions

B. Stack Related Instructions

C. Exchange Related Instructions

A. Move Related Instructions: - There are three types move related instructions.
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i. MOV ii. MOVX iii. MOVC

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i. MOV Instruction:-This instruction is used for onboard data transfers
in 8051 Microcontroller.

Ex: - MOV R1, #68H MOV A, #88H

MOV A, R0 MOV DPTR, #0896H

ii. MOVX Instruction: - This instruction is used for data transfers between
external RAM and Microcontroller through ‗A‘ register. This instruction only
supports Register Indirect Addressing Mode.

Ex: - MOVX A, @RP MOVX A, @DPTR

MOVX @RP, A MOVX @DPTR, A

iii. MOVC Instruction: - This instruction is used for data transfers between
internal or external ROM and the Microcontroller through ‗A‘ register. This
instruction only supports Indexed Addressing Mode it is one type of Register
Addressing Mode.

Ex: - MOVC A, @A+DPTR MOVC A, @A+PC

External Addressing Using MOVX and MOVC Instructions: -

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B. Stack Related Instructions: -There are two instructions are there in this
group. These instructions are used for data transfer between the internal RAM
and the specified Direct Address in the instruction. The internal RAM can be
used as Stack. The instructions are

i. PUSH ii. POP

i. PUSH Instruction: - This instruction is used for transferring the data from
specified Direct Address into Top of the Stack. For this instruction execution the
SP content is increment by
‗1‘. In this instruction execution the internal operations are performed in the following
order. It support only Direct Addressing Mode

1. SP content increment by ‗1‘

2. Specified Direct Address content is pushed on to SP specified location in the Stack.

Ex: - PUSH 76H

ii. POP Instruction: -This instruction is used for transferring the data from Top of
the Stack to specified Direct Address. For this instruction execution the SP
content is decrement by ‗1‘. In this instruction execution the internal operations
are performed in the following order. It supports only Indirect Addressing Mode.

1. SP specified location in the Stack content is copied to Specified Direct

Address in instruction.
2. SP content decrement

by ‗1‘ Ex: - POP 86H

C. Exchange Related Instructions: -In this group there are two instructions.
In these instructions one operand is accumulator register ‗A‘. These
instructions don‘t support Immediate Addressing Mode.

i. XCH ii. XCHD

i. XCH Instruction: - This instruction is used for data exchanging between

Accumulator register ‗A‘ and the specified other operand in the instruction.

Ex: - XCH A, R0 XCH A,

@R1 XCH A, 46H

ii. XCHD Instruction: -This instruction is used for Least Significant Nibbles data
exchanging between Accumulator register ‗A‘ and the specified other operand in
the instruction.

Ex: - XCHD A, R0 XCHD A,

@R1 XCHD A, 46H

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2. Arithmetic Instructions: -The microcontroller 8051 supports the following
arithmetic operations. If any arithmetic instruction is executed by controller
based on the result the mathematical flags are modified. For these arithmetic
instructions one operand must be the content of accumulator ‗A‘and after
completion of operation the result is stored in register ‗A‘.

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i. Addition ii. Subtraction iii. Multiplication iv. Division

v. Increment vi. Decrement vii. Decimal Adjust

i. Addition Instructions: -There are two instructions for to perform addition operation.
Those are

a. ADD b. ADDC

a. ADD Instruction: -This instruction is used to perform addition between

Accumulator and specified another operand in the instruction. It supports all
addressing modes.

Ex: - ADD A, R0 ADD A, #24H ADD A, @R0 ADD A, 68H

b. ADDC Instruction: -This instruction is used to perform addition between

Accumulatorspecified another operand in the instruction and previous
operation generated carry. It supports all addressing modes.

Ex: - ADDC A, R0 ADDC A, #24H

ADDC A, @R0 ADDC A, 68H

ii. Subtraction Instruction: -Only one instruction is there for performing the
subtraction operation. That is subtraction with borrow ‗SUBB‘. For this
Accumulator content is Minuend.

SUBB Instruction: -This instruction is used to perform subtraction between

Accumulatorspecified another operand in the instruction and previous operation
generated carry. It supports all addressing modes.

Ex: - SUBB A, R0 SUBB A,

#24H SUBB A, @R0 SUBB A, 68H

iii. Multiplication Instruction: -Only one instruction is there for performing the
Multiplication operation. This instruction syntax is fixed, and it support only two
8-bits numbers Multiplication.

MUL Instruction: - This instruction is used to perform Multiplication between ‗A‘

register and
‗B‘ register. The result of the Multiplication is stored in B & A registers. MSByte is
stored in
‗B‘ register and LSByte is stored in ‗A‘ register.

Ex: - MUL AB

iv. Division Instruction: -Only one instruction is there for performing the Division
operation. This instruction syntax is fixed, and it support only two 8-bits
numbers Division.

DIV Instruction: -- This instruction is used to perform Division between ‗A‘ register
and ‗B‘ register. The result of the Division is stored in A & B registers. Quotient is
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stored in ‗A‘ register and Remainder is stored in ‗B‘ register.

Ex: - DIV AB

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v. Increment Instruction: - Only one instruction is there for performing the
Increment operation. It supports all types of addressing modes except
Immediate addressing Mode. No mathematical flag is affected for this instruction
execution.

INC Instruction: -This instruction is used to increment the specified operand

content by ‗1‘. The operand may not an immediate data.

Ex: - INC R0 INC 70H INC @R0 INC DPTR INC A

vi. Decrement Instruction: -Only one instruction is there for performing the
decrement operation. It supports all types of addressing modes except
Immediate addressing Mode. No mathematical flag is affected for this instruction
execution.

DEC Instruction: -This instruction is used to decrement the specified operand content
by
‗1‘. The operand may not an immediate data.

Ex: - DEC R0 DEC 70H DEC @R0 DEC DPTRDEC A

vii. Decimal Adjust Instruction: -Only one instruction is there for performing the
decimal adjust operation. It supports only register addressing mode. For this
Instruction the operand is Accumulator register ‗A‘ only.

DA A Instruction: -This instruction is used to decimal adjust the accumulator

content, it means convert the binary content of register ‗A‘ into BCD form.

Ex: - DA A

3. Logical Instructions: -The 8051 support two types of logical operations

based on the size of applied data. Those are Byte level Logical Instructions
and Bit Level Logical Instructions. 8051 support the following logical
operations,

i. AND ii. OR iii. XOR iv. NOT

A. Byte level Logical Instructions: -

i. AND Instructions: -Only one instruction is there for performing the

logical AND operation.It supports all addressing modes.

ANL Instruction: - This instruction is used to perform Logical AND operation

between the source operand and destination operands. The destination
operand is either ‗A‘ register or an Address but the source is a register, or an
immediate data, or an address.

Ex: - ANL A, R0 ANL 70H, R1 ANL A, #80H ANL 76H, #74H ANL A, @R0

ii. OR Instruction: -Only one instruction is there for performing the logical OR
operation.It supports all addressing modes.

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ORL Instruction: - This instruction is used to perform Logical OR operation
between the source operand and destination operands. The destination
operand is either ‗A‘ register or an Address but the source is a register, or an
immediate data, or an address.

Ex: - ORL A, R0 ORL 70H, R1 ORL A, #80H ORL 76H, #74H ORL A, @R0

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iii. XOR Instruction: -Only one instruction is there for performing the
logical XOR operation.It supports all addressing modes.

XRL Instruction: - This instruction is used to perform Logical XOR operation

between the source operand and destination operands. The destination
operand is either ‗A‘ register or an Address but the source is a register, or an
immediate data, or an address.

Ex: - XRL A, R0 XRL 70H, R1 XRL A, #80H XRL 76H, #74H XRL A, @R0

iv. NOT Instruction: -Only one instruction is there for performing the logical NOT
operation. For this instruction the operand is Accumulator register ‗A‘.

CPL Instruction: - This instruction is used to complement the content of

Accumulator register.

Ex: - CPL A

Rotation Related Instructions: -All these instructions are designed based on the
‗A‘ register is an operand of the instruction, and all these instructions support
register addressing mode only.

RL Instruction: - This instruction is used to rotate the accumulator content bit by

bit to left side. MSbit is copied into LSbit and Carry flag position.

Ex: - RL A

RR Instruction: -This instruction is used to rotate the accumulator content bit by

bit to right side. LSbit is copied intoMSbit and Carry flag position.

Ex: - RR A

RLC Instruction: -This instruction is used to rotate the accumulator content bit by
bit to left side through Carry. MSbit is copiedto Carry flag position and Carry bit is
copied to LSbit position.

Ex: - RLC A

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RRC Instruction: -This instruction is used to rotate the accumulator content bit by
bit to right side through Carry. LSbit is copiedto Carry flag position and Carry bit
is copied to MSbit position.

Ex: - RRC A

SWAP Instruction: - This instruction is used to exchange the nibbles of

Accumulator register.

Ex: - SWAP A

B. Bit level Logical Instructions: -These instructions perform operations on any

Bit Addressable RAM or SFR bits. The Carry flag in the PSW can be used as
destination for maximum number of instructions.

We have bit related instructions for the operations like Logical AND, OR,
Complement, Clear, Set and Move.

AND Instructions: -

i. ANL C, b: - This instruction is used logical AND between Carry Flag (CY)
and the specified direct addressed bit in the instruction. Ex: - ANL C,
64H.

ii. ANL C, : -This instruction is used logical AND between Carry Flag (CY)
and the complement of specified direct addressed bit in the instruction.
Ex: - ANL C,

OR Instructions: -

i. ORL C, b -This instruction is used FOR logical OR between Carry Flag (CY)
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and the specified direct addressed bit in the instruction. Ex: - ORL C, 64H.

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ii. ORL C, : -This instruction is used logical OR between Carry Flag (CY)

and the complement of specified direct addressed bit in the instruction.

Ex: - ORL C,

Complement Instructions: -

i. CPL C : - This instruction is used to Complement the Carry flag content.

ii. CPL b : - This instruction is used to Complement the specified direct

addressed bit content.

Clear Instructions: -

i. CLR C : - This instruction is used to Clear the Carry flag content.

ii. CLRb -This instruction is used to Clear the specified direct addressed bit content.

Set Instructions: -

i. SETB C : - This instruction is used to Set the Carry flag content.

ii. SETB b: - This instruction is used to Set the specified direct addressed bit content.

Move Instructions: -

i. MOV C, bInstruction: - This instruction is used Move the content of the

specified direct addressed bit in the instruction to the Carry Flag (CY). Ex: -
MOV C, 64H.

i. MOV b, CInstruction: - This instruction is used Move the content ofthe Carry
Flag (CY) tothespecified direct addressed bit in the instruction. Ex: - MOV 64H,
C.

4. Branching Instructions: - These instructions are also called as Transfer of

control Instructions, or Program flow control instructions. By using these
instructions the program flow control is transferred from one location to
another location conditionally or unconditionally. Basically these are two
types of instructions

A. Unconditional Branching Instructions

B. Conditional Branching Instructions

A. Unconditional Branching Instructions: -These instructions are used to change

the program flow control from one location to another location without taking
any condition from the flags of PSW or Accumulator content. In this mainly
there are two types of instructions.

a. Jump Related Instructions,

b. Call and Return Related Instructions.

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a. Jump Related Instructions: -These instructions are used to change the
program execution from one location to another location
unconditionally.Inthis different instructions are available in 8051
Microcontroller instruction set. Those are

i. SJMP ii. AJMP iii. LJMP iv. JMP

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i. SJMP Instruction: -It is a Short Jump Instruction. By using this jump instruction
execution is moved to the previous locations or next locations. The destination
must be in the range - 128 to +127 from the current instruction. For this
instruction the operand is an 8-bit relative address. The operand address is
added to or subtracted from the current content of PC. This instruction is also
used as termination instruction in 8051 programs.

Ex: - SJMP 8-bit Relative address

ii. AJMP Instruction: -It is anAbsolute Jump Instruction. By using this jump
instruction execution is moved to only next locations. The destination must be
within 2K locations from the current instruction. For this instruction the operand
is an 11-bit address. The operand address is added to the current content of
PC.

Ex: - AJMP 11-bit address

iii. LJMP Instruction: -It is a Long Jump Instruction. By using this jump instruction
execution is moved to only next locations. The destination is any location in the
64K locations of the memory. For this instruction the operand is a 16-bit address.
The operand address is added to the current content of PC.

Ex: - LJMP 16-bit address

iv. JMP Instruction: -It is a simple Jump Instruction. By using this jump instruction
execution is moved to the location address is provided by the combination of ‗A‘
register and DPTR register.

Ex: - JMP @A + DPTR

b. Call and Return Related Instructions: - By using the Call and Return
instructions the subprogram is called into the main program. Call instruction is
used to change the program execution from the main program to subprogram,
and by using Ret instruction the program execution is shifted from the
subprogram to the main program. There are two Call related instructions, those
are

i. ACALL ii. LCALL

i. ACALL Instruction: -By using this instruction to call a subprogram into the main
program. But the subprogram must be within the 2K locations. In another way
the subprogram and the main program must be in the same page and the page
size is 2KB.

Ex: - ACALL 11-bit address

ii. LCALL Instruction: -By using this instruction to call a subprogram into the main
program. The subprogram is in any location in the 64K locations. Ex: - LCALL 16-
bit address

There are two Return Related Instructions, those are

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i. RET ii. RETI

i. RET Instruction: -By using this instruction the program execution is shift
from the subprogram to the main program, and this instruction is used as
last instruction in the subprogram. This instruction is comes under implicit
addressing mode. Ex: - RET

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ii. RETI Instruction: -By using this instruction the program execution is shift
from theInterrupt Service Routine (ISR) to the main program, and this
instruction is used as last instruction in the ISR. This instruction also comes
under implicit addressing mode.

Ex: - RETI

B. Conditional Branching Instructions: -These instructions are used to change

the program flow control from one location to another location with taking
condition from the flags of PSW or Accumulator content. All Conditional Jump
instructions are Relative Jump instructions or Short Jump Instructions. In this
mainly there are three types of instructions.

a. Conditional Jump Instructions

b. Comparison Related Instructions

c. Decrement Related Instructions

a. Conditional Jump Instructions: -These Instructions are designed based

on the conditions of Carry flag in the PSW, Accumulator content and the
specified bit.

i. JC Instruction: -By using this instruction the program execution is shift from
one location to other location only if the CY = ‗1‘. Otherwise the instruction is
ignored.

Ex: - JC 8-bit rel add

ii. JNC Instruction: -By using this instruction the program execution is shift
from one location to other location only if the CY = ‗0‘. Otherwise the
instruction is ignored.

Ex: - JNC 8-bit rel add

iii. JZ Instruction: -By using this instruction the program execution is shift from
one location to other location only if the Accumulator (A) content = ‗0‘.
Otherwise the instruction is ignored.

Ex: - JZ 8-bit rel add

iv. JNZ Instruction: -By using this instruction the program execution is shift
from one location to other location only if the Accumulator (A) content not
equal to‗0‘. Otherwise the instruction is ignored. Ex: - JNZ 8-bit rel add

v. JB instruction: -By using this instruction the program execution is shift from
one location to other location only if the Specified bit = ‗1‘. Otherwise the
instruction is ignored.

Ex: - JB b, 8-bit rel add where ‗b‘ indicates the Direct Address of the Bit.

vi. JNB instruction: -By using this instruction the program execution is shift
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from one location to other location only if the Specified bit = ‗0‘. Otherwise
the instruction is ignored.

Ex: - JNB b, 8-bit rel add where ‗b‘ indicates the Direct Address of the Bit.

vii. JBC instruction: -By using this instruction the program execution is shift
from one location to other location only if the Specified bit = ‗1‘, and clear that
bit also. Otherwise the instruction is ignored.

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Ex: - JBC b, 8-bit rel add where ‗b‘ indicates the Direct Address of the Bit.

b. Comparison Related Instruction: -This instruction are used compare the

accumulator content with any memory location content or an immediate data
or a memory location content is compare with an immediate data or any GPR
content is compare with an immediate data. After comparison if both operands
are not equal then jump to the specified relative address. Only this instruction
has three operand fields.

Ex: -CJNE A, #70H, CJNE A, 80H, CJNE Rn, #78H, CJNE @Ri, #32H

Where Rn = any GPR (R0 to R7) and Ri = either R0 or R1

c. Decrement Related Instructions: -This instruction is used to Decrement the

specified GPR content or the Direct Address content by ‗1‘ and that is not
equal to zero then jump to the specified relative address.

Ex: - DJNZ R0, 8-bit rel add, DJNZ 64H, 8-bit rel add

An instruction set is a group of commands for a CPU in machine language.

The term can refer to all possible instructions for a CPU or a subset of
instructions to enhance its performance in certain situations.

Arithmetic instructions
Arithmetic instructions perform several basic operations such as
addition, subtraction, division, multiplication etc.
After execution, the result is stored in the first operand. Some of the
Instructions are
Arithmetic Instructions
Mnemonic Description Byte Cycle
ADD A,Rn Adds the register to the accumulator 1 1
ADD A,direct Adds the direct byte to the accumulator 2 2
ADD A,@Ri Adds the indirect RAM to the 1 2
accumulator
ADD A,#data Adds the immediate data to the 2 2
accumulator
Adds the register to the accumulator
ADDC A,Rn 1 1
with a carry flag
Adds the direct byte to the
ADDC A,direct 2 2
accumulator with a carry flag
Adds the immediate data to the
ADDC A,#data 2 2
accumulator with a carry flag
Subtracts the register from the
SUBB A,Rn 1 1
accumulator with a borrow
Subtracts the direct byte from
SUBB A,direct 2 2
the accumulator with a
borrow

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Subtracts the indirect RAM from
SUBB A,@Ri 1 2
the accumulator with a
borrow
INC A Increments the accumulator by 1 1 1
INC Rn Increments the register by 1 1 2

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INC Rx Increments the direct byte by 1 2 3
INC @Ri Increments the indirect RAM by 1 1 3
DEC A Decrements the accumulator by 1 1 1
DEC Rn Decrements the register by 1 1 1
DEC Rx Decrements the direct byte by 1 1 2
INC DPTR Increments the Data Pointer by 1 1 3
MUL AB Multiplies A and B 1 5
DIV AB Divides A by B 1 5

Table 4.4: Arithmetic instructions

Branch Instructions
There are two kinds of branch instructions:

Unconditional jump instructions: upon their execution a jump to a new

location from where the program continues execution is executed.

Conditional jump instructions: a jump to a new program location is

executed only if a specified condition is met. Otherwise, the
program normally proceeds with the next instruction.
Some of the instructions are

Branch Instructions
Mnemonic Description Byte Cycle
ACALL addr11 Absolute subroutine call 2 6
LCALL addr16 Long subroutine call 3 6
RET Returns from subroutine 1 4
RETI Returns from interrupt 1 4
subroutine
AJMP addr11 Absolute jump 2 3
LJMP addr16 Long jump 3 4
Short jump (from –128 to +127
SJMP rel locations relative to the 2 3
following instruction)
JC rel Jump if carry flag is set. Short 2 3
jump.
Jump if carry flag is not set.
JNC rel 2 3
Short jump.
JB bit,rel Jump if direct bit is set. Short 3 4
jump.
Jump if direct bit is set and clears
JBC bit,rel 3 4
bit. Short jump.
Jump if the accumulator is
JZ rel 2 3
zero. Short jump.
Jump if the accumulator is not
JNZ rel 2 3
zero. Short jump.
Compares direct byte to the
CJNE
accumulator and jumps if not 3 4

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Compares immediate data to
CJNE
the accumulator and jumps if 3 4
A,#data,rel
not equal. Short jump.
Compares immediate data to
CJNE
the register and jumps if not 3 4
Rn,#data,rel
equal. Short jump.
Compares immediate data to
CJNE
indirect register and jumps if 3 4
@Ri,#data,rel
not equal. Short jump.
Decrements register and jumps if
DJNZ Rn,rel 2 3
not
0. Short jump.
Decrements direct byte and
DJNZ Rx,rel 3 4
jump if not 0. Short jump.
NOP No operation 1 1

Table 4.5: Branch Instructions

Data Transfer Instructions

Data transfer instructions move the content of one register to
another. The register the content of which is moved remains
unchanged.
If they have the suffix ―X‖ (MOVX), the data is exchanged with
Data Transfer Instructions
external memory. Some of the instructions are
Mnemonic Description Byte Cycle
MOV A,Rn Moves the register to the 1 1
accumulator
MOV A,direct Moves the direct byte to the 2 2
accumulator
Moves the indirect RAM to the
MOV A,@Ri 1 2
accumulator
Moves the immediate data to the
MOV A,#data 2 2
accumulator
MOV Rn,A Moves the accumulator to the 1 2
register
MOV Rn,direct Moves the direct byte to the register 2 4
Moves the immediate data to the
MOV Rn,#data 2 2
register
MOV direct,A Moves the accumulator to the direct 2 3
byte
MOV direct,Rn Moves the register to the direct byte 2 3
MOV
Moves the direct byte to the direct 3 4
direct,direct
byte
MOV Moves the indirect RAM to the
2 4
direct,@Ri direct byte
MOV Moves the immediate data to the
3 3
direct,#data direct byte
Moves the accumulator to the
MOV @Ri,A 1 3

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@Ri,direct RAM
MOV Moves the immediate data to the
2 3
@Ri,#data indirect RAM
MOV
Moves a 16-bit data to the data 3 3
DPTR,#data
pointer
Moves the code byte relative to
MOVC
the DPTR to the accumulator 1 3
A,@A+DPTR
(address=A+DPTR)
MOVC Moves the code byte relative to
1 3
A,@A+P the PC to the accumulator
C (address=A+PC)
Moves the external RAM (8-bit
MOVX A,@Ri 1 3-10
address) to the accumulator
MOVX Moves the external RAM (16-bit
1 3-10
A,@DPTR address) to the accumulator
Moves the accumulator to the
MOVX @Ri,A 1 4-11
external RAM (8-bit address)
MOVX Moves the accumulator to the
1 4-11
@DPTR,A external RAM (16-bit address)
PUSH direct Pushes the direct byte onto the 2 4
stack
POP direct Pops the direct byte from the 2 3
stack/td>
Exchanges the register with the
XCH A,Rn 1 2
accumulator
Exchanges the direct byte with the
XCH A,direct 2 3
accumulator
Exchanges the indirect RAM with
XCH A,@Ri 1 3
the accumulator
Exchanges the low-order nibble
XCHD A,@Ri 1 3
indirect RAM with the accumulator
Table 4.6: Data Transfer Instructions
Logic Instructions
Logic instructions perform logic operations upon corresponding bits of two
registers.
After execution, the result is stored in the first operand. Some of the instructions
are

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Logic Instructions
Mnemonic Description Byte Cycle
ANL A,Rn AND register to accumulator 1 1
ANL A,direct AND direct byte to 2 2
accumulator
ANL A,@Ri AND indirect RAM to 1 2
accumulator
AND immediate data
ANL A,#data 2 2
to accumulator
ANL direct,A AND accumulator to direct 2 3
byte
AND immediae data to
ANL direct,#data 3 4
direct register
ORL A,Rn OR register to accumulator 1 1
ORL A,@Ri OR indirect RAM to 1 2
accumulator
ORL direct,A OR accumulator to direct byte 2 3
ORL direct,#data OR immediate data to direct 3 4
byte
Exclusive OR register
XRL A,Rn 1 1
to accumulator
Exclusive OR direct byte
XRL A,direct 2 2
to accumulator
Exclusive OR indirect RAM
XRL A,@Ri 1 2
to accumulator
Exclusive OR immediate data
XRL A,#data 2 2
to accumulator
Exclusive OR accumulator
XRL direct,A 2 3
to direct byte
Exclusive OR immediate data
XORL 3 4
to direct byte
direct,#data
CLR A Clears the accumulator 1 1
Complements the
CPL A 1 1
accumulator
(1=0, 0=1)
Swaps nibbles within
SWAP A 1 1
the accumulator
Rotates bits in the
RL A 1 1
accumulator left
Rotates bits in the
RLC A 1 1
accumulator left through carry
Rotates bits in the
RR A 1 1
accumulator right
Rotates bits in the
RRC A 1 1
accumulator right through
carry
Table 4.7: Logic Instructions
Bit-oriented Instructions
Similar to logic instructions, bit-oriented instructions perform logic
operations.
The difference is that these are performed upon single bits. Some of the
instructions are

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Bit-oriented Instructions
Mnemonic Description Byte Cycle
CLR C Clears the carry flag 1 1
CLR bit Clears the direct bit 2 3
SETB C Sets the carry flag 1 1
SETB bit Sets the direct bit 2 3
CPL C Complements the carry flag 1 1
CPL bit Complements the direct bit 2 3
ANL C,bit AND direct bit to the carry flag 2 2
ANL C,/bit AND complements of direct bit to the 2 2
carry flag
ORL C,bit OR direct bit to the carry flag 2 2
ORL C,/bit OR complements of direct bit to the carry 2 2
flag
MOV C,bit Moves the direct bit to the carry flag 2 2
MOV bit,C Moves the carry flag to the direct bit 2 3

Table 4.8: Bit-oriented Instructions

4.11 ASSEMBLY LANGUAGE PROGRAMMING.

1. Writ an 8051 ALP to save the status of bits P1.1 and P1.2 on RAM bit locations
08H and 09H respectively.
MOV C, P1.1
MOV 08H, C
MOV C, P1.2
MOV 09H, C
UP: SJMP UP

2. Writ an 8051 ALP to find the sum of values 79H, 0F5H, and 0E2H. Put the sum
in register R0 (Lower order Byte) and R1 (Higher order Byte).
MOV A, 00H
MOV R1, A
MOV R0, A
ADD A, #79H
JNC NEXT1
INC R1
NEXT1: ADD A, #0F5H
JNC NEXT 2
INC R1
NEXT 2: ADD A, #0E2H
JNC NEXT3
INC R1
NEXT 3: MOV R0, A
HERE: SJMP HERE

3. Writ an 8051 ALP to add ‘2’ to the accumulator by 600H times.

MOV A, #77H
MOV R2,
#10H
NEXT: MOV R3,
#60H AGAIN: ADD
A, #02H DJNZ R3,
AGAIN DJNZ R2,
NEXT STOP: SJMP
STOP

4. Writ an 8051 ALP to toggle all the bits of Port 1 by sending to it the values 66H
and 0BBH continuously. Put a delay in between each issuing of data to port.
UP: MOV A, #66H
MOV P1, A
LCALL DELAY
MOV A,
#0BBH MOV
P1, A LCALL
DELAY SJMP
UP
241
DELAY: MOV R3,
#0FFH AGAIN: DJNZ
R3, AGAIN RET

5. Writ an 8051 ALP to find the number of 1’s in a 0FFH.

MOV R2, #00H
MOV R3, #08H
MOV A, #0FFH
REPEAT: RLC A
JNC NEXT
INC R2
NEXT: DJNZ R3, REPEAT
HERE: SJMP HERE

6. Writ an 8051 ALP to find the Largest / Maximum number in the array.
MOV DPTR,
#3000H MOVX A,
@DPTR MOV R0,
#‘N‘
L1: MOV B, A
L3: DJNZ R0,
L2 SJMP
DOWN L2: INC
DPTR
MOVX A, @DPTR
CJNE A, B, UP
SJMP L3
UP: JC L3
SJMP L1
DOWN: MOV R1, B

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Part-A (2 Marks Questions and Answers)

1. What is mean by microcontroller?

A device which contains the microprocessor with integrated peripherals
like memory, serial ports, parallel ports, timer/counter, interrupt controller, data
acquisition interfaces like ADC,DAC is called microcontroller.

2. Explain DJNZ instructions of Intel 8051 microcontroller?

a) DJNZ Rn, rel : Decrement the content of the register Rn and jump if not zero.
b) DJNZ direct , rel :Decrement the content o f direct 8-bit address and jump if not
zero.

3. State the function of RS1 and RS0 bits in the flag register of Intel 8051
microcontroller? (May 2013)
RS1 , RS0 – Register bank select bits
RS1 RS0 Bank
Selection
0 0 Bank 1
0 1 Bank 2
1 0 Bank 3
1 1 Bank 4
4. Explain the function of the pins PSEN and EA of
8051 PSEN: PSEN stands for program store enable.
In 8051 based system in which an external ROM holds the program code, this pin
is connected to the OE pin of the ROM.
EA : EA stands for external access.
When the EA pin is connected to Vcc, program fetched to addresses 0000H
through 0FFFH are directed to the internal ROM and program fetches to
addresses 1000H through FFFFH are Directed to external ROM/EPROM. When
the EA pin is grounded, all addresses fetched by program are directed to the
external ROM/EPROM.

5. Explain the 16-bit registers DPTR and SP of 8051.

DPTR:
DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a blow b
yte (DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-
bit data register or as two independent 8-bit registers. It serves as a base b
register in indirect jumps, lookup table instructions and external data transfer.
SP:
SP stands for stack pointer. SP is a 8- bit wide register. It is incremented before
data is stored during PUSH and CALL instructions. The stack array can reside
anywhere in on-chip RAM. The stack pointer is initialized to 07H after a reset.
This causes the stack to begin at location

6. Name the special functions registers available in 8051.

• Accumulator
• B Register
• Program Status Word.
• Stack Pointer.
• Data Pointer.
• Port 0
• Port 1
• Port 2

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7. Name the five interrupt sources of 8051?(Nov/Dec 2010)
The interrupts are:
1) Vector address
2) External interrupt 0

244
3) Timer interrupts 0
4) External interrupt 1
5) Timer Interrupt 1
6) Serial Interrupt
7) Receive interrupt:
8) Transmit interrupt:

8. Compare Microprocessor and Microcontroller.

1. Microprocessor: It contains the circuitry ALU, general purpose of
microprocessor and Microcontroller registers, stack pointer, has built- in ROM,
RAM, I/O program counter, clock timing devices, timers and counters. Circuit and
interrupt circuit.
2. Microprocessor It has man y instructions to It has one or two instructions to
move data between memory data between memory and CPU.
Microcontroller It has one or two bit handling. It has man y bit handling instructions.
3. Microprocessor Access times for memory and I/O devices
are more. Microcontroller Less access times for built-in
memory and I/O devices. 4 .Microprocessor based system
requires more hardware
Microcontroller based system requires less hardware reducing PCB size and
increasing the reliability.

9. What is the size of the on-chip program memory and on-chip data memory of 8051
microcontroller? (May /June 2012)
• 4 kb on chip program memory
• 128 bytes on chip data memory

10. List some of the features of 8096 microcontroller.

1) The 8096 is a 16-bit microcontroller.
2) The 8096 is designed to use in applications which require high speed
calculations and fast I/O operations.
3) The high speed I/O section of an 8096 includes a 16-bit timer, a 16-bit
counter, a 4 input programmable edge detector, 4 software timers and a 6-
output programmable event generator. It has 100 instructions, which can
operate on bit, byte, word, and double words.
4) The bit operations are possible and these can be performed on an y bit in the
register file or in the special function register.

11. What are the addressing modes supported by 8051?(ECE M/J 2009)
• Immediate addressing mode.
• Register addressing mode.
• Direct addressing mode.
• Indirect addressing mode.
• Indexed addressing mode

18. List the applications of microcontroller. [MAY/JUNE 2009]

Stepper motor
interfacing Length
measurement Square
wave generator

19. Give the alternate functions for the port pins of port3?
• RD – Read data control output.
• WR – Write data control output.
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• T1 – Timer / Counter1 external input or test pin.
• T0 – Timer / Counter0 external input or test pin.
• INT1- Interrupt 1 input pin.
• INT 0 – Interrupt 0 input pin.

246
• TXD – Transmit data pin for serial port in UART mode.

20. Define XTAL1 and XTAL2. [MAY/JUNE 2009]

In built oscillator which derives the necessary clock frequency for the operation
of the controller. XTAL1 is the input of amplifier and XTAL2 is the output of the
amplifier.

21. What are the advantages of microcontroller over microprocessor?

The overall system cost is low, as the peripherals are integrated in a single chip.
Size is small. Easy to troubleshoot and maintain. System is more reliable

22. Give the various modes of 8254 timer?

• Mode 0: interrupt or terminal count
• Mode 1: Rate generator
• Mode 3: square wave generator
• Mode 4: software triggered strobe
• Mode 5: hardware triggered strobe

23. What are the functions of the following signals of 8051? ALE/PROG, PSEN.
(Nov/Dec 2010)
ALE:The ALE (Address latch enable) is used to latch the lower order address so
that it can be available in T2 and T3 and used for identifying the memory
address. During T1 the ALE goes high. When ALE goes low the lower order
address is latched until the next ALE.
PSEN: PSEN stands for program store enable. In 8051 based system in which an
external ROM holds the program code, this pin is connected to the OE pin of the
ROM.

24. What are the difference between microprocessor and microcontroller? (Nov/Dec
2011)
Microprocessor Microcontroller
Microprocessor contains ALU, Microcontroller contains the
general purpose registers, stack circuitry of microprocessor and in
pointer, program counter, clock addition it has built- in ROM, RAM,
timing circuit and interrupt circuit. I/O devices, timers and counters.
It has many instructions to move It has one or two instructions to
data between memory and CPU move data between memory and
CPU.
It has one or two bit It has many bit handling
handling instructions.
Instructions
4 Access times for memory and Less access times for built-in
I/O devices are more. memory and I/O devices
Microprocessor based system Microcontroller based system
requires more hardware. requires less hardware reducing
PCB size and
Increasing the reliability.

25. What are the advantages of using a microcontroller in a place of a

microprocessor? (May/June 2012)
The overall system cost is low, as the peripherals are integrated in a single chip.
247
Size is small.
Easy to troubleshoot and maintain.
System is more reliable.

248
Part-B (16 Marks Questions)
1. Bring out the features of special function registers of 8051 microcontroller.
(Ref Sec 4.7) (Nov/Dec 2010)
2. Draw the pin diagram of 8051 microcontroller and explain the functions of each
pin.
(Ref Sec 4.7 ) (Nov/Dec 2011)
3. With a neat sketch of a schematic diagram, explain the functions of
various signals of 8051(Ref Sec4) (Nov/Dec 2010)
4. Discuss briefly the various registers in 8051 microcontroller.(Ref
Sec 4.8) (Nov/Dec 2011,Apr/May 2011)
5. Draw the architectural block diagram of 8051 microcontroller and explain.
(Ref Sec 4.5) (May/June 2012)
6. Explain the internal data memory structure of 8051 microcontroller with its
SFRs
(Ref Sec 4.6) (May/June 2012)
7. Draw the diagram of 8051 microcontroller and explain the input/output lines in
detail
(Ref Sec 4.10) (May/June 2014)
8. Explain instruction sets of 8051. (.Ref Sec 4.11) (May/June 2014)

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