8051

Microcontroller Architecture
(Embedded System)

Dr. Basudeba Behera

Assistant Professor

Department of Electronics and Communication Engineering

National Institute of Technology Jamshedpur, Jharkhand, India
Overview

• Introduction to 8051
• Microprocessor Vs Microcontroller
• The Architecture of 8051
• Pin Configuration of 8051
•Memory Configuration

2
Introduction
• Microcontroller are single chip microcomputers
• Consists of Central processing Unit
• Memory
• I/O ports
• Timers and counters
• Analog-to-Digital converter (ADC)
• Digital-to-Analog converter (DAC)
• Serial Port, Interrupt Logic
• Oscillatory circuitry and many more functional blocks on chip

3
Difference
MICRO PROCESSER MICRO CONTROLLER
• It is a CPU • It is a single chip
• Memory, I/O Ports to be connected externally • Consists Memory, I/o ports

4
Difference

5
8051 Basic Component
} 4K bytes internal ROM
} 128 bytes internal RAM
} Four 8-bit I/O ports (P0 - P3).
} Two 16-bit timers/counters
} One serial interface
} 8 bit cpu
A single chip
} 64k Program memory (4k on chip)
} 64k Data memory
} 32 I/O
} Full duplex UART
} 6 Source/5 Vector interrupts with
} two level priority levels- On chip clock Oscillator. CPU RAM ROM
Microcontroller
I/O Serial
Timer COM
Port
Port 6
Block Diagram

External Interrupts

Interrupt 4k 128 bytes Timer 1 Counter I/P

Control ROM RAM Timer 2

CPU

OSC Bus
4 I/O Ports Serial
Control

PSEN ALE P0 P2 P1 P3 TXD RXD

Addr/Data

7
Other 8051 featurs

} only 1 On chip oscillator (external crystal)

} 6 interrupt sources (2 external , 3 internal, Reset)
} 64K external code (program) memory(only read) PSEN
} 64K external data memory(can be read and write) by RD, WR
} Code memory is selectable by EA (internal or external)
} We may have External memory as data and code

8
Embedded System
(8051 Application)

• What is Embedded System?

– An embedded system is closely
integrated with the main system
– It may not interact directly with the
environment
– For example – A microcomputer in a car
ignition control

v An embedded product uses a microprocessor or microcontroller to do one task only

v There is only one application software that is typically burned into ROM

9
Examples of Embedded Systems

• Keyboard
• Printer
• video game player
• MP3 music players
• Embedded memories to keep configuration
information
• Mobile phone units
• Domestic (home) appliances
• Data switches
• Automotive controls

10
Three criteria in Choosing a
Microcontroller
• meeting the computing needs of the task efficiently and cost effectively
– speed, the amount of ROM and RAM, the number of I/O ports and timers, size,
packaging, power consumption
– easy to upgrade
– cost per unit
• availability of software development tools
– assemblers, debuggers, C compilers, emulator, simulator, technical support
• wide availability and reliable sources of the microcontrollers

11
Comparison of the 8051 Family Members
} ROM type
◦ 8031 no ROM
◦ 80xx mask ROM
◦ 87xx EPROM
◦ 89xx Flash EEPROM
} 89xx
◦ 8951
◦ 8952
◦ 8953
◦ 8955
◦ 898252
◦ 891051
◦ 892051
} Example (AT89C51,AT89LV51,AT89S51)
◦ AT= ATMEL(Manufacture)
◦ C = CMOS technology
12
◦ LV= Low Power(3.0v)
Comparison of the 8051 Family Members

89XX ROM RAM Timer Int IO pin Other

Source
8951 4k 128 2 6 32 -

8952 8k 256 3 8 32 -

8953 12k 256 3 9 32 WD

8955 20k 256 3 8 32 WD

898252 8k 256 3 9 32 ISP

891051 1k 64 1 3 16 AC

892051 2k 128 2 6 16 AC

WD: Watch Dog Timer

AC: Analog Comparator
ISP: In System Programable
13
8051 Internal Block Diagram

14
8051 Architecture
} ALU
◦ Performs Arithmetic and logical operation on 8-bit operand.
◦ It also performs multiplication and subtraction operation
◦ Each logical operation involves AND, OR, NOT, XOR
} Boolean Processor
◦ It has own instruction set , accumulator and bit addressable RAM
◦ Carry flag serves as accumulator
◦ Instructions allow complement bit, set bit, and clear bit
◦ Conditional branch like jump if bit set etc
◦ Logical bit wise AND,OR
◦ The result of bitwise logical operation are stored into the carry bit, which works as an
accumulator

15
8051 Architecture
} Program and Data Memory
◦ There are two separate Program and Data Memories
◦ Code is stored in ROM/EPROM
◦ 8051 is having 4K ROM while 8052 is 8K ROM
◦ Data memory can be internal RAM and off-chip external data RAM
◦ Some internal on-chip RAM locations are also used for controlling the operations of the
peripherals such as timers/counters, serial port, interrupts. etc. called as special function
registers (SFRs)
◦ To access off-chip data RAM, 16-bit address is used.
◦ The address (Port 0) and address-data (Port 2) buses holds this address
◦ Lower order byte of the address – data bus is time multiplexed
◦ Multiplexing reduces pin counts also reduces speed of the memory

16
8051 Architecture
} The Oscillator
◦ It uses an external crystal for oscillator function
◦ 8051 operates at a 12 MHz frequency
◦ The baud rate is the rate at which information is transferred in a communication
channel.
◦ In the serial port context, "9600 baud" means that the serial port is capable of
transferring a maximum of 9600 bits per second
◦ It is necessary to connect the quartz crystal externally and all other oscillator circuit is
on-chip
} Timing and Control
◦ The whole operation of 8051 is synchronous with clock
◦ Apart from the internal timings, there are control signals ALE, PSEN, and RD, WR are
generated by timing and control unit, for accessing the off-chip devices.

17
8051 CPU Registers

qA (Accumulator)
qB (Used in assembler instructions)
qPSW (Program Status Word)
qSP (Stack Pointer)
qPC (Program Counter)
qDPTR (Data Pointer)

18
8051 Registers
} There are general purpose or working registers, Stack Pointer, Program counter and in
addition to these CPU registers, and SFRs.
} Accumulator
◦ 8-bit accumulator
◦ Accumulator is used by all ALU instructions
◦ Access to accumulator is faster than access to main memory
◦ Accumulator has direct path to ALU and can immediately store the intermediate result of operation
} B- register
◦ 8-bit register
◦ It is available as general purpose register when it is not used by multiplication or division operation.
◦ While Multiplying, It holds one of the 8-bit operands
◦ And after the execution of the multiplication operation, it stores higher byte of the result.
◦ While division, It holds as 8-bit divisor
◦ And after the execution of division instruction, the reminder is stored in B-register
19
8051 Registers
} Register R0 through R7
◦ These 8 registers are used as scratch pad registers (high-speed internal memory used for temporary
storage of calculations, data, and other work in progress) .
◦ There are 4-register banks containing R0 through R7 registers.
◦ Each of these registers are 8-bit wide.
◦ At a time only one bank can be selected by appropriate setting of bits in the program status word (PSW).
◦ These are located in the on-chip RAM
◦ Certain instructions can access these registers in RAM directly.
◦ Power-up-reset causes bank 0 to be selected by default.
◦ If a byte is written in R4 then it would stored at RAM location 04H.
◦ If in another case, the programmer is selecting bank 1 and writing a byte in R4, it will store the byte at
RAM location 0CH.

20
8051 Registers

21
8051 Registers
Ø Stack Pointer
◦ SP is 8-bit wide.
◦ It is incremented during push or call operations
◦ It is decremented during pop or return operation.
◦ After RESET operation, the stack pointer in initialized to 07H, causing the stack to begin at 08H.
Ø Program Counter
◦ Instruction opcode bytes are fetched from the program memory locations addressed by the program
counter.
◦ PC in 16-bit wide, and it can address 64K code byte.
◦ PC always points to the instruction to be fetched and is automatically incremented after fetching the
instruction.
◦ PC is affected by call and jump instruction.
◦ Only PC has no on-chip RAM address.

22
8051 Registers
} Special Function Registers (SFR)
◦ The 128 bytes of on-chip additional RAM location from 80H to 0FFH are reserved for the special function
and therefore these are called as SFR.
◦ These SFRs are used for control or to show the status of various function done by 8051 microcontroller.
◦ All SFRs are directly addressable and can be read or written to as well.
◦ SFR space is only reserved for the special functions and cannot be used for any other purpose.
◦ Some SFRs are bit addressable and allow their individual bits to be set or cleared by instructions.
Example
◦ One can set the port 1 bit P1.1 using an instruction
SETB P1.0
◦ One can clear the port 1 bit P1.1 using an instruction
CLR P1.0
◦ The address of P1.1 is 91H.
◦ Port 1 has 90H as its byte address and it is byte addressable too.
◦ By writing a byte to address 90H, all the 8-bit of Port 1 can be changed in on stroke
23
8051 Special Function Registers

24
25
8051 Registers
} Program status word
◦ PSW is 8-bit wide.
◦ It consists of carry, auxiliary carry, overflow, and parity flags
◦ There are bits RS1 and RS0 for register bank selection
◦ PSW is bit addressable register
◦ Each PSW bit a is reffered as PSW.X
◦ PSW.0 is LSB, which is parity flag
◦ And MSB PSW.7 is carry flag.

26
8051 Registers
} Carry Flag (PSW.7)
◦ Carry flag is set when a carry is generated out of 7th bit of result.
Example
11000010 B (0C2H)
+
10101010 B (0AAH)
101101100 B (6CH)
} Auxiliary Carry Flag (PSW.6)
◦ Auxiliary Carry flag is set when a carry is generated out of 3rd bit, during an operation.
} F0 (PSW.5)
◦ F0 will be available to user as general purpose flag.
◦ This can be set/Reset by Flag.

27
8051 Registers
} Register bank select bits RS1 and RS0 (PSW.4 and PSW.3)
◦ These are bits for selecting one of the four register banks.

} Overflow Flag (PSW.2)

◦ Overflow flag is set as a result of an arithmetic operation, provided there is a carry out of bit 6, but not
out of bit 7 or a carry out of bit 7 but not out of bit 6.
} Parity Flag (PSW.0)
◦ This indicates the number of 1 s in accumulator.
◦ If there are odd number of 1s this will be set.
◦ If even number of 1s then it will be cleared.

28
8051 Registers
} Data Pointer (DPTR)
◦ DPTR is 16-bit register of two bytes.
◦ Higher bytes is DPH and lower is DPL.
◦ The DPTR is used for addressing the off-chip data and code with the MOVX and MOVC command.
◦ With 16-bit pointer DPTR , a maximum of 64K of off-chip data memory and maximum of 64K of off-chip
program memory can be addressed.
} Timer Registers
◦ Register pairs (TH0, TL0) (TH1, TL1) (TH2, TL2) form 16-bit timer/counter registers 0,1,2, respectively.
◦ The operation may be timing or counting.
} Port 0 to 3
◦ P0, P1, P2, P3 are the SFRs corresponding to four I/O ports.
◦ Each of these ports are bit/byte addressable.

29
8051 Registers
} Control Registers
◦ TCON, TMOD, IE, IP, SCON, PCON contain the control and
status for interrupts, serial I/O and timer/counters.
} Capture Registers
◦ Register pairs (RCAP2H-RCAP2L) are the capture
registers for the timer 2.
◦ In capture mode , a transition at the 8052 T2EX pin
causes TH2 and TL@ to be copied into RCAP2H and
RCAP2L .

Addresses 80h – FFh

Direct Addressing used to access SPRs

30
8051 Pin Configuration

P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0)
P1.2 3 38 P0.1(AD1)
P1.3 4 37 P0.2(AD2)
P1.4 5 36 P0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 8051 31
EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29
PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14)
(T1)P3.5 15 26 P2.5(A13)
(WR)P3.6 16 25 P2.4(A12)
(RD)P3.7 17 24 P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)

31
8051 Schematic Pin out 8051 Foot Print
Important Pins

} PSEN (out): Program Store Enable, the read signal for external program memory (active low).

} ALE (out): Address Latch Enable, to latch address outputs at Port0 and Port2

} EA (in): External Access Enable, active low to access external program memory locations 0 to 4K

} RXD,TXD: UART (Universal Asynchronous Receiver/Transmitter) pins for serial I/O on Port 3

} XTAL1 & XTAL2: Crystal inputs for internal oscillator.

32
Pins of 8051
} Vcc（pin 40）：
◦ Vcc provides supply voltage to the chip.
◦ The voltage source is +5V.
◦ Power supply current for 8051 is 125 mA.
◦ Maximum power dissipation rating is 1 W.
} GND（pin 20）：ground
} XTAL1 and XTAL2（pins 19,18）：These 2 pins provide external clock.
◦ Way 1：using a quartz crystal oscillator
◦ Way 2：using a TTL oscillator
} XTAL1 XTAL2 (18):
• Output of the inverting amplifier that forms a part of the oscillator and input to the internal clock
generator.
} XTAL1 (19):
• is the input to the inverting amplifier that forms part of the oscillator circuit.
• In case of external clock, this pin must be connected to ground.
33
XTAL Connection to 8051
C2
XTAL2
} Using a quartz crystal oscillator 30pF
} We can observe the frequency on the XTAL2 pin. C1
XTAL1
30pF

GND
XTAL Connection to an External Clock Source

NC XTAL2

} Using a TTL oscillator

External
Oscillator XTAL1 } XTAL2 is unconnected.
Signal

GND

34
Machine Cycle

} Find the machine cycle for

} (a) XTAL = 11.0592 MHz
} (b) XTAL = 16 MHz.

} Solution:

} (a) 11.0592 MHz / 12 = 921.6 kHz;

} machine cycle = 1 / 921.6 kHz = 1.085 µs
} (b) 16 MHz / 12 = 1.333 MHz;
} machine cycle = 1 / 1.333 MHz = 0.75 µs

35
Pins of 8051
} RST（pin 9）：reset
◦ input pin and active high. Vcc
– The high pulse must be high at least 2
machine cycles.
◦ power-on reset.
10 uF
– Upon applying a high pulse to RST, the
microcontroller will reset and all values in
RST
registers will be lost. 9
– Reset values of some 8051 registers 8.2 K
X1
30 pF
◦ power-on reset circuit
X2

Power-On RESET

36
Pins of 8051
} /EA（pin 31）：external access
◦ There is no on-chip ROM in 8031 and 8032 .
◦ The /EA pin is connected to GND to indicate the code is stored externally.
◦ /PSEN ＆ ALE are used for external ROM.
◦ For 8051, /EA pin is connected to Vcc.
◦ “/” means active low.
} /PSEN（pin 29）：program store enable
◦ This is an output pin and is connected to the OE pin of the ROM.
} ALE（pin 30）：address latch enable
◦ It is an output pin and is active high.
◦ 8051 port 0 provides both address and data.
◦ The ALE pin is used for de-multiplexing the address and data by connecting to the G
pin of the 74LS373 latch.

37
IMPORTANT PINS (IO Ports)
} One of the most useful features of the 8051 is that it contains four I/O ports (P0 - P3)
} Port 0 （pins 32-39）：P0（P0.0～P0.7）
◦ 8-bit R/W - General Purpose I/O
◦ Or acts as a multiplexed low byte address and data bus for external memory design
} Port 1 （pins 1-8） ：P1（P1.0～P1.7）
◦ Only 8-bit R/W - General Purpose I/O
} Port 2 （pins 21-28）：P2（P2.0～P2.7）
◦ 8-bit R/W - General Purpose I/O
◦ Or high byte of the address bus for external memory design
} Port 3 （pins 10-17）：P3（P3.0～P3.7）
◦ General Purpose I/O
◦ if not using any of the internal peripherals (timers) or
◦ external interrupts.
} Each port can be used as input or output (bi-direction)

38
Hardware Structure of I/O Pin
} Each pin of I/O ports
◦ Internally connected to CPU bus
◦ A D latch store the value of this pin
Read V
– Write to latch＝1：write data into the D latch TB
cc
latch 2 Load(L1)
◦ 2 Tri-state buffer：
Internal P1.X pin
– TB1: controlled by “Read pin” D Q
CPU bus
– Read pin＝1：really read the data Clk Q
Write to M1
present at the pin latch
– TB2: controlled by “Read latch”
– Read latch＝1：read value from TB
internal latch Read pin 1
◦ A transistor M1 gate
– Gate=0: open
– Gate=1: close 39
Address Multiplexing for External Memory

Accessing external code memory Multiplexing the address (low-byte) and data bus

40
External code memory

WR
RD
PSEN OE
ALE 74LS373 CS
G
P0.0 A0
D
P0.7 A7

D0
D7
EA
P2.0 A8
P2.7 A15

8051 ROM

41
External data memory

WR WR
RD RD
PSEN
ALE 74LS37 CS
G
P0.0 3 A0
D
P0.7 A7

D0
D7
EA
P2.0 A8
P2.7 A15

8051 RAM
Interface to 1K RAM

42
Overlapping External Code and Data Spaces

WR WR
RD
PSEN RD
ALE 74LS373 CS
G
P0.0 A0
D
P0.7 A7

D0
D7
EA
P2.0 A8
P2.7 A15

8051 RAM
43
Timing for MOVX Instruction

44
Overlapping External Code and Data Spaces
qAllows the RAM to be
v written as data memory, and
v read as data memory as well as
code memory.
qThis allows a program to be
vdownloaded from outside into the
RAM as data, and
v executed from RAM as code.

45
Interrupts

46
Inside Architecture of 8051

External interrupts
On-chip ROM Timer/Counter
Interrupt for program
On-chip Timer 1 Counter
Control code
RAM Timer 0 Inputs

CPU

Bus Control Serial

4 I/O Ports
OSC Port

P0 P1 P2 P3 TxD RxD
Address/Data

8051 Microcontroller Block Diagram 47

I/O Services
• A single microcontroller can serve several devices.
• Two ways:
§ Interrupt method
ü An interrupt is an external or internal event that interrupts the microcontroller to inform it that
a device needs its service.
ü Whenever any device needs its service, the device notifies the microcontroller by sending it an
interrupt signal.
ü Upon receiving an interrupt signal, the microcontroller interrupts whatever it is doing and
serves the device.
ü The program which is associated with the interrupt is called the interrupt service routine (ISR)
or interrupt handler.
§ Polling method
Ø The microcontroller continuously monitors the status of a given device.
Ø When the condition is met, it performs the device.
Ø After that, it moves on to monitor the next device until every one is serviced.
Ø The microcontroller check all devices in a round-robin fashion.
48
Interrupt Service Routine
• For every interrupt, there is a fixed location in memory that holds the address of its ISR.
• The group of memory locations set aside to hold the addresses of ISRs is called the interrupt vector table

The advantage of Interrupts

• The microcontroller can serve many devices.
• Each device can get service based on the priority assigned to it.
• The microcontroller can ignore (mask) a device request.
• The use of microcontroller is more efficient.
– Ex: in polling system, HERE: JNB TI, HERE wastes much of the microcontroller’s time.

Steps in Enabling an Interrupt

• To enable an interrupt, we take the following steps:
– Set EA=1. Enables all interrupts.
• If EA=0, no interrupt will be responded to, even if the associated bit in the IE is high.
– Enable each interrupt by setting its corresponding bit in IE.
49
Six Interrupts in the 8051
• Reset
• Two interrupt for the timers
– TF0, TF1
• Two interrupt for external hardware interrupts
– INT0, INT1
• Serial communication
– TI or RI
• There is a limited number of bytes for each interrupt.
– 3 bytes for reset
– 8 bytes for timers and external hardware interrupts
– If the service routine is too short to fit the ISR, an LJMP instruction is placed in the vector table to
point to the address of the ISR.
• Programmers must enable these interrupts before using them.

Note: that there are only 8 memory locations between vectors.

50
Interrupt Vectors
• Each interrupt has a specific place in code memory where program execution (interrupt service
routine) begins.

Interrupt ROM Location (Hex) Pin

Reset 0000 9
External hardware interrupt 0 (INT0) 0003 P3.2 (12)

Timer 0 interrupt (TF0) 000B

External hardware interrupt 1 (INT1) 0013 P3.3 (13)

Timer 1 interrupt (TF1) 001B

Serial COM interrupt (RI and TI) 0023

51
IE (Interrupt Enable) Register

EA IE.7 Disables all interrupts.

If EA=0, no interrupt is acknowledged.
If EA=1, each interrupt source is individually enabled of
disabled by setting or clearing its enable bit.
--- IE.6 Not implemented, reserved for future use. *
ET2 IE.5 Enables or disables timer 2 overflow or capture interrupt (8952).
ES IE.4 Enables or disables the serial port interrupt. RI or TI
ET1 IE.3 Enables or disables timer 1 overflow interrupt. TF1
EX1 IE.2 Enables or disables external interrupt 1. INT1
ET0 IE.1 Enables or disables timer 0 overflow interrupt. TF0
EX0 IE.0 Enables or disables external interrupt 0. INT0
52
External Hardware Interrupts
• The 8051 has two external hardware interrupts:
– EX0: INT0, Pin 12 (P3.2)
– EX1: INT1, Pin 13 (P3.3)
• These two pins are used in timer/counter.
– INT is a trigger for hardware control (GATE=1).
– Timer/counter is enabled only while the INT pin is high and the TR control pin is set.
• They are enabled and disabled using the IE register.
– EX0 by IE.0
– EX1 by IE.1
• Upon activation of these pins, the 8051 gets interrupted and jumps to the vector table to perform the ISR.
• There are two activation levels for the external hardware interrupts:
– Low level triggered
– Falling edge triggered
• This is chosen by IT0/IT1 in TCON.
– On Reset, IT0 and IT1 are both low, making external interrupts low level-triggered.
53
Interrupt Process
• If interrupt event occurs AND interrupt flag for that event is enabled, AND interrupts are
enabled, then:
ü Current PC is pushed on stack.
ü Program execution continues at the interrupt vector address for that interrupt.
ü When a RETI instruction is encountered, the PC is popped from the stack and program execution resumes
where it left off.

Interrupt Priorities

• What if two interrupt sources interrupt at the same time?

• The interrupt with the highest PRIORITY gets serviced first.
• All interrupts have a default priority order.
• Priority can also be set to “high” or “low”.

54
Interrupt SFRs

Interrupt enables for the 5 original 8051 interrupts:

Timer 2
Serial (UART0)
Timer 1
Global Interrupt Enable – must
External 1
be set to 1 for any interrupt to
1 = Enable Timer 0
be enabled
0 = Disable External 0

55
Interrupts

…
mov a, #2
mov b, #16
mul ab
Program Execution

mov R0, a
mov R1, b interrupt
mov a, #12 ISR: inc r7
mov b, #20 mov a,r7
mul ab jnz NEXT
add a, R0 cpl P1.6
mov R0, a NEXT: reti
mov a, R1
addc a, b return
mov R1, a
end

56
Timer and Counter
• The 8051 has two counters/timers which can be used either as timer to generate a time delay
or as counter to count events happening outside the microcontroller.
• They can be used either as timers or as counters.
• The Timer :Used as a time delay generator.
– The clock source is the internal crystal frequency of the 8051.
• An event counter.
– External input from input pin to count the number of events on registers.
– These clock pulses cold represent the number of people passing through an entrance, or the
number of wheel rotations, or any other event that can be converted to pulses.
• The 8051 has 2 timers/counters:
ü Timer/Counter 0
ü Timer/Counter 1
• Both timers are 16 bits wide.
• Since the 8051 has an 8-bit architecture, each 16-bit is accessed as two separate registers of low byte and
high byte.
• Timer0 registers is a 16 bits register and accessed as low byte and high byte.
• The low byte is referred as a TL0 and the high byte is referred as TH0.
57
• These registers can be accessed like any other registers.
Timer
• Set the initial value of registers
• Start the timer and then the 8051 counts up.
• Input from internal system clock (machine cycle)
• When the registers equal to 0 and the 8051 sets a bit to denote time out

8051

P2 P1
To LCD
Set Timer 0
TH0

TL0

58
Counter
• Count the number of events
– Show the number of events on registers
– External input from T0 input pin (P3.4) for Counter 0
– External input from T1 input pin (P3.5) for Counter 1
– External input from Tx input pin.
– We use Tx to denote T0 or T1.

8051

TH0
P1 to
TL0 LCD
P3.4
a switch T0

59
Registers Used in Timer/Counter
• 8051 has two 16-bit Timer registers ,Timer 0 & Timer 1.
• As 8051 has 8-bit architecture , each Timer register is treated as two 8-bit registers namely
TH0, TL0, TH1, TL1.
• One 8-bit mode register -TMOD.
• One 8-bit control register-TCON.

Edge-Triggered Interrupt
• To make INT0 and INT1 edge-triggered interrupts, we must program the bits of the TCON
register
– The TCON register holds the IT0 and IT1 flag bits that determine level- or edge-
triggered mode of the hardware interrupt
• IT0 and IT1 are bits D0 and D2 of TCON
– They are also referred to as TCON.0 and TCON.2 since the TCON register is
bit-addressable

60
TCON Register

61
TCON Register

62
TCON Register

• Timer control register TMOD is a 8-bit register which is bit addressable and in which Upper
nibble is for timer/counter, lower nibble is for interrupts
• TR (Timer run control bit)
TR0 for Timer/counter 0; TR1 for Timer/counter 1.
TR is set by programmer to turn timer/counter on/off.
TR=0 : off (stop)
TR=1 : on (start)
• TF (timer flag, control flag)
TF0 for timer/counter 0; TF1 for timer/counter 1.
TF is like a carry. Originally, TF=0. When TH-TL roll over to 0000 from FFFFH, the TF is set to 1.
TF=0 : not reach
TF=1: reach
If we enable interrupt, TF=1 will trigger ISR. 63
Equivalent Instructions for the Timer Control Register
For timer 0
SETB TR0 = SETB TCON.4
CLR TR0 = CLR TCON.4

SETB TF0 = SETB TCON.5

CLR TF0 = CLR TCON.5
For timer 1
SETB TR1 = SETB TCON.6
CLR TR1 = CLR TCON.6

SETB TF1 = SETB TCON.7

CLR TF1 = CLR TCON.7

TCON: Timer/Counter Control Register

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD Register

q Both Timer 0 &Timer 1 use the same Mode register TMOD.

• It is an 8-bit register.
• The lower 4-bits are meant for Timer 0 & the user 4-bits are meant for Timer 1
• It is not a bit addressable.
• It is used similar to any other register of 8051.
• For ex:
MOV TMOD,#21H
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TMOD Register
GATE
• Every timer has a mean of starting and stopping.
– GATE=0
• Internal control
• The start and stop of the timer are controlled by way of software.
• Set/clear the TR for start/stop timer.
SETB TR0
CLR TR0
– GATE=1
• External control
• The hardware way of starting and stopping the timer by software and an external
source.
• Timer/counter is enabled only while the INT pin is high, and the TR control pin is
set (TR).
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TMOD Register
C/T : Timer or counter selected cleared for timer operation (input from internal system
clock). Set for counter operation (input from Tx input pin).
M1,M0 : Used for mode selection. Because the Timers of 8051 can be set in 4-different modes.

M1 M0 Mode Operation
0 0 0 13-bit timer mode 8-bit THx + 5-bit TLx (x= 0 or 1)
0 1 1 16-bit timer mode 8-bit THx + 8-bit TLx
1 0 2 8-bit auto-reload 8-bit auto-reload timer/counter;
THx holds a value that is to be reloaded into
TLx each time it overflows.
1 1 3 Split timer mode

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TMOD Register

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Working of Timer Mode 1
• For this , let us consider timer 0 as an example.
• 16-bit timer (TH0 and TL0)
• TH0-TL0 is incremented continuously when TR0 is set to 1.
• And the 8051 stops to increment TH0-TL0 when TR0 is cleared.
• The timer works with the internal system clock.
• In other words, the timer counts up each machine cycle.
• When the timer (TH0-TL0) reaches its maximum of FFFFH, it rolls over to 0000, and TF0 is
raised.
• Programmer should check TF0 and stop the timer 0.

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Steps of Mode 1
1. Choose mode 1 timer 0
– MOV TMOD,#01H
2. Set the original value to TH0 and TL0.
– MOV TH0,#FFH
– MOV TL0,#FCH
3. You better to clear the TF: TF0=0.
– CLR TF0
4. Start the timer.
– SETB TR0

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Steps of Mode 1

5. The 8051 starts to count up by incrementing the TH0-TL0.

– TH0-TL0= FFFCH,FFFDH,FFFEH,FFFFH,0000H

TR0=1 TR0=0
TH0 TL0
Start timer
Stop timer

FFFC FFFD FFFE FFFF 0000

TF = 0 TF = 0 TF = 0 TF = 0 TF = 1

TF Monitor TF until TF=1

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Steps of Mode 1

6. When TH0-TL0 rolls over from FFFFH to 0000, the 8051 set TF0=1.
TH0-TL0= FFFE H, FFFF H, 0000 H (Now TF0=1)
7. Keep monitoring the timer flag (TF) to see if it is raised.
AGAIN: JNB TF0, AGAIN
8. Clear TR0 to stop the process.
CLR TR0
9. Clear the TF flag for the next round.
CLR TF0

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Basics of serial communication

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RxD and TxD pins in the 8051
• The 8051 has two pins for transferring and receiving data by serial communication. These two
pins are part of the Port3(P3.0 &P3.1)
• These pins are TTL compatible and hence they require a line driver to make them RS232
compatible
• Max232 chip is one such line driver in use.
• Serial communication is controlled by an 8-bit register called SCON register, it is a bit
addressable register.

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Interfacing to PC

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SCON (Serial control) register

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SM0 , SM1, REN, TI, RI
• These two bits of SCON register determine the framing of data by specifying the number of
bits per character and start bit and stop bits. There are 4 serial modes.
SM0 SM1
0 0 Serial Mode 0
0 1 Serial Mode 1, 8-bit data, 1 stop bit, 1 start bit
1 0 Serial Mode 2
1 1 Serial Mode 3
• REN (Receive Enable) also referred to as SCON.4.
• When it is high, it allows the 8051 to receive data on the RxD pin.
• So, to receive and transfer data REN must be set to 1.
• When REN=0, the receiver is disabled.
• This is achieved as below
SETB SCON.4 & CLR SCON.4

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Contd…
TI (Transmit interrupt) is the D1 bit of SCON register.
• When 8051 finishes the transfer of 8-bit character, it raises the TI flag to indicate that it is
ready to transfer another byte.
• The TI bit is raised at the beginning of the stop bit.
RI (Receive interrupt) is the D0 bit of the SCON register.
• When the 8051 receives data serially ,via RxD, it gets rid of the start and stop bits and places
the byte in the SBUF register.
• Then it raises the RI flag bit to indicate that a byte has been received and should be picked up
before it is lost.
• RI is raised halfway through the stop bit.

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Thank you