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Course Name: VLSI PHYSICAL DESIGN

Assignment- Week 10
TYPE OF QUESTION: MCQ/MSQ/SA
Number of questions: 10 Total mark: 10 x 1 = 10
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QUESTION 1:
To detect a stuck-at-0 fault on line X of a circuit, the required test vector T must satisfy the
following:
a. The fault-free value at line X must be 0.
b. The fault-free value at line X must be 1.
c. The fault-free and faulty logic values at the primary output(s) must be same.
d. The fault-free and faulty logic values at the primary output(s) must be different.

Correct Answer: b, d

Detailed Solution: To detect a stuck-at fault in a circuit, the necessary conditions are: (i) the
fault-free logic value at the site of the fault must be opposite to the polarity of the fault, and (ii)
the fault-free and faulty logic values on at least one of the primary outputs must be different.
Hence, the correct options are (b) and (d).
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QUESTION 2:
Which of the following represents the Boolean difference of the function F = A’B + AC’ + B with
respect to variable C?
a. A’B
b. AB’
c. A’B+A
d. B
Correct Answer: b

Detailed Solution: The Boolean difference of F with respect to C is given by:

dF/dC = FC=0 xor FC=1
= (A’B + A + B) xor (A’B + B) = (A + B) xor B
= (A + B)’B + (A + B)B’ = AB’
Hence, the correct option is (b).
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QUESTION 3:
Which of the following statements are true for detecting a stuck-at fault X/1 in a circuit?
a. During the forward drive phase of path sensitization, we set primary input values
so that the logic value at X becomes 0.
b. During the forward drive phase of path sensitization, we sensitize a path so that
any change in X is propagated to one of the primary outputs.
c. We avoid any fanout connection at line X by replicating gates.
d. None of these.
Correct Answer: b
Detailed Solution: Option (a) is not true as the primary input values are not set during the
forward drive phase. Option (c) is also not true, as the method does not depend on fanout
connection at line X. During the forward drive phase, the objective is to set the value to X to a
value reverse to that of the polarity of the fault (here, X = 0), and sensitize a path from X to one
of the primary outputs.
The correct option is (b).
QUESTION 4:
What do you mean by aliasing in LFSR-based test data compaction?
a. Some error has occurred for which the faulty circuit is identical to the fault-free
circuit.
b. Two different faults occur that are equivalent faults.
c. During compaction, the fault-free and faulty signatures become identical.
d. None of these.
Correct Answer: c
Detailed Solution: In LFSR-based data compaction, the test data are applied serially to the input
of the LFSR and the final value in the register is taken to be the signature. Since this is a many-
to-one mapping, multiple data streams applied at the input may lead to the same signature. If a
faulty bit stream generates the same signature as the fault-free bit stream, it is called aliasing.
The correct option is (c).
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QUESTION 5:
Consider a scan path design where there are 15 scan flip-flops, 5 primary inputs, 3 primary
outputs, and we have to apply 100 combinational test vectors. The total number of clock cycles
required for applying the test vectors and observing the outputs will be _____________. Ignore
the additional clock cycles required to test the scan chain.
Correct Answer: Range 1610 to 1620

Detailed Solution: If ns and nc respectively denote the number of flip-flops in the scan chain and
the number of combinational test vectors, then the total number of clock cycles required for test
application is given by: (ns + 1)nc + ns. The value does not depend on the number of primary
inputs or outputs.
In this example, number of clock cycles = (15 + 1) x 100 + 15 = 1600 + 15 = 1615.
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QUESTION 6:
Which of the following test patterns must be applied to the input of a scan chain to test faults
in the scan flip-flops?
a. 1000 1000 1000 1000 …
b. 1100 1100 1100 1100 …
c. 1111 0000 1111 0000 …
d. 0011 0011 0011 0011 …

Correct Answer: b, d

Detailed Solution: To test for faults in the scan flip-flops, we have to serially shift in a sequence
of bits to the scan chain such that every flip-flop undergoes all possible transitions (0 to 0, 0 to 1,
1 to 0, and 1 to 1). The test vectors mentioned in option (b) and (d) have this property. In fact, we
can either apply 1100 1100 … or else 0011 0011 ….
Hence, the correct options are (b) and (d).
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QUESTION 7:
For a 10-bit LFSR generating an m-sequence, the number of distinct patterns that can be
generated before they are repeated is ____________.
Correct Answer: 1023

Detailed Solution: An LFSR that implements a primitive polynomial generates a maximum-

length sequence (called m-sequence). For such an n-bit LFSR, the number of distinct patterns
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that are generated is given by 2n – 1. Here, n=10, and hence the number of patterns = 210 – 1 =
1023.
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QUESTION 8:
For a 6-bit LFSR compacting a 3000-bit serial bit stream, the probability of aliasing is given by
________________.

Correct Answer: Range 0.0150 to 0.0160

Detailed Solution: For an n-bit LFSR, the probability of aliasing is given by 1/2n, which is
independent of the length of the bit pattern being compressed. Here, n=6, and so the probability
of aliasing = 1/64 = 0.0156.
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QUESTION 9:
Which of the following statements is/are true for full-scan based testing?
a. Test vectors cannot be applied at the maximum rated clock frequency.
b. Test vectors can be applied at the maximum rated clock frequency.
c. A sequential circuit ATPG tool is required for test generation.
d. A combinational circuit ATPG tool is required for test generation.
Correct Answer: a, d

Detailed Solution: In full-scan based testing, due to the presence of the scan chain, test vectors
have to be serially shifted in and circuit responses serially shifted out. Hence, testing at
maximum rated clock frequency cannot be carried out. Also, because of complete controllability
and observability of the flip-flops, a combinational ATPG tool is sufficient for generating the test
vectors.
Hence, the correct options are (a) and (d).
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QUESTION 10:
Which of the following is/are true for BIST?
a. The number of required test patterns is less.
b. There is no hardware overhead to allow for self-testing.
c. Test application can be carried out at the maximum clock speed of the chip.
d. Test patterns are randomly generated.

Correct Answer: c, d
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Detailed Solution: BIST normally uses random pattern testing, where the number of test
patterns is large. It incurs additional hardware overhead that includes the pattern generation and
response compaction circuitry on-chip. However, the patterns can be applied at the maximum
rated clock frequency.
Hence the correct answers are (c) and (d).
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