17th International Microelectronics Olympiad

TEST

The participants shall select one answer out of 5 possible answers in the answer sheet for each question (A, B, C, D, E)

by crossing lines from the top left corner to the bottom right corner and form the bottom left corner to the top right

corner (as it is shown below).

8. A B C D E

In the case of crossing out more than one answer for the same question or making any other notes, the answer to that

question will be scored 0.

8. A B C D E

Participant ___________________________________________

University ___________________________________________
1. Which one is the correct timing condition for the following circuit?

A. t +t <t
pFF setup p,comb
B. tsetup+thold+tpcomb < T
C. t +t <t Combin D Q
pFF p,comb hold
ational DFF
D. t +t <T+t
pFF p,comb setup Logic
E. t +t +t -T >0
pFF p,comb setup

CLK

2. Determine the condition where the transmission line is overdriven.

Vi
A. Zs > Zt
B. Zs<Zt Zs
C. Zs<Z0 TL
Zt
D. Zs+Zt>Z0 Zo
Vs
E. Zs+Zt<Z0

GND
3. The value of threshold voltage of a short channel MOS transistor depends only on:
A. Source voltage
B. Geometric dimensions of the transistor
C. Channel length and drain voltage
D. Type of substrate conductivity
E. Type of gate insulator

4. Technological operations for integrated circuit manufacturing are:

A. Ion implantation and diffusion
B. Ion etching
C. Lithography
D. Metallization
E. All the answers are correct

5. Which of the following goals is used in timing-driven placement criteria?

A. Reduction of the total length of interconnects
B. Reduction of area
C. Reduction of the length of interconnects on the decisive paths
D. Equalization of interconnect lengths
E. Reduction of the number of vias

6. Which of the following goals is used in thermal placement criteria?

A. Reduction of the thermal gradient
B. Reduction of powers of separate elements
C. Increase of placement area
D. Placement of powerful elements in the central parts
E. Reduction of placement area

7. How to calculate the power delay product (PDP) value?

A. 𝑃𝐷𝑃 = 𝐶𝑡𝑜𝑡 𝑉𝐷𝐷2 𝑓(𝑡𝑃𝐻𝐿 + 𝑡𝑃𝐿𝐻 )
B. 𝑃𝐷𝑃 = 𝐶𝑡𝑜𝑡 𝑓(𝑡𝑃𝐻𝐿 + 𝑡𝑃𝐿𝐻 )
C. 𝑃𝐷𝑃 = 𝐶𝑡𝑜𝑡 𝑉𝐷𝐷2 𝑓
D. 𝑃𝐷𝑃 = 𝐶𝑡𝑜𝑡 𝑉𝐷𝐷2 (𝑡𝑃𝐻𝐿 + 𝑡𝑃𝐿𝐻 )
E. 𝑃𝐷𝑃 = 𝐶𝑡𝑜𝑡 𝑉𝐷𝐷2
8. How to calculate propagation delay for the below circuit?

A. 𝑡𝑃𝐿𝐻 = 𝑡𝑃𝐻𝐿 = 0.7𝑁(𝑅𝑛 ||𝑅𝑝 )𝐶𝑙𝑜𝑎𝑑 + 0.35(𝑅𝑛 ||𝑅𝑝 )(𝐶𝑜𝑥𝑝 + 𝐶𝑜𝑥𝑛 )

B. 𝑡𝑃𝐿𝐻 = 𝑡𝑃𝐻𝐿 = 0.7𝑁(𝑅𝑛 ||𝑅𝑝 )𝐶𝑙𝑜𝑎𝑑 + (𝐶𝑜𝑥𝑝 + 𝐶𝑜𝑥𝑛 )𝑁 2
C. 𝑡𝑃𝐿𝐻 = 𝑡𝑃𝐻𝐿 = 0.7𝑁(𝑅𝑛 ||𝑅𝑝 )𝐶𝑙𝑜𝑎𝑑 + 0.35(𝑅𝑛 ||𝑅𝑝 )(𝐶𝑜𝑥𝑝 + 𝐶𝑜𝑥𝑛 )𝑁 2
D. 𝑡𝑃𝐿𝐻 = 𝑡𝑃𝐻𝐿 = 0.7𝑁(𝑅𝑛 ||𝑅𝑝 )𝐶𝑙𝑜𝑎𝑑 + 0.35(𝑅𝑛 ||𝑅𝑝 )
E. 𝑡𝑃𝐿𝐻 = 𝑡𝑃𝐻𝐿 = 0.35(𝑅𝑛 ||𝑅𝑝 )(𝐶𝑜𝑥𝑝 + 𝐶𝑜𝑥𝑛 )𝑁 2

9. The function f(a,b,c) =(1,3,4,5) is given. Find its minimum form and check if there is a static hazard. What
implicant should be added to eliminate the static hazard?

A. a~b
B. ~bc
C. bc
D. b~c
E. ac

10. Determine which function is implemented by the following circuit.

A. y=~a~b+ac DC 0
B. y=ab+~c 1
C. y=~b~c+ac c 20 2
D. y=ab+~bc b 21 3
E. =a~b+ac y
22 4
a 5
6
7

(𝑛+1) 3 1
11. Calculate the limit: 𝑙𝑖𝑚 ∑𝑘=𝑛3 3 .
𝑛→∞ √𝑘 2 +4𝑘
A. 2
B. 3
C. 4
D. 5
E. 6
1 100 0 0
0 1 100 0
12. We have fourth order determinant Δ = | |. We want to change one element of this determinant
0 0 1 100
0 0 0 1
by the value ε=0.000001 so that perturbed determinant’s value will be zero. Is it possible, and, if yes, then what
element should be changed? (Example of an answer: (2,1), that is the element from second row and first column
should be changed).
A. 3,1
B. 3,2
C. 4,1
D. 4,2
E. Impossible

13. Detection Test for a fault F on a line A.

Given a combinational circuit with n inputs x1, x2, …, xn and m output pins implementing the Boolean functions fj = fj
(x1, x2, …, xn), j=1, …, m. Let fj*(x1, x2, … xn) be the j-th output function of the circuit with fault F on the line A.
Then, a fault F on a line A of the circuit is called a detectable fault if and only if
A. There exists a j, 1≤j≤m, there exists an input pattern (a1, a2, …, an), ai  {0,1}, i=1, 2, …, n, such that fj*(
a1, a2, …, an)  fj(a1, a2, …, an);
B. For all j, 1≤j≤m, there exists an input vector (a1, a2, …, an), ai  {0,1}, i=1, 2, …, n, such that fj*( a1, a2, …, an)
 fj(a1, a2, …, an ;
C. For all j, 1≤j≤m, for all input vectors (a1, a2, …, an), ai  {0,1}, i=1, 2, …, n, it is true that fj*( a1, a2, …, an)
 fj(a1, a2, …, an);
D. There exists a j, 1≤j≤m, there does not exist an input vector (a1, a2, …, an), ai  {0,1}, i=1, 2, …, n, such that
fj*( a1, a2, …, an)  fj(a1, a2, …, an);
E. For all j, 1≤j≤m, there exists an input vector (a1, a2, …, an), ai  {0,1}, i=1, 2, …, n, such that fj*( a1, a2, …, an)
= fj(a1, a2, …, an) .

14. Application of Boolean difference for detection of stuck-at faults on internal nodes g.

The given combinational circuit with n inputs x1, x2, …, xn and an output f(x1, x2, …, xn) (see the figure below) consists
of two combinational sub-circuits C1 and C2 combined by a node g=g(x)=g(x1, x2, …, xn). The node g is stuck-at-c, c
{0,1}. Point out the Boolean equation below that should be solved to find all the test patterns detecting the stuck-at fault
g/0 where x’ is the negation of x, the Boolean function f*(x1, x2, …, xn , g(x)) is obtained from f(x1, x2, …, xn) by a
modification to express its dependence on g(x), the Boolean function implemented by node g :

A. g(x) & df*(x, g(x)) / dg(x) = 1

B. g(x) & df*(x, g(x)) / dg(x) = 0
C. g’(x) & df*(x, g(x)) + df*(x, g(x)) / dg(x) = 1
D. g(x)’df*(x, g(x)) / dg(x) = 1
E. df*(x, g(x)) / dg(x) = 0

x1
x2
C1 g C2
xn … f (x1 x2, …, xn)
Node g stuck-at-c

f(x1, x2, …, xn)=f*(x1, x2, …, xn, g( x1, x2, …, xn)).

15. What chemical elements in semiconductors can be as acceptors?

A. Bor (B)
B. Silicon (Si)
C. Phosphorus (P)
D. Gallium (Ga)
E. All of the above

16. The potential barrier in a semiconductor energy diagram, compared to insulators, is:
A. Slightly large
B. Very large
C. Small
D. Almost equal
E. There is no potential barrier
17. Which single stage amplifier has the greatest amplification in theory?
A. Common source with current source load
B. Common gate with current source load
C. Common source with resistive load
D. Source follower with current source load
E. Common gate with resistive load

18. How will be changed the output common mode voltage of an nmos input based differential amplifier if decreasing
the tail current (Iss)?
A. Will decrease
B. It’s depended on what load is used
C. Will not change
D. Will increase
E. The output common mode voltage of a differential amplifier does not depend on tail current (Iss) value

19. What will be the value of j in the following snippet?

int main() { int i = 5; int j = i++ + ++i; }
A. 10
B. 11
C. 12
D. Implementation-defined
E. Undefined

20. What is the time complexity of the following code?

int c = 0;
for (int i = n; i > 0; i /= 2) {
for (int j = 0; j < i; ++j) {
++c;
}
}

A. 𝑂(𝑛)
B. 𝑂(𝑛 log 𝑛)
C. 𝑂(𝑛 log log 𝑛)
D. 𝑂(𝑛2 )
E. 𝑂(𝑛√𝑛)

21. By what technological method was the p-type layer obtained on the initial n-type Si substrate?

A. Thermal diffusion
B. Vacuum deposition
C. Ion implantation
D. Epitaxy
E. None of the above
22. Which of the structures corresponds to a photodiode?

E. None of the above

23. For what value of  does the following problem have no solution:

f (X) = x 1 + x 2 + x 3 → max ,
XD

x 1 + x 3 = 2,

D : x 1 + 2x 2 + x 3 = 0,
x  0, x  0,x  0 :
 1 2 3

A. 2
B. 3
C. 1
D. 0.5
E. 0

24. The following linear programming problem has

f (X) = 2x 1 + 4x 2 → min,
XD

x 1 + 2x 2  5,

D : x 1 + x 2  4,
x  0, x  0 :
 1 2
A. One Solution
B. No Solution
C. Many Alternative Optimal Solutions
D. Unbounded Solutions
E. Two Solutions

25. Multiply the following 16-bit numbers:

(1ADB)16 × (7D)16 =

A. (F1ECF)16
B. (FC1FE)16
C. (D1CEF)16
D. (C1FEF)16
E. (CF1ED)16

26. Divide the following 16-bit numbers:

(1ADB)16 ÷ (7D)16 =

A. (26)16
B. (72)16
C. (54)16
D. (37)16
E. (42)16
Answer Sheet

A B C D E A B C D E
1. 14.

A B C D E A B C D E
2. 15.

A B C D E A B C D E
3. 16.

A B C D E A B C D E
4. 17.

A B C D E A B C D E
5. 18.

A B C D E A B C D E
6. 19.

A B C D E A B C D E
7. 20.

A B C D E A B C D E
8. 21.

A B C D E A B C D E
9. 22.

A B C D E A B C D E
10. 23.

A B C D E A B C D E
11. 24.

A B C D E A B C D E
12. 25.

A B C D E A B C D E
13. 26.

Student ___________________________________________

University ___________________________________________