COA MODULE 2 PREVIOUS YEAR QUESTION PAPER SOLVED

1.Explain shift microoperation with help of examples. 3

2. Illustrate the processor organisation using scratchpad memory with
help of a diagram. 3
3. What is the role of status register within the processor? Draw the
circuit diagram for a basic status register for an 8-bit ALU and explain
how the carry and overflow status bits are set. 7
4.What is a control word? Explain, using an example, how a control
word can be used to specify a complete instruction. 7
5. Draw the circuit diagram and function table for one stage of the
logic unit for a 4-bit ALU with following logic operations - AND, O&
XOR and NOT. Explain the working. 7
6. Illustrate the use of accumulator register. Explain processor
organization using accumulator register with help of a diagram. 7
7. Write the register transfer logic format for a conditional control
statement, Give an example? 3
8. Discuss the logic used behind the booth multiplication algorithm 3
9. a) Describe processor organization with diagram using
i) scratchpad memory
ii) Two-port memory iii) Accumulator register 10
10. Draw and explain about true/complement circuit? 4
11.Give the structure of status register, which is connected to
8bit ALU 8
12.Design 4-bit combinationallogic shifter which'will perform the
operation given below with 2 control variable HI&HO?
i) Shrl
ii) clear
iii) Load all bits with I 6
13.What is micro-operation, With help of examples explain shift
micro-operation 3
14. Design an adder circuft with one selection variable S and 2 inputs
A and B. When S=0 circuit performs A+B, when S=l it performs A-B
by taking twos complement of B? (9)
15.Write a short note about accumulator register? 5
16. Give a simple design for generating status bits for an
8-bit ALU? 6
17. How do a binary adder circuit can be used for the implementation
of logical operation AND, OR, NOT, XOR. 8
18. How is the two port memory organization of processor unit better
when compared to scratch pad memory organization? 3
19. Give the block diagram of circuit that implements following
statements in register transfer logic: 3
T1; C <-A
Ti: C -R
20.Illustrate and explain the organization of a processor unit where
processor registers and ALU are connected through common buses.
Explain how the micro operation R2 <-- R3+R4 would be performed
using this organization, where R2, R3 and R4 are processor registers.
(7)
21. Explain with the help of a block diagram the design of a 4 bit
status register for an 8 bit ALU. The four status bits are c (carry),
s(sign), z(zero) and v(overflow). Clearly indicate the purpose of each
status bit and how they are set or reset. (7)
22. Describe about arithmetic, logic and shift micro operations, listing
the available, operations in each category (4)
23.Design and draw a combinational logic shifter using multiplexers
with two selection variables, H1 and Hn. The operations of shifter
should be as specified in the following table:
H1 H0 operation function
0 0 S<- 0 Transfer 0’s to
F
0 1 S<-shl F Shift left F to S
1 0 S<-shr F Shift right F to
S
1 1 S<-F No shift

(10)

ANSWER

Question 1 ,13
Micro-operation refers to a basic operation that can be executed on a register or memory at
the level of machine instructions. Micro-operations are the fundamental actions that the
processor performs in one cycle, like loading a register, shifting bits, or performing arithmetic
operations.
Shift Microoperation refers to the operation that shifts the contents of a register to the left or right,
typically by one or more positions. Shifting can be logical or arithmetic.

 Logical Shift: This shifts the bits of the register and fills the vacated positions with 0.
o Example: If the register holds 10110101 (in binary), a logical left shift by one
position results in 01101010 (the rightmost bit is replaced by 0).
 Arithmetic Shift: Similar to logical shift, but in case of a left shift, the vacated bit is
filled with 0. However, for right shift, the leftmost bit (sign bit) is copied to preserve
the sign of the number.
o Example: If the register holds 11010101 (in binary), an arithmetic right shift
will result in 11101010, preserving the sign bit.
Use case example:
 Left Shift (Logical): Multiplying an unsigned binary number by 2.
o If you have 0011 (which is 3 in decimal) and you perform a logical left shift,
you get 0110 (which is 6 in decimal).
 Right Shift (Arithmetic): Dividing a signed binary number by 2.
o If you have 1101 (which is -3 in decimal using 2's complement), an arithmetic
right shift will give you 1110 (which is -1 in decimal).

2. Processor Organization with Scratchpad Memory:

Scratchpad memory is a small, fast, and volatile type of memory used to store data
temporarily for fast access by the processor. It usually has a low capacity but offers quick
read/write speeds.
 processor: The processor has an ALU, control unit, and buses that control data flow to and
from the scratchpad memory.
 Scratchpad Memory: It holds data temporarily during operations, often holding
intermediate values or constants that need to be accessed quickly.
3.11.16.21. Status Register: The status register, often called the flag register, stores information
about the result of the last arithmetic or logic operation in the processor. It contains several status
bits, including:

 Carry Flag (C): Indicates whether there was a carry or borrow in the operation.
 Overflow Flag (V): Indicates whether the result of an operation exceeds the capacity
of the register (signed overflow).
 Zero Flag (Z): Indicates whether the result of the operation is zero.
 Sign Flag (S): Indicates whether the result of an operation is positive or negative.
  Carry Bit (C): Set when there is a carry out of the most significant bit during
addition, or when there is a borrow in subtraction.
  Overflow Bit (V): Set when the result of an addition or subtraction operation
causes the result to exceed the representable range of the data (e.g., signed overflow).
4. Control Word: A control word is a binary word used to control the operation of the
processor. It consists of a combination of bits, each specifying a particular control signal for
components like registers, ALU, and buses.
Example:
Assume we want to specify an instruction for the ALU to perform an addition
operation between two registers and store the result in a destination register.
Control word:
 Bit 0-3: Specifies the ALU operation (0001 for addition).
 Bit 4-5: Specifies the source registers (01 for register 2 and 10 for register 3).
 Bit 6-7: Specifies the destination register (11 for register 1).
Control Word Format: 0001 01 10 11
This control word tells the processor to:
1. Perform addition (from the ALU operation bits),
2. Use registers 2 and 3 as inputs (from the source register bits),
3. Store the result in register 1 (from the destination register bits).
5. Function Table:

Operation ALU Output

A AND B A & B

A OR B A

A XOR B A ^ B

NOT A ~A
Explanation:
 AND: All bits of the output will be 1 only if both corresponding bits of A and B are 1.
 OR: A bit is 1 in the output if at least one of the corresponding bits of A or B is 1.
 XOR: A bit in the output is 1 if and only if the corresponding bits of A and B are
different.
 NOT: Inverts the bits of A (flips 0 to 1 and 1 to 0).
6.16. Accumulator Register: The accumulator is a special register used to hold
intermediate results during arithmetic or logic operations in the processor. It is
typically used in processors with a "one-register" architecture.
7.Register Transfer Logic Format: Register transfer logic (RTL) specifies the operations that occur
during a single clock cycle in a processor. Conditional register transfer is used to transfer data based
on some condition.

Example:
 If the Zero Flag (Z) is set, then copy the value of Register A to Register B.
8. Booth's Algorithm is used to multiply two signed binary numbers in 2's complement form. It
reduces the number of operations by using a technique that considers pairs of bits in the multiplier.

 The basic idea is to examine two consecutive bits of the multiplier and determine
whether to add, subtract, or do nothing.
 For each step, the algorithm considers:
o If the pair is 01, add the multiplicand to the product.
o If the pair is 10, subtract the multiplicand from the product.
o If the pair is 00 or 11, no operation is performed.
This allows Booth’s algorithm to handle both positive and negative numbers efficiently.
9.
10. A True/Complement Circuit is a logic circuit that produces both the true value and the
complement (inverted) value of a binary number.

 True: The original binary value of A.

 Complement: The negated (flipped) value of A (A').

The circuit uses a NOT gate to produce the complement of the input

12. The 4-bit shifter design with two control variables (HI and HO) will perform the following
operations:

1. SHRL (Shift Right Logical): Shifts the 4-bit input to the right, filling with zeros on the left.

2. Clear: Clears all bits to 0.

3. Load all bits with I: Loads the input I into all 4 bits of the output.

Design Explanation:

 HI = 0, HO = 0: Shift right logically (SHRL).

 HI = 0, HO = 1: Clear all bits (set to 0).

 HI = 1, HO = 0: Load all bits with input I.

Truth Table:

HI HO Operation Output

0 0 SHRL (Shift Right) A3 A2 A1 0

0 1 Clear 0000

1 0 Load with I IIII

HI HO Operation Output

Logic Design: The shift logic can be implemented using multiplexers (MUX) to select the appropriate
operation based on the values of HI and HO

14. This is a multiplexer-based adder design.

 When S = 0: The circuit performs A + B.

 When S = 1: The circuit performs A - B, which is equivalent to A + (-B). To get -B, we need to
take the 2's complement of B.

Logic:

 The 2's complement of B is computed by inverting all bits of B and adding 1.

 Use a multiplexer to select between A + B (when S = 0) and A + (~B + 1) (when S = 1).

Diagram:

+-------+ +------+

A --->| |----| S |

|Adder | +------+

B --->| |----| |

+-------+ |

| |

A+B A + (2's Complement of B)

 When S = 0, the adder performs A + B.

 When S = 1, the adder performs A + (-B) (taking 2's complement of B).

17. A binary adder can be used to perform logical operations by manipulating the inputs in a specific
way:

 AND: The adder’s carry logic can be used to perform an AND operation. Set the sum output
as the AND of the inputs.

o Sum = A AND B

o Carry = 0 (since AND does not carry).

 OR: The sum output can be set to the result of an OR operation.

o Sum = A OR B

o Carry = 1 (since OR can always produce a carry).

 XOR: The sum output can be set to XOR the inputs.

o Sum = A XOR B

o Carry = (A AND NOT B) OR (NOT A AND B).

 NOT: Invert the bits before passing them to the adder.

o Sum = NOT A

o Carry = 0 (since NOT does not carry).

18. Two-Port Memory Organization:

In a two-port memory organization, the memory has two separate access ports, one for reading and
one for writing. This allows simultaneous reading and writing operations, which can improve the
performance of the processor by enabling parallel operations without conflicts.

Advantages:

1. Parallelism: It allows simultaneous read and write operations without any conflict. This is
useful in multi-step computations where data needs to be fetched and written back at the
same time, increasing throughput.

2. Faster Data Access: Two independent operations (e.g., reading data and writing results) can
occur at the same time, improving performance in processors that need fast access to
memory.

3. Improved Efficiency: It reduces bottlenecks in situations where different processor units

need to access the memory at the same time, ensuring that the processor doesn’t need to
wait for one operation to finish before starting another.

Scratchpad Memory Organization:

Scratchpad memory is a type of memory used for storing temporary data, and it usually involves a
single-port memory. This means only one operation (read or write) can occur at a time.

Disadvantages:

 Serial Access: Because scratchpad memory only has one access port, only one operation
(read or write) can occur at a time. This can lead to slower performance in scenarios where
multiple operations need to be performed simultaneously.

 Limited Throughput: Scratchpad memory might not be as efficient in high-performance

processors that require concurrent read and write operations for different parts of the
processor.

19.

T1; C <- A
T2; C <- R

This register transfer logic implies that during T1, the contents of register A are copied into register C,
and during T2, the contents of register R are copied into register C.
Block Diagram:

+---------+ +---------+

| Register| | Register|

| A |----->| C | <-- T1 (C <- A)

+---------+ +---------+

+---------+ +---------+

| Register| | Register|

| R |----->| C | <-- T2 (C <- R)

+---------+ +---------+

 T1 (C <- A): During T1, the value from register A is transferred to register C.

 T2 (C <- R): During T2, the value from register R is transferred to register C.

In both steps, the control signals would determine when each transfer occurs.

20. Processor Organization with Common Buses:

In this organization, multiple processor registers and the ALU are connected through shared data
buses. This setup allows the transfer of data between registers and the ALU for operations.

Diagram:

lua

Copy

+-----------+ +-----------+ +-----------+

| Register | | ALU | | Register |

| R2 |<-------->| |<--------->| R3 |

+-----------+ +-----------+ +-----------+

| |

+-----------+ +-----------+

| Register |<------------------------------------>| Register |

| R4 | | R2 |
+-----------+ +-----------+

Step-by-step explanation for micro-operation R2 <-- R3 + R4:

1. Step 1: Select registers R3 and R4 using multiplexers controlled by the control unit, and place
their contents on the data bus.

2. Step 2: Send the contents of R3 and R4 to the ALU through the bus.

3. Step 3: The ALU performs the addition operation R3 + R4 and produces the result.

4. Step 4: The result of R3 + R4 is sent back to R2 via the common bus.

5. Step 5: Register R2 captures the result from the bus.

Explanation of Operations:

 The ALU is responsible for performing the addition of R3 and R4.

 The control unit decides which registers are connected to the ALU and which register gets
the result.

This organization allows flexibility and efficient use of resources, as the same bus can be shared by
multiple registers and the ALU for different operations.

22.

 Arithmetic Micro-operations: These operations perform basic arithmetic on registers and

memory.

 Addition: Adding contents of two registers (e.g., R1 + R2).

 Subtraction: Subtracting the contents of one register from another (e.g., R1 - R2).

 Increment: Adding 1 to a register (e.g., R1 = R1 + 1).

 Decrement: Subtracting 1 from a register (e.g., R1 = R1 - 1).

 Logic Micro-operations: These operations perform logical operations on the bits of registers.

 AND: Performs a bitwise AND (e.g., R1 AND R2).

 OR: Performs a bitwise OR (e.g., R1 OR R2).

 XOR: Performs a bitwise exclusive OR (e.g., R1 XOR R2).

 NOT: Performs a bitwise negation (e.g., NOT R1).

 Shift Micro-operations: These operations move the bits of a register to the left or right.

 Logical Shift Left (SHL): Shifts all bits to the left and fills the rightmost bit with 0.

 Logical Shift Right (SHR): Shifts all bits to the right and fills the leftmost bit with 0.

 Arithmetic Shift Left: Same as SHL but typically used in signed integers.

 Arithmetic Shift Right: Shifts all bits to the right, and the leftmost bit is filled with the sign bit
for signed integers.
23. To implement this combinational logic shifter, we can use multiplexers (MUXes) controlled
by the two selection variables H1 and H0.

 Selection Variables: These two variables (H1, H0) will determine which operation is
performed.

o H1 = 0 and H0 = 0: Transfer all 0s to S.

o H1 = 0 and H0 = 1: Perform a shift left on F and store the result in S.

o H1 = 1 and H0 = 0: Perform a shift right on F and store the result in S.

o H1 = 1 and H0 = 1: Transfer the contents of F to S without any shift.

We will use 2-to-1 multiplexers to implement each of these operations. The multiplexers will
select between different inputs based on the values of H1 and H0.

Design using Multiplexers:

Block Diagram:

+-----------------+

| Multiplexer 1 |-------> S (Shifted result)

| (2-to-1 MUX) |

+-----------------+

+------------------+------------------+

| |

| |

+--------------+ +--------------+

| Input F (original) | MUX | Input 0 |

+--------------+ +--------------+

| |

| |

+------------------+------------------+

| Multiplexer 2 (2-to-1) |

+------------------+------------------+

| |

| |

+--------------+ +----------------+
| Shift Left | | Shift Right |

+--------------+ +----------------+

| |

| |

| |

+------------------+ +----------------+

| Input 0 | | Input 0 |

+------------------+ +----------------+

Explanation of Multiplexers:

1. Multiplexer 1 is responsible for choosing between 3 possible outputs:

o Input 0: All 0s to shift into S. This is used when H1 = 0 and H0 = 0.

o Shift Left (shl F): This will left-shift the bits in F. This happens when H1 = 0 and H0 =
1.

o Shift Right (shr F): This will right-shift the bits in F. This happens when H1 = 1 and H0
= 0.

The logic for Multiplexer 1 would be controlled by the H1 and H0 selection variables.

2. Multiplexer 2 is used to implement the shifting operations:

o When H1 = 0 and H0 = 1, the Shift Left (shl F) input is selected.

o When H1 = 1 and H0 = 0, the Shift Right (shr F) input is selected.

3. The function:

o When H1 = 0, H0 = 0: The output will be all 0s (i.e., S <- 0).

o When H1 = 0, H0 = 1: The output will be the result of shifting F left, i.e., S <- shl F.

o When H1 = 1, H0 = 0: The output will be the result of shifting F right, i.e., S <- shr F.

o When H1 = 1, H0 = 1: The output will be the contents of F transferred directly to S

without shifting (i.e., S <- F).