SN74HCT244-Q1

SCLS509C – JUNE 2003 – REVISED JUNE 2022

SN74HCT244-Q1 Octal Buffer and Line Driver With 3-State Outputs

1 Features 2 Description
• Qualified for automotive applications This octal buffer and line driver is designed
• ESD protection exceeds 1000 V per MIL-STD-883, specifically to improve both the performance and
Method 3015; exceeds 200 V using machine density of 3-state memory address drivers, clock
model (C = 200 pF, R = 0) drivers, and bus-oriented receivers and transmitters.
• Operating voltage range of 4.5 V to 5.5 V The ’HCT244 device is organized as two 4-bit buffers/
• High-current outputs drive up to 15 LSTTL loads drivers with separate output-enable (OE) inputs.
• Low power consumption, 80-μA max ICC When OE is low, the device passes noninverted data
• Typical tpd = 13 ns from the A inputs to the Y outputs. When OE is high,
• ±6-mA output drive at 5 V the outputs are in the high-impedance state.
• Low input current of 1 μA max
Device Information
• Inputs are TTL-voltage compatible (1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• 3-state outputs drive bus lines or buffer memory
address registers SN74HCT244QPW-Q1 TSSOP (20) 6.50 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCT244-Q1
SCLS509C – JUNE 2003 – REVISED JUNE 2022 www.ti.com

Table of Contents
1 Features............................................................................1 7.1 Overview..................................................................... 7
2 Description.......................................................................1 7.2 Functional Block Diagram........................................... 7
3 Revision History.............................................................. 2 7.3 Device Functional Modes............................................7
4 Pin Configuration and Functions...................................3 8 Power Supply Recommendations..................................8
5 Specifications.................................................................. 4 9 Layout...............................................................................8
5.1 Absolute Maximum Ratings........................................ 4 9.1 Layout Guidelines....................................................... 8
5.2 Recommended Operating Conditions(1) .................... 4 10 Device and Documentation Support............................9
5.3 Thermal Information....................................................4 10.1 Receiving Notification of Documentation Updates....9
5.4 Electrical Characteristics.............................................5 10.2 Support Resources................................................... 9
5.5 Switching Characteristics ...........................................5 10.3 Trademarks............................................................... 9
5.6 Switching Characteristics............................................5 10.4 Electrostatic Discharge Caution................................9
5.7 Operating Characteristics........................................... 5 10.5 Glossary....................................................................9
6 Parameter Measurement Information............................ 6 11 Mechanical, Packaging, and Orderable
7 Detailed Description........................................................7 Information...................................................................... 9

3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2022) to Revision C (June 2022) Page
• Junction-to-ambient thermal resistance values increased. PW was 83 is now 131.8........................................ 4

Changes from Revision A (February 2008) to Revision B (February 2022) Page

• Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect
modern data sheet standards............................................................................................................................. 1

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4 Pin Configuration and Functions

1OE 1 20 VCC
1A1 2 19 2OE
2Y4 3 18 1Y1
1A2 4 17 2A4
2Y3 5 16 1Y2
1A3 6 15 2A3
2Y2 7 14 1Y3
1A4 8 13 2A2
2Y1 9 12 1Y4
GND 10 11 2A1

PW Package
20-Pin TSSOP
Top View

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
IIK Input clamp current(2) VI < 0 or VI > VCC ± 20 mA
IOK Output clamp current(2) VO < 0 or VO > VCC ± 20 mA
IO Continuous output current VO = 0 to VCC ± 35 mA
Continuous current through VCC or GND ± 70 mA
TJ Junction temperature 150 ℃
Tstg Storage temperature range –65 150 ℃

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 Recommended Operating Conditions(1)

MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 V
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
Δt/Δv Input transition rise/fall time 500 ns
TA Operating free-air temperature −40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

5.3 Thermal Information

PW (TSSOP)
THERMAL METRIC 20 PINS UNIT
(1)
RθJA Junction-to-ambient thermal resistance 131.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 72.2 °C/W
RθJB Junction-to-board thermal resistance 82.8 °C/W
ψJT Junction-to-top characterization parameter 21.5 °C/W
ψJB Junction-to-board characterization parameter 82.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

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5.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
MIN TYP MAX
IOH = −20 μA 4.4 4.499 4.4
VOH VI = VIH or VIL 4.5 V V
IOH = −6 mA 3.98 4.3 3.7
IOL = 20 μA 0.001 0.1 0.1
VOL VI = VIH or VIL 4.5 V V
IOL = 6 mA 0.17 0.26 0.4
II VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 nA
IOZ VO = VCC or 0, VI = VIH or VIL 5.5 V ±0.01 ±0.5 ±10 μA
ICC VI = VCC or 0, IO = 0 5.5 V 8 160 μA
One input at 0.5 V or 2.4 V, 3
ΔICC (1) 5.5 V 1.4 2.4 mA
Other inputs at 0 or VCC
Ci 4.5 V to 5.5 V 3 10 10 pF

(1) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

5.5 Switching Characteristics

over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 6-1)
FROM TO TA = 25°C
PARAMETER VCC MIN MAX UNIT
(INPUT) (OUTPUT) MIN TYP MAX
4.5 V 15 28 42
tpd A Y ns
5.5 V 13 25 38
4.5 V 21 35 53
ten OE Y ns
5.5 V 19 32 48
4.5 V 19 35 53
tdis OE Y ns
5.5 V 18 32 48
4.5 V 8 12 18
tt Y ns
5.5 V 7 11 16

5.6 Switching Characteristics

over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 6-1)
FROM TO TA = 25°C
PARAMETER VCC MIN MAX UNIT
(INPUT) (OUTPUT) MIN TYP MAX
4.5 V 21 45 68
tpd A Y ns
5.5 V 18 40 61
4.5 V 25 52 79
ten OE Y ns
5.5 V 22 47 71
4.5 V 17 42 63
tt Y ns
5.5 V 14 38 57

5.7 Operating Characteristics

TA = 25℃
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per buffer/driver No load 40 pF

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6 Parameter Measurement Information

A. CL includes probe and test-fixture capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.

Figure 6-1. Load Circuit and Voltage Waveforms

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7 Detailed Description
7.1 Overview
This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state
memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT244 device is
organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device
passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-
impedance state.
7.2 Functional Block Diagram

7.3 Device Functional Modes

Table 7-1. Function Table
(Each Buffer/Driver)
INPUTS OUTPUT
OE A Y

L H H
L L L
H X Z

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8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

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10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com 30-Jun-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74HCT244QPWRG4Q1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HT244Q Samples

SN74HCT244QPWRQ1 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 HT244Q Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 30-Jun-2022

OTHER QUALIFIED VERSIONS OF SN74HCT244-Q1 :

• Catalog : SN74HCT244
• Enhanced Product : SN74HCT244-EP
• Military : SN54HCT244

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT244QPWRG4Q1 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74HCT244QPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1
SN74HCT244QPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

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TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT244QPWRG4Q1 TSSOP PW 20 2000 356.0 356.0 35.0
SN74HCT244QPWRQ1 TSSOP PW 20 2000 356.0 356.0 35.0
SN74HCT244QPWRQ1 TSSOP PW 20 2000 356.0 356.0 35.0

Pack Materials-Page 2
PACKAGE OUTLINE
PW0020A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
6.6 C
TYP PLANE
A 6.2
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1

2X
6.6 5.85
6.4
NOTE 3

10
11
0.30
20X
4.5 0.19 1.2 MAX
B
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE 0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220206/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN
PW0020A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

20X (1.5) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220206/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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