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4 views

Lab 3

Uploaded by

linhnguyen952756
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CP213 - Winter 2024 Lab 3: Gate-Level Minimization 1

Gate-Level Minimization
1 Overview
The gate-level implementation of a logic design has a direct impact on its cost, preformance, power, and
other considerations. Altough the truth table of a logic design is unique, up to reordering, it can correspond
to many different algebraic Boolean expressions and their gate-level realizations. In the previous lab, we
looked at using Boolean algebra postulates and theorems to simply algebraic Boolean functions. The Kar-
naugh maps (K-maps) represent a simple, and easy to use procedure for minimzing Boolean functions for
functions with 2, 3, or 4 variables. In this lab, you will experiement with using this method. Furthermore,
we highlighted in the previous lab that the most common gates used in practice are those of NAND and
NOR.
The learning objective of this lab can be summarized as follows:
1. Know how to obtain the sum of products and the product of sums forms of a Boolean function directly
from its Karnaugh map.
2. Know how to use don’t care conditions to simplify a Karnaugh map.
3. 3. Know how to form a two-level implementation of a Boolean function.

Reading and related topics: Chapter 3 of the textbook and the lecture notes.

2 Lab Tasks

Problem 1: Implement in the MultiMedia Logic/Logisim simulation tool the following Boolean function,
together with the don’t-care conditions d, using no more than two-level NOR gate circuits:
X
F (A, B, C, D) = (2, 4, 10, 11, 12, 14)
X
d(A, B, C, D) = (0, 1, 5, 8)
In this course, unless specified otherwise, we always use the don’t-care conditions the simplest possible
circuit realization.

Problem 3: Using K-map method, convert the following Boolean function from a sum-of-products form to
a simplified product-of-sums form.
X
F (w, x, y, z) = (0, 1, 2, 5, 8, 10, 13)

3 Submission Guideline
The labs must be done individually. Please note that you must attend the lab sessions. The TA may ask you
to go over your answers or simulation that you have submitted during those lab sessions. Your lab mustbe
submitted by the end of your lab session. You must submit your lab during your lab session to your TA.
Have Fun! ,
Ali Miri ©2024
Toronto Metropolitan University

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