118 Chapter 3 Gate-Level Minimization

A
B UDP_02467 E
C

F
D

FIGURE 3.37
Schematic for Circuit with_UDP_02467

Note that the variables listed on top of the table are part of a comment and are shown
only for clarity. The system recognizes the variables by the order in which they are listed
in the input declaration. A user-defined primitive can be instantiated in the construction
of other modules (digital circuits), just as the system primitives are used. For example,
the declaration
Circuit _with _UDP_ 02467 (E, F, A, B, C, D);
will produce a circuit that implements the hardware shown in Figure 3.37.
Although Verilog HDL uses this kind of description for UDPs only, other HDLs and
computer-aided design (CAD) systems use other procedures to specify digital circuits
in tabular form. The tables can be processed by CAD software to derive an efficient gate
structure of the design. None of Verilog’s predefined primitives describes sequential
logic. The model of a sequential UDP requires that its output be declared as a reg data
type, and that a column be added to the truth table to describe the next state. So the
columns are organized as inputs : state : next state.
In this section, we introduced the Verilog HDL and presented simple examples to
illustrate alternatives for modeling combinational logic. A more detailed presentation
of Verilog HDL can be found in the next chapter. The reader familiar with combina-
tional circuits can go directly to Section 4.12 to continue with this subject.

PROBLEMS

(Answers to problems marked with * appear at the end of the text.)

3.1* Simplify the following Boolean functions, using three-variable maps:
(a) F 1x, y, z2 = ⌺10, 2, 4, 52 (b) F 1x, y, z2 = ⌺10, 2, 4, 5, 62
(c) F 1x, y, z2 = ⌺10, 1, 2, 3, 52 (d) F 1x, y, z2 = ⌺11, 2, 3, 72
3.2 Simplify the following Boolean functions, using three-variable maps:
(a)* F (x, y, z) = ⌺(0, 1, 5, 7) (b)* F (x, y, z) = ⌺(1, 2, 3, 6, 7)
(c) F 1x, y, z2 = ⌺12, 3, 4, 52 (d) F 1x, y, z2 = ⌺11, 2, 3, 5, 6, 72
(e) F 1x, y, z2 = ⌺10, 2, 4, 62 (f) F 1x, y, z2 = ⌺13, 4, 5, 6, 72
3.3* Simplify the following Boolean expressions, using three-variable maps:
(a)* xy + x⬘ y⬘ z⬘ + x⬘ yz⬘ (b)* x⬘ y⬘ + yz + x⬘yz⬘
(c)* F 1x, y, z2 = x⬘y + yz⬘ + y⬘z⬘ (d) F 1x, y, z2 = x⬘yz + xy⬘z⬘ + xy⬘z
Problems 119

3.4 Simplify the following Boolean functions, using Karnaugh maps:

(a)* F (x, y, z) = ⌺(2, 3, 6, 7) (b)* F (A, B, C, D) = ⌺(4, 6, 7, 15)
(c)* F (A, B, C, D) = ⌺(3, 7, 11, 13, 14, 15) (d)* F (w, x, y, z) = ⌺(2, 3, 12, 13, 14, 15)
(e) F (w, x, y, z) = ⌺ (11, 12, 13, 14, 15) (f) F (w, x, y, z) = ⌺(8, 10, 12, 13, 14)
3.5 Simplify the following Boolean functions, using four-variable maps:
(a)* F (w, x, y, z) = ⌺ (1, 4, 5, 6, 12, 14, 15)
(b) F (A, B, C, D) = ⌺(2, 3, 6, 7, 12, 13, 14)
(c) F (w, x, y, z) = ⌺ (1, 3, 4, 5, 6, 7, 9, 11, 13, 15)
(d)* F (A, B, C, D) = ⌺ (0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
3.6 Simplify the following Boolean expressions, using four-variable maps:
(a)* A⬘B⬘ C⬘ D⬘ + AC⬘D⬘ + B⬘ CD⬘ + A⬘ BCD + BC⬘ D
(b)* x⬘z + w⬘ xy⬘ + w(x⬘y + xy⬘)
(c) A⬘B⬘C⬘D + AB⬘D + A⬘BC⬘ + ABCD + AB⬘C
(d) A⬘B⬘C⬘D⬘ + BC⬘D + A⬘C⬘D + A⬘BCD + ACD⬘
3.7 Simplify the following Boolean expressions, using four-variable maps:
(a)* w⬘ z + xz + x⬘ y + wx⬘ z
(b) AD⬘ + B⬘C⬘D + BCD⬘ + BC⬘D
(c)* AB⬘ C + B⬘ C⬘D⬘ + BCD + ACD⬘ + A⬘B⬘ C + A⬘ BC⬘D
(d) wxy + xz + wx⬘z + w⬘x
3.8 Find the minterms of the following Boolean expressions by first plotting each function in
a map:
(a)* xy + yz + xy⬘ z (b)* C⬘D + ABC⬘ + ABD⬘ + A⬘B⬘D
(c) wyz + w⬘x⬘ + wxz⬘ (d) A⬘B + A⬘CD + B⬘CD + BC⬘D⬘
3.9 Find all the prime implicants for the following Boolean functions, and determine which
are essential:
(a)* F (w, x, y, z) = ⌺ (0, 2, 4, 5, 6, 7, 8, 10, 13, 15)
(b)* F (A, B, C, D) = ⌺ (0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
(c) F 1A, B, C, D2 = ⌺ 12, 3, 4, 5, 6, 7, 9, 11, 12, 132
(d) F 1w, x, y, z2 = ⌺ 11, 3, 6, 7, 8, 9, 12, 13, 14, 152
(e) F 1A, B, C, D2 = ⌺ 10, 1, 2, 5, 7, 8, 9, 10, 13, 152
(f) F 1w, x, y, z2 = ⌺ 10, 1, 2, 5, 7, 8, 10, 152
3.10 Simplify the following Boolean functions by first finding the essential prime implicants:
(a) F 1w, x, y, z2 = ⌺ 10, 2, 5, 7, 8, 10, 12, 13, 14, 152
(b) F (A, B, C, D) = ⌺(0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
(c)* F (A, B, C, D) = ⌺(1, 3, 4, 5, 10, 11, 12, 13, 14, 15)
(d) F 1w, x, y, z2 = ⌺ 10, 1, 4, 5, 6, 7, 9, 11, 14, 152
(e) F 1A, B, C, D2 = ⌺ 10, 1, 3, 7, 8, 9, 10, 13, 152
(f) F 1w, x, y, z2 = ⌺ 10, 1, 2, 4, 5, 6, 7, 10, 152
3.11 Convert the following Boolean function from a sum-of-products form to a simplified
product-of-sums form.
F 1x, y, z2 = ⌺ 10, 1, 2, 5, 8, 10, 132
120 Chapter 3 Gate-Level Minimization

3.12 Simplify the following Boolean functions:

(a)* F 1A, B, C, D2 = ⌸ 11, 3, 5, 7, 13, 152
(b) F 1A, B, C, D2 = ⌸ 11, 3, 6, 9, 11, 12, 142
3.13 Simplify the following expressions to (1) sum-of-products and (2) products-of-sums:
(a)* x⬘ z⬘ + y⬘ z⬘ + yz⬘ + xy
(b) ACD⬘ + C⬘D + AB⬘ + ABCD
(c) 1A⬘ + B + D⬘2 1A⬘ + B⬘ + C⬘2 1A⬘ + B⬘ + C2 1B⬘ + C + D⬘2
(d) BCD⬘ + ABC⬘ + ACD
3.14 Give three possible ways to express the following Boolean function with eight or fewer literals:
F = A⬘BC⬘D + AB⬘CD + A⬘B⬘C⬘ + ACD⬘

3.15 Simplify the following Boolean function F, together with the don’t-care conditions d, and
then express the simplified function in sum-of-minterms form:
(a) F 1x, y, z2 = ⌺10, 1, 4, 5, 62 (b)* F (A, B, C, D) = ⌺(0, 6, 8, 13, 14)
d1x, y, z2 = ⌺12, 3, 72 d (A, B, C, D) = ⌺(2, 4, 10)
(c) F 1A, B, C, D2 = ⌺15, 6, 7, 12, 14, 15,2 (d) F 1A, B, C, D2 = ⌺14, 12, 7, 2, 10,2
d1A, B, C, D2 = ⌺13, 9, 11, 152 d1A, B, C, D2 = ⌺10, 6, 82
3.16 Simplify the following functions, and implement them with two-level NAND gate circuits:
(a) F 1A, B, C, D2 = AC⬘D⬘ + A⬘C + ABC + AB⬘C + A⬘C⬘D⬘
(b) F 1A, B, C, D2 = A⬘B⬘C⬘D + CD + AC⬘D
(c) F 1A, B, C2 = 1A⬘ + C⬘ + D⬘2 1A⬘ + C⬘2 1C⬘ + D⬘2
(d) F 1A, B, C, D2 = A⬘ + B + D⬘ + B⬘C
3.17* Draw a NAND logic diagram that implements the complement of the following function:
F 1A, B, C, D2 = ⌺ 10, 1, 2, 3, 6, 10, 11, 142
3.18 Draw a logic diagram using only two-input NOR gates to implement the following function:
F 1A, B, C, D2 = (A { B)'(C { D)
3.19 Simplify the following functions, and implement them with two-level NOR gate circuits:
(a)* F = wx⬘ + y⬘ z⬘ + w⬘ yz⬘
(b) F 1w, x, y, z2 = ⌺ 10, 3, 12, 152
(c) F (x, y, z) = [(x + y)(x = z)]⬘
3.20 Draw the multiple-level NOR circuit for the following expression:
CD1B + C2A + 1BC⬘ + DE⬘2
3.21 Draw the multiple-level NAND circuit for the following expression:
w 1x + y + z2 + xyz
3.22 Convert the logic diagram of the circuit shown in Fig. 4.4 into a multiple-level NAND circuit.
3.23 Implement the following Boolean function F, together with the don’t-care conditions d,
using no more than two NOR gates:
F 1A, B, C, D2 = ⌺ 12, 4, 10, 12, 14,2
d1A, B, C, D2 = ⌺ 10, 1, 5, 82
Assume that both the normal and complement inputs are available.
Problems 121

3.24 Implement the following Boolean function F, using the two-level forms of logic (a) NAND-
AND, (b) AND-NOR, (c) OR-NAND, and (d) NOR-OR:
F 1A, B, C, D2 = ⌺ 10, 4, 8, 9, 10, 11, 12, 142

3.25 List the eight degenerate two-level forms and show that they reduce to a single operation.
Explain how the degenerate two-level forms can be used to extend the number of inputs
to a gate.
3.26 With the use of maps, find the simplest sum-of-products form of the function F = fg, where
f = abc⬘ + c⬘d + a⬘cd⬘ + b⬘cz⬘
and
g = 1a + b + c⬘ + d⬘2 1b⬘ + c⬘ + d2 1a⬘ + c + d⬘2
3.27 Show that the dual of the exclusive-OR is also its complement.
3.28 Derive the circuits for a three-bit parity generator and four-bit parity checker using an odd
parity bit.
3.29 Implement the following four Boolean expressions with three half adders:
D = A{B{C
E = A⬘ BC + AB⬘ C
F = ABC⬘ + (A⬘ + B⬘) C
G = ABC
3.30* Implement the following Boolean expression with exclusive-OR and AND gates:
F = AB⬘ CD⬘ + A⬘ BC D⬘ + AB⬘ C⬘ D + A⬘ BC⬘ D
3.31 Write a Verilog gate-level description of the circuit shown in
(a) Fig. 3.20(a) (b) Fig. 3.20(b) (c) Fig. 3.21(a)
(d) Fig. 3.21(b) (e) Fig. 3.24 (f) Fig. 3.25
3.32 Using continuous assignment statements, write a Verilog description of the circuit
shown in
(a) Fig. 3.20(a) (b) Fig. 3.20(b) (c) Fig. 3.21(a)
(d) Fig. 3.21(b) (e) Fig. 3.24 (f) Fig. 3.25
3.33 The exclusive-OR circuit of Fig. 3.30(a) has gates with a delay of 3 ns for an inverter, a 6 ns
delay for an AND gate, and a 8 ns delay for an OR gate. The input of the circuit goes from
xy = 00 to xy = 01.
(a) Determine the signals at the output of each gate from t = 0 to t = 50 ns.
(b) Write a Verilog gate-level description of the circuit, including the delays.
(c) Write a stimulus module (i.e., a test bench similar to HDL Example 3.3), and simulate
the circuit to verify the answer in part (a).
3.34 Using continuous assignments, write a Verilog description of the circuit specified by the
following Boolean functions:
Out_1 = 1A + B⬘2C⬘ 1C + D2
Out_2 = 1C⬘D + BCD + CD⬘2 1A⬘ + B2
Out_3 = 1AB + C2D + B⬘C

Write a test bench and simulate the circuit’s behavior.

122 Chapter 3 Gate-Level Minimization

3.35* Find the syntax errors in the following declarations (note that names for primitive gates
are optional):

module Exmpl-3(A, B, C, D, F) // Line 1

inputs A, B, C, Output D, F, // Line 2
output B // Line 3
and g1(A, B, D); // Line 4
not (D, A, C), // Line 5
OR (F, B; C); // Line 6
endmodule; // Line 7

3.36 Draw the logic diagram of the digital circuit specified by the following Verilog description:

(a) module Circuit_A (A, B, C, D, F);

input A, B, C, D;
output F;
wire w, x, y, z, a, d;
or (x, B, C, d);
and (y, a ,C);
and (w, z ,B);
and (z, y, A);
or (F, x, w);
not (a, A);
not (d, D);
endmodule

(b) module Circuit_B (F1, F2, F3, A0, A1, B0, B1);
output F1, F2, F3;
input A0, A1, B0, B1;
nor (F1, F2, F3);
or (F2, w1, w2, w3);
and (F3, w4, w5);
and (w1, w6, B1);
or (w2, w6, w7, B0);
and (w3, w7, B0, B1);
not (w6, A1);
not (w7, A0);
xor (w4, A1, B1);
xnor (w5, A0, B0);
endmodule

(c) module Circuit_C (y1, y2, y3, a, b);

output y1, y2, y3;
input a, b;

assign y1 = a || b;
and (y2, a, b);
assign y3 = a && b;
endmodule
References 123

3.37 A majority logic function is a Boolean function that is equal to 1 if the majority of the
variables are equal to 1, equal to 0 otherwise.
(a) Write a truth table for a four-bit majority function.
(b) Write a Verilog user-defined primitive for a four-bit majority function.
3.38 Simulate the behavior of Circuit_with_UDP_02467, using the stimulus waveforms shown
in Fig. P3.38.

t, ns
10 20 30 40 50 60 70 80
B

t, ns
10 20 30 40 50 60 70 80

C
t, ns
10 20 30 40 50 60 70 80
D

t, ns
10 20 30 40 50 60 70 80

FIGURE P3.38
Stimulus waveforms for Problem 3.38

3.39 Using primitive gates, write a Verilog model of a circuit that will produce two outputs,
s and c, equal to the sum and carry produced by adding two binary input bits a and b (e.g.,
s = 1 and c = 0 if a = 0 and b = 1). (Hint: Begin by developing a truth table for s and c.)

REFERENCES
1. Bhasker, J. 1997. A Verilog HDL Primer. Allentown, PA: Star Galaxy Press.
2. Ciletti, M. D. 1999. Modeling, Synthesis and Rapid Prototyping with the Verilog HDL.
Upper Saddle River, NJ: Prentice Hall.
3. Hill, F. J., and G. R. Peterson. 1981. Introduction to Switching Theory and Logical Design,
3rd ed. New York: John Wiley.
4. IEEE Standard Hardware Description Language Based on the Verilog Hardware Descrip-
tion Language (IEEE Std. 1364-1995). 1995. New York: The Institute of Electrical and
Electronics Engineers.
5. Karnaugh, M. A Map Method for Synthesis of Combinational Logic Circuits. Transactions
of AIEE, Communication and Electronics. 72, part I (Nov. 1953): 593–99.
6. Kohavi, Z. 1978. Switching and Automata Theory, 2nd ed. New York: McGraw-Hill.
  27  

Chapter 3
3.1
yz y yz y
x 00 01 11 10 x 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
0 1 1 0 1 1
m4 m5 m7 m6 m4 m5 m7 m6
x 1 1 1 x 1 1 1 1

z z
F = xy' + x'z' F = z' + xy'

yz y yz y
x 00 01 11 10 x 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
0 1 1 1 1 0 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
x 1 1 x 1 1

z z
F = x' + y'z F = x'z + yz + x'y

 
3.2

yz y yz y
x 00 01 11 10 x 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
0 1 1 0 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
x 1 1 1 x 1 1 1

z z
(a) F = x'y' + xz (b) F = y + x'z

y yz y
yz
x x
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
0 1 1 0 1 1 1

m4 m5 m7 m6 m4 m5 m7 m6
x 1 1 1 x 1 1 1 1

z z

F = xy' + x'y F=y+z

(c) (d)

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  28  

y yz y
yz
x x
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
0 1 1 0 1

m4 m5 m7 m6 m4 m5 m7 m6
x 1 1 1 x 1 1 1 1 1

z z

F = z' F=x+yz

(e) (f)

 
3.3

yz y yz y
x x
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
0 1 1 0 1 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
x 1 1 1 x 1 1

z z
(a) F =xy + x'y'z' + x'yz' (b) F = x'y' + yz + x'yz'
F = xy + x' z' F = x' + yz

yz y yz
x x
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
0 1 1 1 0 1

m4 m5 m7 m6 m4 m5 m7 m6
x 1 1 1 x 1 1 1

z z
F = x'y + yz' + y'z' F = x'yz + xy'z' + xy'z
F = = x' y + z' F = x'yz + xy'

(c) (d)

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  29  

3.4    
CD C
AB
00 01 11 10
m0 m1 m3 m2
00
m4 m5 m7 m6
yz y
x 01 1 1 1
00 01 11 10 B
m0 m1 m3 m2 m12 m13 m15 m14
0 1 1 11 1
m4 m5 m7 m6 A m8 m9 m11 m10
x 1 1 1 10

z D
      (a) F=y (b) F = BCD + A' BD'  

CD C yz y
AB 00 01 11 10 wx 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 01
m12 m13 m15 m14 B m12 m13 m15 m14 x
11 1 1 1 11 1 1 1 1
A m8 m9 m11 m10 w m8 m9 m11 m10
10 1 10

D z
(c) F =CD + ABD + ABC (d) F = w'x'y +wx  
 
yz y yz y
wx wx
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 00
m4 m5 m7 m6 m4 m5 m7 m6
01 01
m12 m13 m15 m14 x m12 m13 m15 m14 x
11 1 1 1 11 1 1 1
w m8 m9 m11 m10 w m8 m9 m11 m10
10 1 10 1 1

z z
F = wx + wyz F = wz' + xy'w  
 
(e)                             (f)  

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3.5  

yz y CD C
wx AB
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 1 01 1 1
m12 m13 m15 m14 x m12 m13 m15 m14 B
11 1 1 1 11 1 1 1
w m8 m9 m11 m10 A m8 m9 m11 m10
10 10

z D
(a) F =xz' + w'y'z+ wxy (b) F = AC' + ABC' + ABD'

yz y CD C
wx AB
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 1 1 01 1 1 1 1
m12 m13 m15 m14 x m12 m13 m15 m14 B
11 1 1 11 1 1
w m8 m9 m11 m10 A m8 m9 m11 m10
10 1 1 10 1

z D
(c) F = z + xw' (d) F =BD + A'B + B' D'
or = BD + B'D' + A'D'

 
3.6

CD C yz y
AB wx
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 x
11 1 1 11 1 1
A m8 m9 m11 m10 w m8 m9 m11 m10
10 1 1 10 1 1 1

D z
(a) F = B' D' +A'BD + ABC' (b) F = xy' +x'z + wx'y

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  31  

CD C CD C
AB AB
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 1 11 1
A m8 m9 m11 m10 A m8 m9 m11 m10
10 1 1 1 10 1

D D
(d) F = C'D + A'BD + A'B'C'
(c) F = A'BC' + B'C'D + ACD + AB'C

3.7

yz y CD C
wx AB
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 1 00 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
m12 m13 m15 m14 x m12 m13 m15 m14 B
11 1 1 11 1 1 1
w m8 m9 m11 m10 A m8 m9 m11 m10
10 1 1 1 10 1 1 1

z D
(a) F = z + x'y (b) F = AD' + C'D + BCD'

CD C yz y
AB 00 01 11 10 wx 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 1 00
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 x
11 1 1 11 1 1 1
A m8 m9 m11 m10 w m8 m9 m11 m10
10 1 1 1 10

D z
(c) F = B'D' + AC + A'BD + CD (or B'C) (d) F = xw' + xz + xy  
 
 

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  32  

3.8    
(a) F(x, y, z) = Σ(3, 5, 6, 7)

yz y
x 00 01 11 10
m0 m1 m3 m2
0 1
m4 m5 m7 m6
x 1 1 1 1

(b) F = Σ(1, 3, 5, 9, 12, 13, 14)

CD C
AB 00 01 11 10
m0 m1 m3 m2
00 1 1
m4 m5 m7 m6
01 1
m12 m13 m15 m14 B
11 1 1 1
A m8 m9 m11 m10
10 1

D  
 
(c) F = Σ(0, 1, 2, 3, 11, 12, 14, 15)

y
wx 00 01 11 10
m0 m1 m3 m2
00 1 1 1 1
m4 m5 m7 m6
01
m12 m13 m15 m14 x
11 1 1 1
w m8 m9 m11 m10
10 1

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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  33  

(d) F = Σ(3, 4, 5, 7, 11, 12)

CD C
AB 00 01 11 10
m0 m1 m3 m2
00 1
m4 m5 m7 m6
01 1 1 1
m12 m13 m15 m14 B
11 1
A m8 m9 m11 m10
10 1

D
3.9

yz y CD C
wx AB
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 1 1 01 1 1
m12 m13 m15 m14 x m12 m13 m15 m14 B
11 1 1 11 1 1
w m8 m9 m11 m10 A m8 m9 m11 m10
10 1 1 10 1 1 1

z D

(a) (b)

Essential: xz, x'z' Essential: B'D', AC, A'BD

Non-essential: w'x, w'z' Non-essential: CD, B'C
F = xz + x'z' + (w'x or w'z') F = B'D' + AC + A'BD + (CD OR B'C)

CD C yz y
AB wx
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 1 1 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 x
11 1 1 11 1 1 1 1
A m8 m9 m11 m10 w m8 m9 m11 m10
10 1 1 10 1 1

D z

(c) (d)

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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  34  

Essential: BC', AC, A'B'D Essential: wy', xy, w'x'z

Non-Essential: A'B
F = BC' + AC + A'B'D F = wy' + xy + w'x'z

CD C yz y
AB wx
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 1 00 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
m12 m13 m15 m14 B m12 m13 m15 m14 x
11 1 1 11 1
A m8 m9 m11 m10 w m8 m9 m11 m10
10 1 1 1 10 1 1

D z

      Essential: BD, B'C', C'D Essential: x'z', w'y'z, xyz

F = BD + B'C' + C'D F = x'z' + w'y'z + xyz
 
 
3.10

yz y CD C
wx AB
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1
m12 m13 m15 m14 x m12 m13 m15 m14 B
11 1 1 1 1 11 1 1
w m8 m9 m11 m10 A m8 m9 m11 m10
10 1 1 10 1 1 1

z D  
 
F = Σ(0, 2, 5, 7, 8, 10, 12, 13, 14, 15) F = Σ(0, 2, 3, 5, 7, 8, 10, 11, 14, 15)
Essential: xz, wx, x'z' Essential: AC, B'D', CD, A'BD
F = xz + wx + x'z' F = AC + B'D' + CD + A'BD
       
              (a)                                       (b)  

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  35  

CD C yz y
AB wx
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1

m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1 1 1
B m12 m13 m15 m14 x
m12 m13 m15 m14
11 1 1 1 1 11 1 1
A w m8 m9 m11 m10
m8 m9 m11 m10
10 1 1 10 1 1

z
D

F = Σ(1, 3, 4, 5, 10, 11, 12, 13, 14, 15) F = Σ(0, 1, 4, 5, 6, 7, 9, 11, 14, 15)
Essential: AC, BC', A'B'D Essential: w'y', xy, wx'z
Non-essential: AB, Aʹ′Bʹ′D, Bʹ′CD, Aʹ′Cʹ′D Non-essential: wx, x'y'z, w'wz, w'x'z
F = AC + BCʹ′ + Aʹ′Bʹ′D F = w'y' + xy + wx'z
 
            (c)                                         (d)  
 
CD C yz y
AB wx
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 1 00 1 1 1

m4 m5 m7 m6 m4 m5 m7 m6
01 1 01 1 1 1 1
B m12 m13 m15 m14 x
m12 m13 m15 m14
11 1 1 11 1
A w m8 m9 m11 m10
m8 m9 m11 m10
10 1 1 1 10 1

z
D  
F(A, B, C, D) = S(0, 1, 3, 7 8, 9, 10,13,15) F = S(0, 1, 2, 4, 5, 6, 7, 10, 15)
Essential: B'C', AB'D' Essential: w'y', w'z', xyz, x'yz'
Non-essential: ABD, A'CD, BCD Non-Essential: w'x
      F = B'C' + AB'D' +A'CD +ABD F = w'y' + w'z' + xyz + x'yz'

(e) (f)

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3.11   (a)  F(w,  x,  y,  z)  =  ∑  (0,  1,  2,  5,  8,  10,  13)  
 
 
yz y yz y
wx wx
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 1 00 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 01 1 1 1
m12 m13 m15 m14 x m12 m13 m15 m14 x
11 1 11 1 1 1
w m8 m9 m11 m10 w m8 m9 m11 m10
10 1 1 10 1 1

  z z  
          F  =  x'z'  +  w'x'y'  +  xy'z           F'  =  yz  +  xy  +  xz'  +  wx'z  
                              F    =  (y'  +  z')(x'  +  y')(x'  +  z)(w'  +x  +  z')  

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3.12 (a)  
F = Π(1, 3, 5, 7, 13, 15)
F' = A'D + B'D
F = (A + Dʹ′)(Bʹ′ + Dʹ′)
F = C'D' + AB' + CD'
CD C
AB 00 01 11 10
m0 m1 m3 m2
00 0 0
m4 m5 m7 m6
01 0 0
m12 m13 m15 m14 B
11 0 0
A m8 m9 m11 m10
10

D  
 

(b)

F = Π(1, 3, 6, 9, 11, 12, 14)

F' = B'D + BCD' + ABD'
F = (B + D')(B' + C' + D)(A' + B' + D)
F = BD + B'D' + A'C'D'

CD C
AB 00 01 11 10
m0 m1 m3 m2
00 0 0
m4 m5 m7 m6
01 0
m12 m13 m15 m14 B
11 0 0
A m8 m9 m11 m10
10 0 0

D
 

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  38  

3.13   (a) F = x'z' + y'z' + yz' + xy = x'z' + z' + xy = z' + xy

yz y
x 00 01 11 10
m0 m1 m3 m2
0 1 1
m4 m5 m7 m6
x 1 1 1 1

z
F' = x'z + y'z
F = (x + z')(y + z')

 
      (b) F = ACD' + C'D + AB' + ABCD

CD C
AB 00 01 11 10
m0 m1 m3 m2
00 1
m4 m5 m7 m6
01 1
m12 m13 m15 m14 B
11 1 1 1
A m8 m9 m11 m10
10 1 1 1 1

D
F = AC + AB' + C'D
F' = A'C + A'D' + BC'D'
F = (A + C')(A + D)(B'+C + D)

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(c)

F = (A' + B + D')(A' + B' + C')(A' + B' + C)(B' + C + D')

F' = AB'D + ABC + ABC' + BC'D

CD C
AB 00 01 11 10
m0 m1 m3 m2
00 0 0
m4 m5 m7 m6
01 0
m12 m13 m15 m14 B
11 0 0 0 0
A m8 m9 m11 m10
10

F' = AB + BC'D
F = (A' + B')(B' + C + D')

F = A'D' + A'BC + AB'

CD C
AB 00 01 11 10
m0 m1 m3 m2
00 1 0 0 1
m4 m5 m7 m6
01 1 0 1 1
m12 m13 m15 m14 B
11 0 0 0 0
A m8 m9 m11 m10
10 1 1 1 1

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(d)

F = BCD' + ABC' + ACD

CD C CD C
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 00 0 0 0 0
m4 m5 m7 m6 m4 m5 m7 m6
01 1 01 0 0 0
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 1 1 1 11 0
A m8 m9 m11 m10 A m8 m9 m11 m10
10 1 10 0 0 0

D D

F' = A'C' + A'D + B'C' + A'B' + ACD'\

F = (A + C)(A + D') (B + C)(A + B)(A' +C' + D)

3.14

CD C CD C
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 0 0
m4 m5 m7 m6 m4 m5 m7 m6
01 1 01 0 0 0
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 1 11 0 0 0
A m8 m9 m11 m10 A m8 m9 m11 m10
10 1 1 10 0 0

D D

SOP form (using 1s): F = A'BC'D + AB'CD + A'B'C' + ACD'

F = A'B'C' + A'C'D + AB'C + ACD'

POS form (using 0s): F' = AC' + A'C + A'C'D' + ABD

F = (A' + C)(A + C')(A + C + D)(A' + B' + D')

Alternative POS: F' = AC' + A'C + A'C'D' + BCD

F = (A' + C)(A + C')(A + C + D)(B' + C' + D')
 

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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  41  

3.15

CD C
AB 00 01 11 10
m0 m1 m3 m2
00 1 x
m4 m5 m7 m6
yz y
01 x 1
x 00 01 11 10
m0 m1 m3 m2 m12 m13 m15 m14 B
0 1 1 x x 11 1 1
m4 m5 m7 m6
A m8 m9 m11 m10
x 1 1 1 x 1 10 1 x

z
D  
F=1 F = A'D' + B'D' + BCD' + ABC'D
F = Σ(0,1, 2, 3, 4, 5, 6, 7) F = Σ(0, 2, 4, 6, 8, 10, 13, 14)

CD C CD C
AB 00 01 11 10 AB 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 x 00 x 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 1 01 1 1 x
m12 m13 m15 m14 B m12 m13 m15 m14 B
11 1 1 1 11 1
A m8 m9 m11 m10 A m8 m9 m11 m10
10 x x 10 x 1

D D  
 
F = BC + CD + ABD' + A'BD F = B'D' + C'D' + A'BC
F = Σ(3, 5, 6, 7, 11, 12, 14, 15) F = F = Σ(0, 2, 4, 6, 7, 8, 10, 12)
 
 
3.16 (a)

CD C
AB 00 01 11 10
m0 m1 m3 m2 F = C + D'
00 1 1 1 F = (C'D)'
m4 m5 m7 m6
01 1 1 1
m12 m13 m15 m14 B D'
F
11 1 1 1 C
A m8 m9 m11 m10
10 1 1 1

D  

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(b)

CD C
AB 00 01 11 10
m0 m1 m3 m2 F = AD + B'D + CD
00 1 1 F = ((AD)' (B'D)' (CD)')'
m4 m5 m7 m6 A
01 1 D
m12 m13 m15 m14 B B'
11 1 1 F
D
A m8 m9 m11 m10
C
10 1 1 D

(c) F = (A' + C' + D')(A' + C')(C' + D')

F' = (A' + C' + D')' + (A' + C')' + (C' + D')'
F' = ACD + AC + CD

CD C
AB 00 01 11 10 F = C' + A'D'
m0 m1 m3 m2 F = (C(A + D))'
00 1 1 0 1 F = (C(A'D')')'
m4 m5 m7 m6
01 1 1 0 1 C

m12 m13 m15 m14 B

11 1 1 0 0 F
A m8 m9 m11 m10 A'
10 1 1 0 0 D'

        D  
 
      (d)
CD C
AB F = A' + B + D'
00 01 11 10
m0 m1 m3 m2 F = (A(B')D)'
00 1 1 1 1
m4 m5 m7 m6
A
01 1 1 1 1
m12 m13 m15 m14 B B' F
11 1 1 1 1
A m8 m9 m11 m10
D
10 1 1

D
 

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3.17

CD C
AB 00 01 11 10
m0 m1 m3 m2
A'
00 1 1 1 1
B'
m4 m5 m7 m6
01 1 B'
B C F'
m12 m13 m15 m14
11 1
A m8 m9 m11 m10
C
10 1 1 D'

F = A'B' + B'C + CD'

F = ((A + B)(B + C') (C' + D))'
F = ((A'B')'(B'C)'(CD')' )'
F' = (A'B')'(B'C)'(CD')'  
 
3.18 F = (A ⊕ B)'(C ⊕ D) = (AB' + A'B)'(CD' + C'D)
= (AB + A'B')(CD' + C'D) = ABCD' + ABC'D + A'B'CD' + A'B'C'D
F' = (AB + A'B')' + (CD' + C'D)'
F' = ( (A' + B')' + (A + B)' )' + ( (C' + D)' + (C + D')' )'

CD C
AB
00 01 11 10
m0 m1 m3 m2 A'
00 1 1 B'
m4 m5 m7 m6 A
01 B
F'
m12 m13 m15 m14 B
C'
11 1 1 D
A m8 m9 m11 m10
C
10 D'

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3.19   (a) F = (w + zʹ′)(xʹ′ + zʹ′)(wʹ′ + xʹ′ + yʹ′)

 
yz y
wx 00 01 11 10
m0 m1 m3 m2
00 1 1 y
z
m4 m5 m7 m6
01 1 1 w
x
m12 m13 m15 m14 x F
11 1 w
w m8 m9 m11 m10 z
10 1 1 1 1

z  
        F = y'z' + wx' + w'z'
F =[(y + z)' + (w' + x)' + (w + z)']
F' =[(y + z)' + (w' + x)' + (w + z)']'

      (b)
yz y
wx 00 01 11 10
m0 m1 m3 m2 y
00 1 1 z'
m4 m5 m7 m6 y'
01 z
x F'
m12 m13 m15 m14
w
11 1 1 x'
w m8 m9 m11 m10
w'
10 x

z  
      F = Σ(0, 3, 12, 15)
F' =y'z+yz' + w'x + wx' = [(y + z')(w + x')(w + x')(w' + x)]'
F = (y + z')' + (y' + z)' + (w + x')' + (w' + x)'

      (c) F = [(x + y)(x' + z)]' = (x + y)' + (x' + z)'

F' = [(x + y)' + (x' + z)']'
x
y
F'
x'
z
 
 
 

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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  45  

3.20 Multi-level NOR:

   
F = ACD(B + C) + (BC' + DE')
F' = [ACD(B + C) + (BC' + DE')]'
F' = [(A' + C' + D')'(B + C) + (B' + C)' + (D' + E)']'
F' = [((A' + C' + D') + (B + C)' )' + (B' + C)' + (D' + E)']'
F' = [(A' + C' + D' + (B + C)')' + (B' + C)' + (D' + E)']'

A'

C'
D'
B
C

B' F'
C

D'
E

Multi-level NAND:

F = CD(B + C)A + (BC' + DE')

F' = [CD(B + C)A]' [BC' + DE']'
F' = [CD(B'C')'A]' [BC' + DE']'
F' = [CD(B'C')'A]' [[ (BC')' (DE')]' ]'
 
B'

C'
A
C
D F
B
C'

D
E'

3.21 F = w(x + y + z) + xyz

F' = [w(x + y + z)]'[xyz]' = [w(x'y'z')')]'(xyz)'

x
y
z
x'
y' F

z'
w

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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  46  

3.22
 

D
C y

B
x

 
 
 
 
z

D
C y

B
x

A
 

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  47  

3.23

 
CD C
AB
00 01 11 10
m0 m1 m3 m2
00 x x 1
m4 m5 m7 m6 A
01 1 x B'
m12 m13 m15 m14 B
C' F
11 1 1
D
A m8 m9 m11 m10
10 x 1

D  
F = B'D' + AD' + C'D'
F' = D + A'BC
F = [D + A'BC]' = [D + (A + B' + C')']'
 
 
3.24 F(A, B, C, D) = S(0, 4, 8, 9, 10, 11, 12, 14)
 
CD C
AB 00 01 11 10
m0 m1 m3 m2
00 1
m4 m5 m7 m6
01 1
m12 m13 m15 m14 B
11 1 1
A m8 m9 m11 m10
10 1 1 1 1

D  
(a) F = C'D' + AB' + AD'
F' = (C'D')'(AB')'(AD')'
AND-NAND:
C'
D'
A F
B'

A
D'

(b) F' = [C'D' + AB' + AD']'

AND-NOR:

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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  48  

C'
D'
A F’
B'

A
D'

(c) F = C'D' + AB' + AD' = (C + D)' + (A' + B)' + (A' + D)'

F' = (C'D')'(AB')'(AD')' = (C + D)(A' + B)(A' + D)
F = [ (C + D)(A' + B)(A' + D) ]'
OR-NAND:
C
D
A' F
B

A'
D

(d) F = C'D' + AB' + AD' = (C + D)' + (A' + B)' + (A' + D)'

NOR-OR:
C
D
A' F
B

A'
D

3.25
A
B A
B
ABCD A+B+C+D
C
C
D D
AND-AND AND OR-OR OR  
 
A
B A
B
(AB CD)' (A + B + C + D)'
C
C
D D
AND-NAND NAND OR-NOR NOR  
 
A
B A
B
(A'B'C'D')' [(AB)' + (C' D')]'
C
C
D A+B+C+D D ABCD

NOR-NAND OR NAND-NOR AND  

 

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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  49  

A'B'
A
A
B B
A'B'C'D'
C A' + B' + C' + D'
C
D C'D' (A + B + C + D)' D (A + B + C + D)'

NOR-AND NOR NAND-OR NAND  

 
The degenerate forms use 2-input gates to implement the functionality of 4-input gates.

3.26
g = (a + b +c' + d')(b' + c' + d)(a'+ c + d')
f = abc' + c'd + a'cd'+ b'cd' g' = a'b'cd + bcd' + ac'd
cd c cd c
ab ab
00 01 11 10 00 01 11 10
m0 m1 m3 m2 m0 m1 m3 m2
00 1 1 00 1 1 0 1
m4 m5 m7 m6 m4 m5 m7 m6
01 1 1 01 1 1 1 0
m12 m13 m15 m14 b m12 m13 m15 m14 b
11 1 1 11 1 0 1 0
a m8 m9 m11 m10 a m8 m9 m11 m10
10 1 1 10 1 0 1 1

d d  
fg = ac'd + abc'd + b'cd'

3.27 x⊕ y = x'y + xy'; Dual = (x' + y)(x + y') = (x⊕ y)'

3.28
x
y
x
y P C
z
z
P
(a) 3-bit odd parity generator (b) 4-bit odd parity generator  

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  50  

3.29 D=A⊕ B⊕C

E = A'BC + AB'C = (A ⊕ B)C
F = ABC' + (A' + B')C = ABC' + (AB)'C = (AB) ⊕ C
G = ABC  
 
 
A B
A S S D=A B C
Half-Adder C Half-Adder
B C C E = (A B)C

S F = (AB) C
Half-Adder
C G = ABC
AB  

3.30 F = AB'CD' + A'BCD' + AB'C'D + A'BC'D

F = (A ⊕ B)CD' + (A ⊕ B) C'D = (A ⊕ B)(C ⊕ D)

A
B
F
C
D

3.31 Note: It is assumed that a complemented input is generated by another circuit that
is not part of the circuit that is to be described.
 
(a) module Fig_3_20a_gates (F, A, B, C, C_bar, D);
output F;
input A, B, C, C_bar, D;
wire w1, w2, w3, w4;
and (w1, C, D);
or (w2, w1, B);
and (w3, w2, A);
and (w4, B, C_bar);
or (F, w3, w4);
endmodule

(b) module Fig_3_20b_gates (F, A, B, B_Bar, C, C_bar, D);

output F;
input A, B, B_bar, C, C_bar, D;
wire w1, w2, w3, w4;
not (w1_bar, w1);
not (w3_bar, w3);
not (w4_bar, w4);
nand (w1, C, D);
or (w2, w1_bar, B);
nand (w3, w2, A);
nand (w4, B, C_bar);
or (F, w3_bar, w4_bar);
endmodule

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  51  

(c) module Fig_3_21a_gates (F, A, A_bar, B, B_bar, C, D_bar);

output F;
input A, A_bar, B, B_bar, C, D_bar;
wire w1, w2, w3, w4;
and (w1, A, B_bar);
and (w2, A_bar, B);
or (w3, w1, w2);
or (w4, C, D_bar);
and (F, w3, w4);
endmodule

(d) module Fig_3_21b_gates (F, A, A_bar, B, B_bar, C_bar, D);

output F;
input A, A_bar, B, B_bar, C_bar, D;
wire w1, w2, w3, w4, F_bar;
nand (w1, A, B_bar);
nand (w2, A_bar, B);
not (w1_bar, w1);
not (w2_bar, w2);
or (w3, w1_bar, w2_bar);
or (w4, w5, w6);
not (w5, C_bar);
not (w6, D);
nand (F_bar, w3, w4);
not (F, F_bar);
endmodule

(e) module Fig_3_24_gates (F, A, A_bar, B, B_bar, C, D_bar);

output F;
input A, A_bar, B, B_bar, C, D_bar
wire w1, w2, w3, w4, w5, w6, w7, w8, w7_bar, w8_bar;
not (w1_bar, w1);
not (w2_bar, w2);
not (w3, E_bar);
nor (w1, A, B);
nor (W2, C, D);
and (F, w1_bar, w2_bar, w3);
endmodule

(f) module Fig_3_25_gates (F, A, A_bar, B, B_bar, C, D_bar);

output F;
input A, A_bar, B, B_bar, C, D_bar;
wire w1, w1_bar, w2, w2_bar;
wire w3, w4, w5, w6, w7, w8;
not (w1, A_bar);
not (w2, B);
not (w3, A);
not (w4, B_bar);
and (w5, w1_bar, w2_bar));
and (w6, w3, w4);
nor (w7, w5, w6);
nor (w8, c, d_bar);
and (F, w7, w8);
endmodule

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  52  

3.32 Note: It is assumed that a complemented input is generated by another circuit that
is not part of the circuit that is to be described.
 
Note:  Because  the  signals  here  are  all  scalar–valued,  the  logical  operators  (!,  &&,  and  ||)  are  
equivalent  to  the  bitwise  operators  (~,  &,  |).    If  the  operands  are  vectors  the  bitwise  operators  
produce  a  vector  result;  the  logical  operators  would  produce  a  sclara  result  (true  or  false).  
 
(a) module Fig_3_20a_CA (F, A, B, C, C_bar, D);
output F;
input A, B, C, C_bar, D;
wire w1, w2, w3, w4;
assign w1 = C && D;
assign w2 = w1 || B;
assign w3 = !(w2 && A);
assign w4 = !w3;
assign w5 = !(B && C_bar);
assign w5_bar = !w5;
assign F = w4 || w5_bar);
endmodule

(b) module Fig_3_20b_CA (F, A, B, C, C_bar, D);

output F;
input A, B, B_bar, C, C_bar, D;
wire w2 = !w1;
wire w3 = !B_bar;
wire w4, w5, w5_bar, w6, w6_bar;
assign w1 = !(C && D);
assign w4 = w2 || w3;
assign w5 = !(w4 && A);
assign w5_bar = !w5;
assign w6 = !(B && C_bar);
assign w6_bar = !w6;
assign F = w5_bar || w6_bar;
endmodule
(c) module Fig_3_21a_CA (F, A, A_bar, B, B_bar, C, D_bar);
output F;
input A, A_bar, B, B_bar, C, D_bar;
wire w1, w2, w3, w4;
assign w1 = A && B_bar;
assign w2 = A_bar && B;
assign w3 = w1 || w2);
assign w4 = C || D_bar;
assign F = w3 || w4;
endmodule

(d) module Fig_3_21b_CA (F, A, A_bar, B, B_bar, C_bar, D);

output F;
input A, A_bar, B, B_bar, C_bar, D;
wire w1, w2, w1_bar, w2_bar, w3, w4, w5, w6, F_bar;
assign w1 = !(A && B_bar);
assign w2 = !(A_bar && B);
assign w1_bar = !w1;
assign w2_bar = !w2;
assign w3 = w1_bar || w2_bar;
assign w4 = !C_bar;
assign w5 = !D;
assign w6 = w4 || w5;
assign F_bar = !(w3 && w6);
assign F = !F_bar;
endmodule

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  53  

(e) module Fig_3_24_CA (F, A, B, C, D, E_bar);

output F;
input A, B, C, D, E_bar;
wire w1, w2, w1_bar, w2_bar, w3_bar;
assign w1 = !(A || B);
assign w1_bar = !w1;
assign w2 = !(C || D);
assign w2_bar = !w2;
assign w3 = !E_bar;
assign F = w1_bar && w2_bar && w3;
endmodule

(f) module Fig_3_25_CA (F, A, A_bar, B, B_bar, C, D_bar);

output F;
input A, A_bar, B, B_bar, C, D_bar
wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
assign w1 = !A _bar;
assign w2 = !B;
assign w3 = w1 && w2;
assign w4 = !A;
assign w5 = !B_bar;
assign w6 = w4 && w5;
assign w7 = !(C || D_bar);
assign w8 = !(w3 || w6);
assign w9 = !w8;
assign w10 = !w7;
assign F = w9 && w10;
endmodule

3.33 (a)
Initially, with xy = 00, w1 = w2 = 1, w3 = w4 = 0 and F = 0. w1 should change to 0 3ns after xy
changes to 01. w4 should change to 1 6ns after xy changes to 01. F should change from 0 to 1 8ns
after w4 changes from 0 to 1, i.e., 14 ns after xy changes from 00 to 01.

x w3

w1 6
F=x y
3
8
3 w2
y w4
6

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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  54  

(b)
`timescale 1ns/1ps

module Prob_3_33 (F, x, y);

wire w1, w2, w3, w4;

and #6 (w3, x, w1);

not #3 (w1, x);
and #6 (w4, y, w1);
not #3 (w2, y);
or #8 (F, w3, w4);

endmodule

module t_Prob_3_33 ();

reg x, y;
wire F;

Prob_3_33 M0 (F, x, y);

initial #200 $finish;

initial fork
x = 0;
y = 0;
#20 y = 1;
join
endmodule
 
(c) To simulate the circuit, it is assumed that the inputs xy = 00 have been applied sufficiently long for
the circuit to be stable before xy = 01 is applied. The testbench sets xy = 00 at t = 0 ns, and xy = 1 at t =
10 ns. The simulator assumes that xy = 00 has been applied long enough for the circuit to be in a stable
state at t = 0 ns, and shows F = 0 as the value of the output at t = 0. For illustration, the waveforms show
the response to xy = 01 applied at t = 10 ns.
 
 
Name

x
w1
y
w2
w3
w4  
F

t = 10 ns
t = 24 ns
Note: input change occurs at t = 10 ns.

t = 16 ns

Δ = 14 ns  
 
     

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  55  

3.34 module Prob_3_34 (Out_1, Out_2, Out_3, A, B, C, D);

output Out_1, Out_2, Out_3;
input A, B, C, D;
wire A_bar, B_bar, C_bar, D_bar;
assign A_bar = !A;
assign B_Bar = !B;
assign C_bar = !C;
assign D_bar = !D;
assign Out_1 = (A + B_bar) && C_bar && ( C || D);
assign Out_2 = ( (C_bar && D) || (B && C && D) || (C && D_bar) ) && (A_bar || B);
assign Out_3 = (((A && B) || C) && D) || (B_bar && C);
endmodule
3.35

module Exmpl-3(A, B, C, D, F) // Line 1

inputs A, B, C, Output D, F, // Line 2
output B // Line 3  
and g1(A, B, B); // Line 4
not (D, B, A), // Line 5
OR (F, B; C); // Line 6
endofmodule; // Line 7

Line 1: Dash not allowed character in identifier; use underscore: Exmpl_3. Terminate line with semicolon

(;).

Line 2: inputs should be input (no s at the end). Change last comma (,) to semicolon (;). Output is

declared but does not appear in the port list, and should be followed by a comma if it is intended to

be in the list of inputs. If Output is a mispelling of output and is to declare output ports, C should

be followed by a semicolon (;) and F should be followed by a semicolon (;).

Line 3: B cannot be declared both as an input (Line 2) and output (Line 3). Terminate the line with a

semicolon (;).

Line 4: A cannot be an output of the primitive if it is an input to the module

Line 5: Too many entries for the not gate (may have only a single input, and a single output). Termiante

the line with a semicolon, not a comma.

Line 6: OR must be in lowercase: change to “or”. Replace semicolon by a comma (B,) in the list of ports.

Line 7: Remove semicolon (no semicolon after endmodule).

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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3.36 (a)
B
C x
D d
z F
w
a
A y

(b)
A1 A0 B1 B0
w1
w6

F1
w2

w7 w3 F2

w4
F3

w5

(c)

a b

y1

y2

y3

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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3.37
UDP_Majority_4 (y, a, b, c, d);
output y;
input a, b, c, d;
table
// a b c d : y
0 0 0 0 : 0;
0 0 0 1 : 0;
0 0 1 0 : 0;
0 0 1 1 : 0;
0 1 0 0 : 0;
0 1 0 1 : 0;
0 1 1 0 : 0;
0 1 1 1 : 1;

1 0 0 0 : 0;
1 0 0 1 : 0;
1 0 1 0 : 0;
1 0 1 1 : 0;
1 1 0 0 : 0;
1 1 0 1 : 0;
1 1 1 0 : 1;
1 1 1 1 : 1;
endtable
endprimitive

3.38
module t_Circuit_with_UDP_02467;
wire E, F;
reg A, B, C, D;
Circuit_with_UDP_02467 m0 (E, F, A, B, C, D);

initial #100 $finish;

initial fork
A = 0; B = 0; C = 0; D = 0;
#40 A = 1;
#20 B = 1;
#40 B = 0;
#60 B = 1;
#10 C = 1; #20 C = 0; #30 C = 1; #40 C = 0; #50 C = 1; #60 C = 0; #70 C = 1;
#20 D = 1;
join
endmodule

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  58  

// Verilog model: User-defined Primitive

primitive UDP_02467 (D, A, B, C);
output D;
input A, B, C;
// Truth table for D = f (A, B, C) = S (0, 2, 4, 6, 7);
table
// A B C : D // Column header comment
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive
// Verilog model: Circuit instantiation of Circuit_UDP_02467
module Circuit_with_UDP_02467 (e, f, a, b, c, d);
output e, f;
input a, b, c, d;

UDP_02467 M0 (e, a, b, c);

and (f, e, d); //Option gate instance name omitted
endmodule

t, ns
10 20 30 40 50 60 70 80
B
t, ns
10 20 30 40 50 60 70 80
C
t, ns
10 20 30 40 50 60 70 80
D

t, ns
10 20 30 40 50 60 70 80
E
t, ns
10 20 30 40 50 60 70 80
F

t, ns
10 20 30 40 50 60 70 80

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  59  

3.39

a b s c
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

s = a'b + ab' = a ^ b
c = ab = a && b

module Prob_3_39 (s, c, a, b);

input a, b;
output s, c;

xor (s, a, b);

and (c, a, b);
endmodule
 

Digital  Design  With  An  Introduction  to  the  Verilog  HDL  –  Solution  Manual.  M.  Mano.  M.D.  Ciletti,  Copyright  2012,    
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