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DSD Lab Manual Verilog

Electronics and Communication Engineering (Manipal Academy of Higher Education)

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Expt. No. 7
Verilog Dataflow Modeling
Objective:
To understand the concepts related to dataflow modeling style and write Verilog
Programs using the same.
Theory: Modules, ports and dataflow modeling
Modules are the basic building blocks for modeling. A module is the principal design
entity in Verilog.
Module Declaration: The first line of a module declaration specifies the module
nameand port list (arguments). The next few lines specify the i/o type (input, output or
inout) and width of each port.

Syntax
module module_name (port_list);
input [msb:lsb] input_port_list;
output [msb:lsb] output_port_list;
inout [msb:lsb] inout_port_list;
... statements...
endmodule
Dataflow modeling: The data-flow model uses signal assignment statements that are
concurrent (The order of assign statements does not matter). Dataflow modeling uses
continuous assignment statements with keyword assign.
assign Y = Boolean Expression using variables and operators.
A dataflow description is based on function rather than structure and hence uses a
number of bit-wise operators.
Bitwise Verilog Operator Symbol
NOT ~
AND &
OR |
XOR ^
XNOR ^~ or ~^

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Example-7.1: Write a dataflow Verilog code to realize the given logic function in SOP
form y(a, b, c) = (1, 4, 7) and verify the design by simulation.
Solution: y(a, b, c) = a. b. c + a. b. c + a.b.c
Verilog Code:
module SOP(a,b,c,y );
input a,b,c;
output y;
assign y = a & b & c | ~a & ~b & c | a & ~b & ~c;
endmodule

Simulation Results:
Input: a = 1, b = 1, c=1
Output: y = 1

Fig. 7.1: Simulation results of example-2.1

Example- 7.2: Write a dataflow Verilog code for 2-to-4 decoder with active low enable
input and active low outputsand verify the design by simulation.
Solution:
Truth Table of 2-to-4 decoder with active low enable input and active low outputs.
Input Output
E B(MSB) A D3(MSB) D2 D1 D0
1 x x 1 1 1 1
0 0 0 1 1 1 0
0 1 0 1 1 0 1
0 0 1 1 0 1 1
0 1 1 0 1 1 1

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Verilog Code:
module decoder(
input A,B,E,
output D0,D1,D2,D3
);
assign D0= A|B|E;
assign D1= A|~B|E;
assign D2= ~A|B|E;
assign D3= ~A|~B|E;
endmodule
Simulation Results:
Input: E = 0, B (MSB) = 1, A (LSB) = 0
Output: D [3:0] = 1011

Fig. 7.2: Simulation results of example-7.2

Example-7.3: Write a dataflow Verilog code for 8- to-1 multiplexer with active low
select inputand verify the design by simulation.
Solution:
Verilog Code
module mux1( select, d, q );
input [2:0] select;
input [7:0] d;
output q;
assign q = d [~select];
endmodule

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Simulation Results:
Input: select[2:0]=101
D[7:0]=10101010
Output: q = 0

Fig. 7.3: Simulation results of example-7.3

Example-7.4: Write a dataflow Verilog code for 4 bit binary-to-gray code converter
and verify the design by simulation.

Solution:

Verilog Code:
module binarytogray(
input [0:3] b,
output [0:3] g
);
assign g[3]=b[3];
assign g[2]=b[3]^b[2];
assign g[1]=b[2]^b[1];
assign g[0]=b[0]^b[1];
endmodule
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Simulation Results:
Input: b [3:0] = 01012
Output: g [3:0] = 01112

Fig. 7.4: Simulation results of example-7.4

Exercise Problems
1. Write a dataflow Verilog code to realize the given logic function in POS form
andverify the design by simulation.
F = (A + B + C).(A + B + C).(A + B + C).(A + B + C)
2. Write a dataflow Verilog code for following digital building blocks and verify the
design by simulation: [i] full adder [ii] full subtractor [iii] three variable majority
function [iv] three input exnor function [v] two bit equality detector.
3. Write a dataflow Verilog code for 8- to-3 encoder with enable input and verify the
design by simulation.
4. Write a dataflow Verilog code for 8-to-3 priority encoder and verify the design by
simulation.
5. Write a dataflow Verilog code for 4 bit gray- to-binary code converter and verify the
design by simulation.
6. Write a dataflow Verilog code for 8421 to 2421 code converter and verify the design
by simulation.
7. Write a dataflow Verilog code for 1 bit magnitude comparator and verify the design
by simulation.
8. Write a dataflow Verilog code for 4 bit adder and verify the design by simulation.

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Expt. No. 8
Verilog Sequential Modeling
Objective:
To understand the concepts related to sequential modeling style and write Verilog
programs using the same.
Theory: To model the behavior of a digital description using sequential modeling the
following two statements are primarily used:
i) Initial statement
ii) Always statement

Initial statement: An initial statement executes only once. It begins its execution at the
start of simulation which is at time t = 0.
Syntax:
initial

[timing_control] procedural_statement
Always statement: An always statement executes repeatedly. Just like the initial
statement, an always statement also begins execution at time t = 0.
Syntax:
always
[timing_control] procedural_statement

Only a register data type can be assigned a value in either of these statements. Such a
data type retains its value until a new value is assigned. All initial and always
statements begin execution at time t = 0 concurrently. If no delays are specified in a
procedural assignment, zero delay is the default, that is, assignment occurs
instantaneously.
Example-8.1: Write a sequential Verilog code for 8-to-3 priority encoder with active
high enable input and verify the design by simulation.

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Solution:

8-to-3 priority encoder block with active high enable input

Truth Table of 8-to-3 priority encoder with active high enable input
Input Output
E D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 X X X X X X X X X X X
1 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1 X 0 0 1
1 0 0 0 0 0 1 X X 0 1 0
1 0 0 0 0 1 X X X 0 1 1
1 0 0 0 1 X X X X 1 0 0
1 0 0 1 X X X X X 1 0 1
1 0 1 X X X X X X 1 1 0
1 1 X X X X X X X 1 1 1

`timescale 1ns / 1ps

// 8-to-3 priority encoder with active high enable input
module encoder(D,Q,E);
input [7:0] D;
input E;
output [2:0] Q;
reg [2:0] Q;
always @(D or E)
begin
if (E= = 1)
casez (D)
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8'b00000001: Q=3'b000;
8'b0000001?: Q=3'b001;
8'b000001??: Q=3'b010;
8'b00001???: Q=3'b011;
8'b0001????: Q=3'b100;
8'b001?????: Q=3'b101;
8'b01??????: Q=3'b110;
8'b1???????: Q=3'b111;
endcase
else
Q=3'bX;
end
endmodule

Simulation Results:
Input: D [7:0] = 00100 010, E = 1
Output: Q [2:0] = 101

Fig. 8.1: Simulation results of example-8.1

Example-8.2: Write a sequential Verilog code for 3-bit binary ripple up counter and
verify the design by simulation.

Solution:
Verilog Code:
`timescale 1ns / 1ps
module counter( clk, count );
input clk;
output [2:0] count;
reg [2:0] count;
wire clk;
initial

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count = 3'b0;
always @( negedge clk )
count[0] <= ~count[0];
always @( negedge count[0] )
count[1] <= ~count[1];
always @( negedge count[1] )
count[2] <= ~count[2];
endmodule
Simulation Results:
Output: 000 - - 001 - - 010 - - 011 - - 100 - - 101 - - 110 - - 111

Fig. 8.2: Simulation results of example-8.2

Example-8.3: Write a sequential Verilog code for 4 bit ring counter and verify the
design by simulation and verify the design by simulation.

Solution:
Table showing output sequence of 4 bit ring counter
Count Order Sequence
0 1000
1 0100
2 0010
3 0001
Verilog Code:
module Ringcounter(q,clk,clr);
input clk,clr;
output [3:0] q;
reg [3:0] q;
always @(posedge clk)
if(clr= =1)
q<=4'b1000;

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else
begin
q[3]<=q[0];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule

Simulation Results:
Output: 1000 --- 0100 --- 0010 --- 0001--- 1000 ----

Fig. 8.3: Simulation results of example-8.3

Exercise Problems
1. Write the sequential Verilog code for synchronous mod 5 counter and verify the
design by simulation.
2. Write a sequential Verilog code for 4 bit priority encoder and verify the design by
simulation.
3. Write the sequential Verilog code for Master-Slave JK flip-flop and verify the design
by simulation.
4. Write sequential Verilog code for 4 bit universal shift register and verify the design
by simulation.

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Expt. No. 9
Verilog Structural Modeling
Objective:
To understand the concepts related to structural modeling style and write Verilog
programs using the same.
Theory:
Structures can be described in Verilog HDL using
i) Built in gate primitives (at the gate level)
ii) Switch level primitives (at the transistor level)
iii) User defined primitives (at the gate level)
iv) Module primitives (to create hierarchy)

A module can be instantiated in another module, thus creating hierarchy. A module

instantiation statement is of the form:
Module_name instance_name( port_association);
Port association can be by position or by name, however associations cannot be mixed.
A port association is of the form.
port_expr
.portname(port_expr)
In positional association, the port expressions connect to the ports of the module in the
specified order. In association by name, the connection between the module port and the
port expression is explicitly specified and thus the order of port associations is not
important.
Example-9.1: Write structural Verilog code for 8:1 multiplexer using 2:1 multiplexers
and verify the design by simulation.

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Solution:

Structure of 8:1 multiplexer using 2:1 multiplexers

Verilog Code:
module mux_2to1(
input A,B,S,
output Y
);
wire Sbar;
assign S bar=~S;
assign Y=((Sbar& A)|(S & B));
endmodule
module mux8to1(D,sel,F);
input [7:0] D;
input [2:0] sel;
output F;
wire W [6:1];
mux_2to1 M1(D[0],D[1],sel[0],W[1]);
mux_2to1 M2(D[2],D[3],sel[0],W[2]);
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mux_2to1 M3(D[4],D[5],sel[0],W[3]);
mux_2to1 M4(D[6],D[7],sel[0],W[4]);
mux_2to1 M5(W[1],W[2],sel[1],W[5]);
mux_2to1 M6(W[3],W[4],sel[1],W[6]);
mux_2to1 M7(W[5],W[6],sel[2],F);

endmodule
Simulation Results:
Input: D[7:0] = 0001 00002 ; sel[2:0] = 1002 ;
Output: F = 1

Fig. 9.1: Simulation results of example-9.1

Example-9.2: Write hierarchical structural Verilog code for 4 bit ripple carry adder
using full-adder component and verify the design by simulation.
Solution:

4 bit ripple carry adder using full-adder blocks

Verilog Code:
module adder(input a,input b,input cin,output s,output cout);
assign s=a^b^cin;
assign cout=(a&b)|(b&cin)|(cin&a);
endmodule
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module rippleadd(input [3:0] a, input [3:0] b,input cin,output [3:0] s,output cout);
wire [3:0] sumout;
wire [3:0] carryout;
adder fa1(a[0],b[0],cin, sumout[0],carryout[0]);
adder fa2(a[1],b[1], carryout [0], sumout [1], carryout [1]);
adder fa3(a[2],b[2], carryout [1], sumout [2], carryout [2]);
adder fa4(a[3],b[3], carryout [2], sumout [3], carryout [3]);
assign s= sumout;
assign cout = carryout[3];
endmodule
Simulation Results:
Input: a[3:0] = 01102 , b[3:0] = 01002, cin = 02
Output: s[3:0] = 10102, cout = 02

Fig. 9.2: Simulation results of example-9.2

Example-9.3: Write structural Verilog code for 3-bit ripple up/down counter and verify
the design by simulation.
Solution:

3-bit ripple up/down counter realization using JK flip-flops

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Verilog Code:
`timescale 1ns / 1ps
module Jk_FF(j,k,clock,q,qb);
input j,k,clock;
output reg q,qb;
initial
begin
q=1;
qb=0;
end
always@(posedge clock)
begin
case({j,k})
2'b00 :q=q;
2'b01 :q=0;
2'b10 :q=1;
2'b11 :q=~q;
default :q=0;
endcase
qb<=~q;
end
endmodule
module jk_up_down_counter(input clk,input M,output [2:0]Q);
wire S1,S2,S3,S4,S5,S6,S7,S8,S9;
Jk_FF JK1(1'b1,1'b1,clk,Q[0],S1),
JK2(1'b1,1'b1,S4,Q[1],S5),
JK3(1'b1,1'b1,S8,Q[2],);
and A1(S2,S9,Q[0]),
A2(S3,S1,M),
A3(S7,Q[1],S9),
A4(S6,S5,M);
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or or1 (S4,S2,S3),
or2 (S8,S7,S6);
not not1(S9,M);
endmodule
Simulation Results:
Input: M = 1 (UP mode)
Output: 000 - - 001 - - 010 - - 011 - - 100 - - 101 - -

Figure 9.3: Simulation results of example-9.3

Example-9.4: Write structural Verilog code for 4:1 multiplexer using 2:1 multiplexer
and verify the design by simulation.

Solution:

4:1 multiplexer using 2:1 multiplexers

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Verilog Code:
Module mux4to1(a,sel,out);
Input [3:0] a;
Input [1:0] sel;
Output out;
Wire mux[2:0];
Mux2to1 m1(a[0], a[1], sel[0], mux_1);
Mux2to1 m2(a[2], a[3], sel[0], mux_2);
Mux2to1 m3(mux_1,mux_2,sel[1],out);
Endmodule
Simulation Results:
Input: sel[1:0] = 102 , a[3] = 0, a[2] = 1, a[1] = 0, a[0] = 1
Output: out = 1

Figure 9.4: Simulation results of example-9.4

Exercise Problems
1. Write structural Verilog code for mod-10 ripple counter and verify the design by
simulation.
2. Write structural Verilog code for 4-bit SIPO shift and verify the design by
simulation.
3. Write structural Verilog code for 4-bit PISO shift register and verify the design by
simulation.
4. Write structural Verilog code for 4- bit binary-to-gray code converter and verify the
design by simulation.

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Expt. No. 10
Verilog examples using task and functions, user defined
primitive
Objective:
To study switch level and mixed mode style of Verilog with examples
Theory:
Task: A task provides the ability to execute common pieces of code from several
different places. This common piece of code is written as task so it can be called from
different places in the design discerption.
A task is delimited by the keywords task and endtask. The syntax for a task declaration
is as follows:
task task_name
input arguments
output arguments
inout arguments
task declarations
local variable declarations
begin
statements
end
endtask
Function: Functions are behavioral statements. Functions must be called within always
or initial. Functions take one or more inputs, and, in contrast to task, they return only a
single output value. Functions are delimited by the keywords function and endfunction
and are used to implement combinational logic; therefore, functions cannot contain
event controls or timing controls.
function [range or type] function name
input declaration
other declarations
begin
statement
end
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endfunction

User defined primitive

The syntax for a UDP is similar to that for declaring a module. The definition begins
with the keyword primitive and ends with the keyword endprimitive. The UDP
contains a name and a list of ports, which are declared as input or output. For a
sequential UDP, the output port is declared as reg. UDPs can have one or more scalar
inputs, but only one scalar output. UDPs do not support inout ports
primitive udp_name (output, input_1, input_2, . . . , input_n);
output output;
input input_1, input_2, . . . , input_n;
regs equential_output; //for sequential UDPs
initial //for sequential UDPs
table
state table entries
endtable
endprimitive
Solved Problems
Example 10.1: Write a Verilog code using task to perform logical operations on two 8-
bit vectors a[7:0] and b[7:0]. The logical operations are: AND, NAND, OR, NOR,
exclusive-OR, and exclusive-NOR.
Solution:

Block performing logical operations on two 8-bit data

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Verilog code
//module to illustrate a task for logical operations
module task_logical;
reg[7:0] a, b;
reg[7:0] a_and_b, a_nand_b, a_or_b, a_nor_b, a_xor_b, a_xnor_b;
initial
begin
a=8'b1010_1010; b=8'b1100_1100;
logical (a, b, a_and_b, a_nand_b, a_or_b, a_nor_b, a_xor_b, a_xnor_b);
//invoke the task
a=8'b1110_0111; b=8'b1110_0111;
logical (a, b, a_and_b, a_nand_b, a_or_b, a_nor_b,a_xor_b, a_xnor_b);
//invoke the task
a=8'b0000_0111; b=8'b0000_0111;
logical (a, b, a_and_b, a_nand_b, a_or_b, a_nor_b,a_xor_b, a_xnor_b);
//invoke the task
a=8'b0101_0101; b=8'b1010_1010;
logical (a, b, a_and_b, a_nand_b, a_or_b, a_nor_b,a_xor_b, a_xnor_b);
//invoke the task
end
task logical;
input [7:0] a, b;
output [7:0] a_and_b, a_nand_b, a_or_b, a_nor_b,a_xor_b, a_xnor_b;
begin
a_and_b = a & b;
a_nand_b = ~(a & b);
a_or_b = a | b;
a_nor_b = ~(a | b);
a_xor_b = a ^ b;
a_xnor_b = ~(a ^ b);

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$display ("a=%b, b=%b, a_and_b=%b, a_nand_b=%b, a_or_b=%b, a_nor_b=%b,

a_xor_b=%b, a_xnor_b=%b", a, b, a_and_b, a_nand_b, a_or_b, a_nor_b, a_xor_b,
a_xnor_b);
end
endtask
endmodule
Simulation Results

Input: a[7:0] = 0101 01012, b[7:0] = 1010 10102

Output: a_and_b[7:0] = 0000 00002; a_nand_b[7:0] = 111111112
a_or_b[7:0] = 111111112; a_nor_b[7:0] = 000000002
a_xor_b[7:0] = 111111112; a_xnor_b[7:0] = 000000002

Fig. 6.1: Simulation results of example-6.1

Example 6.2: Write a Verilog code for the expression z1 = x1 x2 + x3 x4 + x2' x3' using
AND gate and OR gate user defined primitive (UDP).
Solution:

SOP expression using AND gate and OR gate as UDP

Verilog code:
//UDP for a 2-input AND gate
primitive udp_and2 (z1, x1, x2); //output is listed first

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input x1, x2;

output z1;
//define state table
table
//inputs are the same order as the input list
// x1 x2 : z1; comment is for readability
0 0 : 0;
0 1 : 0;
1 0 : 0;
1 1 : 1;
endtable
endprimitive

//UDP for a 3-input OR gate

primitive udp_or3 (z1, x1, x2, x3); //output is listed first
input x1, x2, x3;
output z1;
//define state table
table
//inputs are the same order as the input list
// x1 x2 x3 : z1; comment is for readability
0 0 0 : 0;
0 0 1 : 1;
0 1 0 : 1;
0 1 1 : 1;
1 0 0 : 1;
1 0 1 : 1;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive
//sum of products using UDPs for the AND gate and OR gate
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module udp_sop (x1, x2, x3, x4, z1);

input x1, x2, x3, x4;
output z1;
//define internal nets
wire net1, net2, net3;
//instantiate the udps
udp_and2 (net1, x1, x2);
udp_and2 (net2, x3, x4);
udp_and2 (net3, ~x2, ~x3);
udp_or3 (z1, net1, net2, net3);
endmodule

Simulation Results
Input: x1 = 12 ; x2 = 12 ; x3 = 02 ; x4 = 12
Output: z1=1

Fig. 10.2: Simulation results of example-10.2

Example 10.3: Write a Verilog code for full adder using 3 input XOR gate as UDP and
AND gate and OR gate as built in primitive.

Solution:

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Verilog code:
//UDP for a 3-input exclusive-OR
primitive udp_xor2 (z1, x1, x2,x3);
input x1, x2, x3;
output z1;
//define state table
table
//inputs are in the same order as the input list
// x1 x2 x3 : z1; comment is for readability
0 0 0 : 0;
0 0 1 : 1;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 0;
1 1 1 : 1;
endtable
endprimitive

//full adder using a UDP and built-in primitives

module full_adder_udp (a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
//define internal nets
wire net1, net2, net3;
//instantiate the udps and built-in primitive
udp_xor2 (sum, a, b, cin);
and inst1 (net1, a, b);
and inst2 (net2, b, cin);
and inst3 (net3, a, cin);
or inst3 (cout, net3, net2, net1);
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endmodule

Simulation Results
Input: a = 12 ;b = 12 ; cin = 12
Output: sum =12 ;cout=12

Fig. 10.3: Simulation results of example-10.3

Example 10.4: Write a sequential Verilog code for 3-bit binary-to-gray code converter
using function that evaluates the two-input EX-OR expression and verify the code by
simulation.
Solution:

Verilog code:
module Func_exm (b0, b1,b2,g0,g1,g2);
input b0, b1,b2;
output g0,g1,g2;
reg g0,g1,g2;
always @ (b0,b1,b2)
begin
g0= exp (b0, b1);
g1= exp (b1, b2);
g2= exp (0, b2);
end

function exp ;
input a, b;
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begin
exp = a ^ b;
end
endfunction
endmodule

Simulation Results
Input: b[3:0] = 1012
Output: g[3:0] =1112

Fig. 10.4: Simulation results of example-10.4

Exercise Problems
1. Write a Verilog code of 4-to-1 multiplexer as UDP and verify the design description
by simulation.
2. Write a Verilog code for 4-bit binary-to-gray code converter using two-input xor gate
UDP and verify the design by simulation.
3. Write a Verilog code for half-adder using task and then describe the behaviour of
full-adder from two half-adders and verify the design by simulation.
4. Write a Verilog code for the positive-edge-triggered D flip-flop as UDP and verify
the design by simulation.

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REFERENCES
1. Charles Roth, Lizy Kurian John, ByeongKil Lee, Digital System Design Using
Verilog, 1st Edition, 2016.
2. Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall
Publishing, 2nd edition, 2010.
3. Stephen. Brown and ZvonkoVranesic, Fundamentals of Digital Logic with Verilog
Design, TMH, 2013.
4. Digital Lab Manual, Revision 2.0, University Support Team, Cadence, Bangalore.

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