BECE 102L

DIGITAL SYSTEM DESIGN

Module-II
Digital Logic
Part-II
Module-II (Verilog HDL)

Lexical Conventions, Ports and Modules, Operators, Dataflow Modelling, Gate

Level Modelling, Behavioural Modeling, Test Bench

(5 hours)

2
Content
• Abstraction Levels.
• Gate Level Modelling,
• Data Flow Modelling,
• Behavioural level Modelling
• Test Bench.

3
Abstraction levels
The Verilog HDL supports four types of modelling a Hardware circuit.
1. Behavioural or Algorithmic Model
2. Dataflow Model
3. Structural or Gate level Model
4. Switch level Model

4
Abstraction levels // Test bench for AND gate Gate level Modelling
// AND gate Gate level Modelling module and_g_tb;
module and_g(a,b,y); // AND gate behavioral Modelling reg a;
input a; module and_b(a,b,y); reg b;
input b; input a; wire y;
output y; input b; and_g uut (a,b,y);
and(y,a,b); output y; initial
endmodule reg y; begin
always @ (a or b) a = 0; b = 0;
begin #10 a = 0; b = 1;
// AND gate dataflow Modelling if (a == 1'b1 & b == 1'b1) #10 a = 1; b = 0;
module and_d(a,b,y); y = 1'b1; #10 a = 1; b = 1;
input a; else #10 $stop;
input b; y = 1'b0; $monitor($time, "a=%b, b=%b, y=%b", a,b,y);
output y; end $dumpfile("dump.vcd");
assign y = a & b; endmodule $dumpvars();
endmodule end
endmodule

5
Abstraction levels
1. Behavioural or algorithmic level:
• This is the highest level of abstraction provided by Verilog HDL.
• A module can be implemented in terms of the desired design algorithm
without concern for the hardware implementation details.
• Designing at this level is very similar to C programming.

2. Dataflow level:
• At this level the module is designed by specifying the data flow.
• The designer is aware of how data flows between hardware registers and
how the data is processed in the design.

6
Abstraction levels
3. Gate level:
• The module is implemented in terms of logic gates and interconnections
between these gates.
• Design at this level is similar to describing a design in terms of a gate-
level logic diagram.
4. Switch level:
• This is the lowest level of abstraction provided by Verilog.
• A module can be implemented in terms of switches, storage nodes, and the
interconnections between them.
• Design at this level requires knowledge of switch-level implementation
details.

7
Structural Modelling
• At gate level, the circuit is described in terms of gates. (e.g., and,
nand…)
• Hardware design at this level is intuitive for a user with a basic knowledge
of digital logic design.
• It is possible to see a one-to-one correspondence between the logic circuit
diagram and the Verilog description.
• Actually, the lowest level of abstraction is switch- (transistor-) level
modeling.
• However, with designs getting very complex, very few hardware designers
work at switch level.
• So most of the digital design is now done at gate level or higher levels of
abstraction.
8
Structural Modelling
• All logic circuits can be designed by using basic gates.
• Verilog supports basic logic gates as predefined primitives.

• There are three classes of basic gates.

1. Multiple-input gates: and, or, nand, nor, xor, xnor
2. Multiple-output gates: buffer, not
3. Tristate gates: bufif0, bufif1, notif0, notif1

• These primitives are instantiated like modules except that they are
predefined in Verilog and do not need a module definition.
• Logic gates can be used in design using gate instantiation.
9
Structural Modelling
• The Syntax is
Gate_type [instance_name] (term1, term2,……………..termn);

• Example

// Module Name: Andgate

module Andgate(a, b, c);
input a;
input b;
output c;
and (c, a, b);
endmodule

10
Structural Modelling

11
Structural Modelling

12
Structural Modelling
• Example 2to1 MUX

13
Structural Modelling
• Example 2to1 MUX
Gate Instantiation

14
Structural Modelling
• Full Adder using Half Adder (Module Instantiation)

15
Structural Modelling
• Half Adder

16
Dataflow Modelling
• Data flow level description is higher level modelling and it makes the
circuit description more compact as compared to structural modelling.
• Design implement using data flow modeling uses a continuous assignment
statement and Verilog provides different operators to perform a function.
• The assignment statement start with the keyword assign and results are
assigned to nets.
• Continuous assignment – most basic statement used to drive value onto net

17
Dataflow Modelling
• Implicit continuous assignment – it is the shortcut method of assigning the
expression on the net.

• Implicit net declaration – if a signal name of the left hand side of the
continuous assignment statement is not declared the Verilog simulator
assign an implicit net declaration for the net

18
Dataflow Modelling
• Regular assignment delay – the assignment takes effect with the time delay
of 2 time steps. If the values of „a‟ and „b‟ changes then „c‟ wait for two
time steps to compute the result.

• Implicit continuous assignment delay – it is a shortcut method of assigning

the delay and the expression on the net.

• Net declaration delay – a delay can be specified on a net when it is declared

without putting a continuous assignment on the net.

19
Dataflow Modelling
EXPRESSIONS
• An expression is formed using operands & operators.
• Expression can be used whenever a value is expected.
• Example: a & b, x1[7:0] + x2[7:0].
OPERANDS
• Operands are the data types used in the expression.
• An operands can be constant, net, parameter, register, memory, bit
select.
• Example: c = a + b // a, b, c are real operands.

20
Dataflow Modelling
OPERATORS:
• Operators act on operands to produce desired result.
• Various types: arithmetic, logical, relational, equality, bitwise, shift, etc.,
• Example:
c = a % b // % is operator to perform modules operation on a, b.

21
Dataflow Modelling-Examples

22
Dataflow Modelling-Examples

23
Dataflow Modelling-Examples
• 2X1 MUX

24
Dataflow Modelling-Examples
• D Flip-Flop

25
Behavioural Modelling
• Behavioral model enables you to describe the system at a higher level of
abstraction (i.e.) it specify the circuit in terms of behavior.
• All we need to do is to describe the behavior (Algorithm) of our design.
• Action  How the model of our circuit should behave?
• Timing control At what time do what thing & At what condition do what
thing.
• Verilog supports the following construct to model circuit behavior.
• Procedural block
• Procedural assignment
• Timing controls
• Block statement
• Conditional statement
26
Behavioural Modelling
• Procedural Block:
• In Verilog procedural block are the basic of behavior modeling.
• We can describe one logic in one procedural block.
• Procedural block types:
(i) initial
(ii) always.
• All initial & always statement execute concurrently starting at time t=0.
• A module may contain any number of initial & always statement.

27
Behavioural Modelling
• Procedural Block:
• Structure of procedural block

28
Behavioural Modelling
• Procedural Block:
• Initial statement causes procedural statement to executes only once and it begin
its execution at start of simulation time 0.
• Sequential block (begin-end) is the most commonly used procedural statement,
that is it wait for a certain time until an event occurs.

29
Behavioural Modelling
• Procedural Block-Always Statement
• For circuit synthesis we use the always block and such a block must contain all
sequential constructs.
• Note that the statements in an always block between begin/end are executed
sequentially just as they are written.
• Variables assigned a value inside an always block must be of type reg or integer.
• The if, case, for loop, and while loop must appear inside an always block.
• A module can have multiple blocks, but blocks cannot be nested.
• For modules that have multiple always blocks all of the always blocks are
executed in parallel.

30
Behavioural Modelling
• Procedural Block-Always Statement
• Always blocks are repeated executed until simulation is stopped. Similar to
initial block it begin its execution at start of simulation time 0.
• This statement is used to model a block of activity that is repeated continuously
in a digital circuit.

31
Behavioural Modelling
• Procedural Statement
• The assignment statement within an initial statement or always statement is
called procedural statement.
• It is used to assign to only a register data type.
• Procedural statement executes sequentially respect to other statements that
appear around it.
• Sequential block always start execution when an event occurs.
• Two types of procedural assignments are:
(i) blocking assignment
(ii) non-blocking assignment

32
Behavioural Modelling
• BLOCKING PROCEDURAL ASSIGNMENT
• A procedural statement in which the assignment
operator is an “=” in a blocking procedural
assignment.

• Blocking procedural assignment is executed

before any of the statement that follow it are
executed.
• The sum assignment occurs first, sum is
computed, then second statement is executes C1
is assigned and then third executed and C2 is
assigned and so on.

33
Behavioural Modelling
• NON-BLOCKING PROCEDURAL ASSIGNMENT
• The main characteristics of non-blocking assignment
statement is execution is performed concurrently.
• In non-blocking assignment the assignment symbol
“<=“ is used.
• „a‟ is assigned the stored value of „b‟ this activity is
carried out concurrently.
• At the negative edge clock „c‟ is assigned a value of
b&(~c).
• Two nanoseconds later positive edge clock assign „c‟
value to „b‟.

34
Behavioural Modelling

35
Behavioural Modelling
• BLOCKING STATEMENT - SEQUENTIAL BLOCK
• Block statements are used to group multiple statements to act together as one.
There are two types of blocks:
• Sequential blocks and
• Parallel blocks
• The keywords begin and end are used to group statements into sequential blocks.
• Sequential blocks have the following characteristics:
• The statements in a sequential block are processed in the order they are specified.
• A statement is executed only after its preceding statement completes execution.
• If delay or event control is specified, it is relative to the simulation time when the previous
statement in the block completed execution.

36
Behavioural Modelling
• BLOCKING STATEMENT - SEQUENTIAL BLOCK

37
Behavioural Modelling
• BLOCKING STATEMENT - PARALLEL BLOCK
• Parallel blocks, specified by keywords fork and join, provide interesting
simulation features
• Parallel blocks have the following characteristics:
• Statements in a parallel block are executed concurrently.
• Ordering of statements is controlled by the delay or event control assigned to
each statement.
• If delay or event control is specified, it is relative to the time the block was
entered.

38
Behavioural Modelling
• BLOCKING STATEMENT - PARALLEL BLOCK
• All statements in a parallel block start at the time when the block was entered.
• Thus, the order in which the statements are written in the block is not important.
• The result of simulation remains the same except that all statements start in
parallel at time 0.
• Hence, the block finishes at time 20 instead of time 35.

39
Behavioural Modelling
• CONDITIONAL STATEMENT – IF
• Conditional statements are used for making
decisions based upon certain conditions.
• These conditions are used to decide whether or not
a statement should execute.
• If the condition evaluates to a non zero known
value, then procedural_statement1 is executed.
• If condition_ 1 evaluates 0.x,z, then
procedural_statement2 is not executed and an else
branch, if it exist, is executed.

40
Behavioural Modelling
• CONDITIONAL STATEMENT – CASE
• The keywords case, endcase, and default are
used in the case statement.
• The expression is compared to the alternatives
in the order they are written.
• For the first alternative that matches, the
corresponding statement or block is executed.
• If none of the alternatives match, the
default_statement is executed.
• The default_statement is optional.

41
Behavioural Modelling
• CONDITIONAL STATEMENT – CASE
• Case treats each value 0, 1, x, and z literally.
• 4ʼb01xz only matches 4ʼb01xz
• Example: 4ʼb0110 does not match 4ʼb01xx in a case
• Casez treats 0, 1, and x literally.
• Casez treats z as a donʼt care.
• Example: 4ʼb0110 matches 4ʼb01zz, but not 4ʼb01xz
• Casex treats 0 and 1 literally
• Casex treats both x and z as donʼt cares
• Example: 4ʼb0110 matches 4ʼb01xx and also 4ʼb01xz

42
Behavioural Modelling
• CONDITIONAL STATEMENT – FOR Loop
• When a circuit exhibits regularity, a for loop can be used inside an always
statement to simplify the design description (for loop is a procedural statement
used only inside an always block).
• C style syntax: for (k = 0; k < 4; k = k+1)
• Loop index must be type integer (not reg!)
• Can`t use the convenience of k++
• Use begin …end for multiple statements in the loop
• Each iteration of the loop specifies a different piece of the circuit
• Has nothing to do with changes over “time”

43
Behavioural Modelling
• CONDITIONAL STATEMENT – FOREVER
Loop
• The keyword forever is used to express this loop.
A forever loop can be exited by use of the disable
statement.
• The loop does not contain any expression and
executes forever until the $finish task is
encountered.
• The loop is equivalent to a while loop with an
expression that always true, e.g., while (1).
• A forever loop is typically used in conjunction
with timing control constructs.

44
Behavioural Modelling-Examples
• Half Adder

45
Behavioural Modelling-Examples
• Full Adder

46
Behavioural Modelling-Examples
• 2 to 1 MUX

47
Behavioural Modelling-Examples
• D Flip-flop

48
Test Bench
• We need to apply appropriate stimulus to the design to test it.
• Stimulus is nothing but the application of various permutations and
combinations of inputs at various points of time and, looking for correct results
produced by the design.
• This can be done by writing another Verilog code called Test Bench.
• Test bench used to simulate your design without physical hardware.
• This is written as a separate file, different from the design file(s).
• The biggest benefit of this is that you can actually inspect every signal that is in
your design.

49
Test Bench-Structure
module test_module_name;
//declare local reg and wire identifiers.
//instantiate the design module under test
//generate stimulus (inputs to design module) using initial and always.
// display output response.(display on screen or print)
endmodule

50
Test Bench-Example

51
Test Bench-Example

52
Test Bench-Example-AND Gate

53
Test Bench-Example-Half Adder

54
Test Bench-Example-Full Adder

55
Test Bench-Example-Full Adder

56
Test Bench-Example-D FF

57
Summary
• Abstraction Levels.
• Structural Model
• Dataflow Model
• Behavioural Model
• Sample Programs
• Test Bench.

58
59