Digital Design & HDL

MCQs

1. What is the full form of VHDL?

a) Verilog Hardware Description Language
b) Very High speed Description Language
c) Variable Hardware Description Language
d) Very high speed Hardware Description Language
2. What is the basic use of EDA tools?
a) Communication of Electronic devices
b) Fabrication of Electronics hardware
c) Electronic circuits simulation and synthesis
d) Industrial automation
3. After compiling VHDL code with any EDA tool, we get __________
a) Final device
b) FPGA
c) Optimized netlist
d) Netlist
4. Which of the following is not an EDA tool?
a) Visual C++
b) Quartus II
c) Xilinx ISE
d) MaxPlus II
5. The process of transforming a design entry information of the circuit into a set of
logic equations in any EDA tool is known as _________
a) Simulation
b) Synthesis
c) Optimization
d) Verification
6. Simple Programmable Logic Devices (SPLDs) are also regarded as ________.
a) Programmable Array Logic (PAL)
b) Generic Array Logic (GAL)
c) Programmable Logic Array (PLA)
d) All of the above
7. Which among the following is/are not suitable for in-system programming?
a) EPROM
b) EEPROM
c) Flash
d) All of the above
8. The devices which are based on fusible link or anti-fuse are _________time/s
programmable.
a) one
b) two
c) four
d) infinite
9. Place and Route EDA tools are used to take the design netlist and implement the
design in the device
a) True
b) False
10. Which programming technology/ies is/are predominantly associated with SPLDs
and CPLDs?
a) EPROM
b) EEPROM
c) FLASH
d) All of the above
11. An Antifuse programming technology is predominantly associated with _____
a) SPLDs
b) FPGAs
c) CPLDs
d) All of the above
12. Which of the following is not a back end EDA tool?
a) Floor planning tools
b) Placement tools
c) Routing tools
d) Simulators
13. Difference between simulation tools and Synthesis tool is _________
a) Simulators are used to check the performance of circuit and Synthesis tools are for the
fabrication of circuits
b) Simulators and Synthesis tools works exactly same
c) Simulators are used just to check basic functionality of the circuit and Synthesis tools
includes timing constraints and other factors along with simulation
d) Simulation finds the error in the code and Synthesis tool corrects the code
14. What is the extension of the Netlist file; input to the place and route EDA tools?
a) EIDF
b) SDF
c) TXT
d) CPP
15. Which of the following is the basic building block of a design?
a) Architecture
b) Entity
c) Process
d) Package
16. What does modeling type refer to?
a) Type of ports in entity block of VHDL code
b) Type of description statements in architecture block of VHDL code
c) Type of data objects
d) Type of Signals
17. Which of the following is not a type of VHDL modeling?
a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) Component modeling
18. In behavioral modeling, what do descriptive statements describe?
a) How the system performs on given input values
b) How the design is to be implemented
c) Netlist
d) Concurrent execution
19. Which of the following statement is used in structural modeling?
a) portmap
b) process
c) if-else
d) case
20. What is the basic unit of behavioral description?
a) Structure
b) Sequence
c) Process
d) Dataflow
21. Which sequential circuits generate the feedback path due to the cross-coupled
connection from output of one gate to the input of another gate?
a) Synchronous
b) Asynchronous
c) Both
d) None of the above
22. Boundary scan method takes lesser time on test pattern generation.
a) true
b) false
23. What is/are the crucial function/s of memory elements used in the sequential
circuits?
a) Storage of binary information
b) Specify the state of sequential
c) Both a & b
d) None of the above
24. The behavior of synchronous sequential circuit can be predicted by defining the
signals at ______.
a) discrete instants of time
b) Continuous instants of time
c) Sampling instants of time
d) At any instant of time
25. Which memory elements are utilized in asynchronous & clocked sequential
circuits respectively?
a) Time- delay devices & registers
b) Time- delay devices & flip-flops
c) Time- delay devices & counters
d) Time-delay devices & latches
26. Why do the D-flipflops receives its designation or nomenclature as 'Data
Flipflops'
a) Due to its capability to receive data from fliflop
b) Due to its capability to store data in flipflop
c) Due to its capability to transfer the data into flipflop
d) All of the above
27. The characteristic equation of D-flipflop implies that _____.
a) the next state is dependent on previous state
b) the next state is dependent on present state
c) the next state is independent of previous state
d) the next state is independent of present state
28. Which circuit is generated from D-flipflop due to addition of an inverter by
causing reduction in the number of inputs?
a) Gated JK- latch
b) Gated SR- latch
c) Gated T- latch
d) Gated D- latch
29. Which type of memory elements are used in synchronous sequential circuits?
a) Clocked Flip flops
b) Unclocked Flip flops
c) Time Delay Elements
d) All of the above
30. Which is used to control the scan path movement?
a) clock signals
b) input signals
c) output signals
d) delay signals
31. Boundary scan test is used to test
a) pins
b) multipliers
c) boards
d) wires
32. The boundary scan path is provided with
a) serial input outputs pads
b) parallel input pads
c) parallel output pads
d) buffer pads
33. The disadvantage of boundary scan method is that the fault coverage is less.
a) true
b) false
34. In accordance to the scaling technology, the total delay of the logic circuit
depends on ______
a) The capacitor to be charged
b) The voltage through which capacitance must be charged
c) Available current
d) All of the above
35. ______ architecture is used to design VLSI.
a) system on a device
b) single open circuit
c) system on a chip
d) system on a circuit
36. What is the design flow of VLSI system?
i. architecture design
ii. market requirement
iii. logic design
iv. HDL coding
a) ii-i-iii-iv
b) iv-i-iii-ii
c) iii-ii-i-iv
d) i-ii-iii-iv
37. ______ is used in logic design of VLSI.
a) LIFO
b) FIFO
c) FILO
d) LILO
38. Which provides higher integration density?
a) switch transistor logic
b) transistor buffer logic
c) transistor transistor logic
d) circuit level logic
39. Physical and electrical specification is given in ____________
a) architectural design
b) logic design
c) system design
d) functional design
40. Which is the high level representation of VLSI design?
a) problem statement
b) logic design
c) HDL program
d) functional design
41. The utilization of CAD tools for drawing timing waveform diagram and
transforming it into a network of logic gates is known as ________.
a) Waveform Editor
b) Waveform Estimator
c) Waveform Simulator
d) Waveform Evaluator
42. Which among the following is a process of transforming design entry information
of the circuit into a set of logic equations?
a) Simulation
b) Optimization
c) Synthesis
d) Verification
43. _________ is the fundamental architecture block or element of a target PLD.
a) System Partitioning
b) Pre-layout Simulation
c) Logic cell
d) Post-layout Simulation
44. In VLSI design, which process deals with the determination of resistance &
capacitance of interconnections?
a) Floorplanning
b) Placement & Routing
c) Testing
d) Extraction
45. Among the VHDL features, which language statements are executed at the same
time in parallel flow?
a) Concurrent
b) Sequential
c) Net-list
d) Test-bench
46. In Net-list language, the net-list is generated _______synthesizing VHDL code.
a) Before
b) At the time of (during)
c) After
d) None of the above
47. In VHDL, which object/s is/are used to connect entities together for the model
formation?
a) Constant
b) Variable
c) Signal
d) All of the above
48. Which data type in VHDL is non synthesizable & allows the designer to model the
objects of dynamic nature?
a) Scalar
b) Access
c) Composite
d) File
49. Which type of simulation mode is used to check the timing performance of a
design?
a) Behavioural
b) Switch-level
c) Transistor-level
d) Gate-level
50. In the simulation process, which step specifies the conversion of VHDL
intermediate code so that it can be used by the simulator?
a) Compilation
b) Elaboration
c) Initialization
d) Execution
51. Which type of simulator/s neglect/s the intra-cycle state transitions by checking
the status of target signals periodically irrespective of any events?
a) Event-driven Simulator
b) Cycle-based Simulator
c) Both a and b
d) None of the above
52. Which among the following is not a characteristic of ‘Event-driven Simulator’?
a) Identification of timing violations
b) Storage of state values & time information
c) Time delay calculation
d) No event scheduling
53. Which among the following is an output generated by synthesis process?
a) Attributes & Library
b) RTL VHDL description
c) Circuit constraints
d) Gate-level net list
54. Register transfer level description specifies all of the registers in a design & ______
logic between them.
a) Sequential
b) Combinational
c) Both a and b
d) None of the above
55. In synthesis process, the load attribute specify/ies the existing amount of
_________load on a particular output signal.
a) Inductive
b) Resistive
c) Capacitive
d) All of the above
56. Which attribute in synthesis process specify/ies the resistance by controlling the
quantity of current it can source?
a) Load attribute
b) Drive attribute
c) Arrival time attribute
d) All of the above
57. Which type of digital systems exhibit the necessity for the existence of at least
one feedback path from output to input?
a) Combinational System
b) Sequential system
c) Both a and b
d) None of the above
58. The output of sequential circuit is regarded as a function of time sequence of
__________.
A. Inputs
B. Outputs
C. Internal States
D. External States
a) A & D
b) A & C
c) B & D
d) B & C
59. The time required for an input data to settle _____ the triggering edge of clock is
known as ‘Setup Time’.
a) Before
b) During
c) After
d) All of the above
60. Hold time is defined as the time required for the data to ________ after the
triggering edge of clock.
a) Increase
b) Decrease
c) Remain stable
d) All of the above
61. An Antifuse programming technology is predominantly associated with _____.
a) SPLDs
b) FPGAs
c) CPLDs
d) All of the above
62. In fusible link technologies, the undesired fuses are removed by the pulse
application of _____voltage & current to device input.
a) Low
b) Moderate
c) High
d) All of the above
63. Which programming technology/ies is/are predominantly associated with SPLDs
and CPLDs?
a) EPROM
b) EEPROM
c) FLASH
d) All of the above
64. Before the commencement of design, the clocking strategy determine/s __________
a) Number of clock signals necessary for routing throughout the chip
b) Number of transistors used per storage requirement
c) Power dissipated by chip & the size of chip
d) All of the above
65. Which method/s of physical clocking is/are a /the recursive structure where the
memory elements are grouped together to make the use of nearby or same
distribution points?
a) H tree
b) Balanced tree clock network
c) Both a and b
d) None of the above
66. Increase in the physical distance of H-tree _________the skew rate.
a) Increases
b) Stabilizes
c) Decreases
d) All of the above
67. In testability, which terminology is used to represent or indicate the formal
evidences of correctness?
a) Validation
b) Verification
c) Simulation
d) Integration
68. Which among the following is regarded as an electrical fault?
a) Excessive steady-state currents
b) Delay faults
c) Bridging faults
d) Logical stuck-at-0 or stuck-at-1
69. Which among the following faults occur/s due to physical defects?
a) Process variations & abnormalities
b) Defects in silicon substrate
c) Photolithographic defects
d) All of the above
70. In logic synthesis, ________ is an EDIF that gives the description of logic cells & their
interconnections.
a) Netlist
b) Checklist
c) Shitlist
d) Dualist
71. Which level of system implementation includes the specific function oriented
registers, counters & multiplexers?
a) Module level
b) Logical level
c) Physical level
d) All of the above
72. Which among the following is/are taken into account for post-layout simulation?
a) Interconnect delays
b) Propagation delays
c) Logic cells
d) All of the above
73. Which among the following operation/s is/are executed in physical design or
layout synthesis stage?
a) Placement of logic functions in optimized circuit in target chip
b) Interconnection of components in the chip
c) Both a and b
d) None of the above
74. In VHDL, which class of scalar data type represents the values necessary for a
specific operation?
a) Integer types
b) Real types
c) Physical types
d) Enumerated types
75. Which among the following is pre-defined in the standard package as one-
dimensional array type comprising each element of BIT type?
a) Bit type
b) Bit_vector type
c) Boolean type
d) All of the above
76. In VHDL, the record type comprises the elements of _______data types.
a) Same
b) Different
c) Both a and b
d) None of the above
77. Which among the following wait statement execution causes the enclosing
process to suspend and then wait for an event to occur on the signals?
a) Wait until Clk = ‘1’
b) Wait on x, y, z
c) Wait on clock until answer > 80
d) Wait for 12 ns
78. After an initialization phase, the simulator enters the ______phase.
a) Compilation
b) Elaboration
c) Execution
d) None of the above
79. Which concept proves to be beneficial in acquiring concurrency and order
independence?
a) Alpha delay
b) Beta delay
c) Gamma delay
d) Delta delay
80. An event is nothing but ______ target signal, which is to be updated.
a) Fixed
b) Change on
c) Both a and b
d) None of the above
81. Which functions are performed by static timing analysis in simulation?
a) Computation of delay for each timing path
b) Logic analysis in a static manner
c) Both a and b
d) None of the above
82. Which among the following is/are regarded as the function/s of translation step
in synthesis process?
a) Conversion of RTL description to boolean unoptimized description
b) Conversion of an unoptimized to optimized boolean description
c) Conversion of unoptimized boolean description to PLA format
d) All of the above
83. In synthesis flow, which stage/s is/are responsible for converting an un-
optimized boolean description to PLA format?
a) Translation
b) Optimization
c) Flattening
d) All of the above
84. In scan/set method, __________ is used to implement a scan path
a) serial registers
b) storage elements
c) parallel registers
d) separate register
85. In synthesis flow, the flattening process generates a flat signal representation of
_____levels.
A. AND
B. OR
C. NOT
D. EX-OR
a) A & B
b) C & D
c) A & C
d) B & D
86. If the level of fan-out is beyond a limit in synthesis, it results in an insertion of
buffer by ultimate effect of _____ the speed.
a) Enhancing
b) Reducing
c) Stabilizing
d) None of the above
87. Which among the following constraint/s is/are involved in a state-machine
description?
a) State variable & clock
b) State transitions & output specifications
c) Reset condition
d) All of the above
88. Which among the following is/are identical in Mealy & Moore machines?
a) Combinational output signal
b) Clocked Process
c) Both a and b
d) None of the above
89. Which method/s is/are adopted for acquiring spike-free outputs?
a) Moore machine with clocked outputs
b) Mealy machine with clocked outputs
c) Output-state machine
d) All of the above
90. In SM chart for UART transmitter, which state/s indicate/s the waiting of
sequential machine for the rising edge of bit clock and the consequent clearing of low
order bit of TSR in order to transmit logic ‘0’ for one bit time?
a) IDLE State
b) Sync State
c) Transmit Data State
d) All of the above
91. In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias
and other interconnection discontinuities?
a) Power/Ground Noise
b) Crosstalk Noise
c) Reflection Noise
d) All of the above
92. In floorplanning, placement and routing are __________ tools.
a) Front end
b) Back end
c) Both a and b
d) None of the above
93. In floorplanning, which phase/s play/s a crucial role in minimizing the ASIC area
and the interconnection density?
a. Placement
b. Global Routing
c. Detailed Routing
d. All of the above
94. Stuck open (off) fault occur/s due to _________
a) An incomplete contact (open) of source to drain node
b) Large separation of drain or source diffusion from the gate
c) Both a and b
d) None of the above
95. Which type/s of stuck at fault model exhibit/s the reduced complexity level of
test generation?
a) Single
b) Multiple
c) Both a and b
d) None of the above
96. Why is multiple stuck-at fault model preferred for DUT?
a) Because single stuck-at fault model is independent of design style & technology
b) Because single stuck-at tests cover major % of multiple stuck-at faults & un-modeled
physical defects
c) Because complexity of test generation is reduced to greater extent in multiple stuck-at
fault models
d) All of the above
97. Which among the following EDA tool is available for design simulation?
a) OrCAD
b) ALDEC
c) Simucad
d) VIVElogic
98. Which among the following functions are performed by MSI category of IC
technology?
a) Gates, Op-amps
b) Microprocessor/A/D
c) Filters
d) Memory/DSP
99. The ‘next’ statements skip the remaining statement in the ________ iteration of loop
and execution starts from first statement of next iteration of loop.
a) Previous
b) Next
c) Current (present)
d) None of the above
100. An Assert is ______ command.
a) Sequential
b) Concurrent
c) Both a and b
d) None of the above
101. Timing analysis is more efficient with synchronous systems whose maximum
operating frequency is evaluated by the _________path delay between consecutive flip-
flops.
a) Shortest
b) Average
c) Longest
d) unpredictable
102. What is/are the necessity/ies of Simulation Process in VHDL?
a) Requirement to test designs before implementation & usage
b) Reduction of development time
c) Decrease the time to market
d) All of the above
103. Why is the use of mode buffer prohibited in the design process of synthesizer?
a) To avoid mixing of clock edges
b) To prevent the occurrence of glitches & metastability
c) Because critical path has preference in placement
d) Because Maximum ASIC vendors fail to support mode buffer in library
104. If a port is declared as buffer, then which problem is generated in hierarchical
design due to mapping with port of buffer mode of other entities only?
a) Structural Modeling
b) Functional Modeling
c) Behavioral Modeling
d) Data Flow Modeling
105. In Gray coding, when the state machine changes state, ______ bit/s in the state
vector changes the value.
a) 1
b) 2
c) 4
d) 8
106. Which type of CPLD packaging comprises pins on all four sides that wrap
around the edges of chip?
a) Plastic-Leaded Chip Carrier (PLCC)
b) Quad Flat Pack (QFP)
c) Ceramic Pin Grid Array (PGA)
d) Ball Grid Array (BGA)
107. An antifuse element initial provides ______ between two conductors in absence of
the application of sufficient programming voltage.
a) Conduction
b) Insulation
c) Both a and b
d) None of the above
108. In spartan-3 family architecture, which programmable functional element
accepts two 18 bit binary numbers as inputs and computes the product?
a) Configurable Logic Blocks
b) Input Output Blocks
c) Block RAM
d) Multiplier Blocks
109. Which level of routing resources are supposed to be the dedicated lines
allowing output of each tile to connect directly to every input of eight surrounding
tiles?
a) Ultra-fast local resources
b) Efficient long-line resources
c) High speed, very long-line resources
d) High performance global networks
110. In a chip, which type/s of pad design/s is/are adopted to solve the problem of
pin count?
a) Input pad design
b) Output pad design
c) Three state pad design
d) All of the above
111. Which among the following is/are responsible for the occurrence of Delay
Faults ?
a) Variations in circuit delays & clock skews
b) Improper estimation of on-chip interconnect & routing delays
c) Aging effects & opens in metal lines connecting parallel transistors
d) All of the above
112. Due to the limitations of the testers, the functional test is usually performed at
speed _______the target speed.
a) Lower than
b) Equal to
c) Greater than
d. None of the above
113. High observability indicates that ________number of cycles are required to
measure the output node value.
a) More
b) Equal
c) Less
d) None of the above
114. Built-in self test aims to
a) reduce test pattern generation cost
b) reduce volume of test data
c) reduce test time
d) all of the mentioned
115. In data compression technique, comparison is done on
a) test response
b) entire test data
c) data inputs
d) output sequences
116. Signature analysis performs
a) addition
b) multiplication
c) polynomial division
d) amplifies
117. The signature analysis method can be represented mathematically as
a) R(x) = P(x) * C(x)
b) R(x) = P(x) / C(x)
c) R(x) = C(x) / P(x)
d) R(x) = C(x) * P(x)
118. BILBO uses only the signature analysis.
a) True
b) false
119. In which mode, storage elements are used independently?
a) Normal mode
b) test 1 mode
c) test 2 mode
d) final mode
120. Storage elements are connected as a serial shift In BILBO register when
a) B1=B2=1
b) B1=B2=0
c) B1=0, B2=1
d) B1=1, B2=0
121. The BILBO circuit is configured as LFSR, when
a) B1=B2=1
b) B1=B2=0
c) B1=0, B2=1
d) B1=1, B2=0
122. The BILBO is reset, when
a) B1=B2=1
b) B1=B2=0
c) B1=0, B2=1
d) B1=1, B2=0
123. The efficiency of the test pattern generation is improved by
a) adding buffers
b) adding multipliers
c) partitioning
d) adding power dividers
124. The scan path shift register is verified by
a) shifting in all zeroes first
b) shifting in all ones first
c) adding all ones
d) adding all zeroes
125. In test mode, storage elements are connected as
a) parallel shift registers
b) serial shift register
c) combiners
d) buffers
126. Which has more number of I/O pins?
a) LSSD
b) partial scan
c) scan/set
d) Random access scan
127. Scan/set method has no interruption to normal operation.
a) True
b) false
128. The serial shift register is driven using
a) one over-lapping clock
b) two over-lapping clock
c) one non over-lapping clock
d) two non over-lapping clock
129. In scan/set method __________ is used to implement a scan path.
a) Serial registers
b) storage elements
c) parallel registers
d) separate register
130. general synchronous system are composed of the following three individual
subsystems:
1) memory storage elements
2) logic elements
3) clocking circuitry and distribution network
a) True
b) False
131. The difference in clock signal arrival time between two sequentially-adjacent
registers is knows as
a) Gate delay
b) Fan-in delay
c) Sequential Delay
d) Clock Skew
132. Which among the following is/are responsible for the occurrence of clock skew
by introducing delays from different paths of clock generator to various circuits
a) Different length of wires
b) Gates on the paths
c) Gating of clock to control the loading of registers
d) All of the above
133. Latches are level triggered
a) True
b) False
134. VLSI technology uses ________ to form integrated circuit.
a) Transistors
b) switches
c) diodes
d) buffers
135. Medium scale integration has ____________
a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates
136. As die size shrinks, the complexity of making the photomasks ____________
a) increases
b) decreases
c) remains the same
d) cannot be determined
137. An unconstrained array type is a type whose index range is not defined
a) True
b) false
138. Signals can be declared in packages (global signals), entities (entity global
signals), architectures (architecture global signals) and blocks.
a) True
b) false
139. Variables declared within a process cannot pass values outside of the process
a) True
b) false
140. Which of the following is standardised as IEEE 1364?
a) C
b) C++
c) FORTRAN
d) Verilog
141. Who developed the Verilog?
a) Moorby
b) Thomas
c) Russell and Ritchie
d) Moorby and Thomson
142. Which versions of the Verilog is known as System Verilog?
a) Verilog version 3.0
b) Verilog version 1.0
c) Verilog version 1.5
d) Verilog version 4.0
143. Which of the following is a Verilog version 1.0?
a) IEEE standard 1394-1995
b) IEEE standard 1364-1995
c) IEEE standard 1394-2001
d) IEEE standard 1364-2001
144. Which of the following provides multiple-valued logic with eight signal
strength?
a) Verilog
b) VHDL
c) C
d) C++
145. Which of the following is a superset of Verilog?
a) Verilog
b) VHDL
c) System Verilog
d) System VHDL
146. Which hardware description language is more flexible?
a) VHDL
b) Verilog
c) C
d) C++
147. Which of the following provide more features for transistor-level descriptions?
a) C++
b) C
c) VHDL
d) Verilog
148. The default value for reg data type is ______.
a) 0
b) Z
c) 1
d) X
149. The possible value(s) of the == operator are________.
a) 0
b) Z
c) 1
d) X
150. To suspend a simulation, you can use this system task command.
a) $finish
b) $stop
c) $end
d) $close
151. ______ operator usually comes before the operand.
a) Unary
b) Binary
c) Ternary
d) None
152. @posedge means
a) Transition from x to 1
b) Transition from 0 to 1, X or Z
c) Transition from x to 1
d) Transition from 1 to 0
153. The wait statement is
a) Edge Sensitive
b) Level Sensitive
c) Both
d) None
154. To trigger an event , we can use following operator
a) @
b) ==
c) =>
d) ->
155. ______ defines special parameters in the specify block.
a) specparam
b) parameter
c) defparam
d) param
156. To introduce delays in a circuit, we can use a _________
a) Buffer
b) Flip Flop
c) Both
d) None
157. The keyword deassign is a
a) procedural continuous assignment
b) continuous assignment statement
c) blocking assignment statement
d) nonblocking assignment statement
158. The phenomenon of clock skew is found in ________
a) Asynchronous circuit
b) synchronous circuit
c) Both
d) None