Eval l9026 Yo
Eval l9026 Yo
Data brief
Features
• Operating input voltage: 3 V to 18 V
• Two fixed high-side drivers up to 1 A
• Six configurable HS/LS drivers up to 1 A
• Idle mode for reduced current consumption
• Possible Daisy chain configuration
• Two parallel input pins with Input mapping functionality
• SPI communication interface for control and diagnostics
• Configurable dip switch for all available L9026 configurations
• Reference design with optimized bill of materials
• L9026 hosted in HTSSOP24 package
• 4-layer PCB (80 x 65 mm)
Description
The EVAL-L9026-YO is a low-cost tool designed to evaluate L9026, a smart power
device designed by STMicroelectronics in advanced BCD technology. The L9026 is
an eight channels IC, with 2 fixed HS drivers and 6 configurable HS/LS drivers
designed for Automotive applications (LEDs and Relays) and compatible with
resistive, inductive, and capacitive loads. The device offers advanced diagnostic and
protection functionalities such as: short to GND, open load, overcurrent, over-
temperature detections. The 8 output channels can be either driven by SPI or by 2
dedicated parallel inputs that can be associated to different output thanks to a
Product status link programmable internal multiplexer. Limp home functionality is also featured, which
EVAL-L9026-YO allows using 2 selected drivers in particular, faulty, conditions, such as SPI fault,
microcontroller fault or supply UV. Daisy chain compatibility even with 8bit SPI is
Product summary available. The device is able to guarantee operations under cranking scenario down
to VBATT = 3 V and guarantees very low quiescent current under RESET condition.
Order code EVAL-L9026-YO A serial peripheral interface (SPI) is used for control and configuration of the loads as
Reference Evaluation board well as of the device; besides, status feedback of all diagnostic functions is provided.
For direct control and PWM there are two input pins available: these are connected
Order code PTSCONNECTUM to two defined outputs by default, but additional or different output mapping can be
Reference Hardware interface controlled by SPI. Thanks to the expansion connectors, EVAL-L9026-YO allows the
complete control of L9026 communication interface (SPI) and parallel input/output.
All the possible configuration on the single channel can be easily managed thanks to
dip switches. The evaluation board can be also controlled with Graphical User
Interface available on PTSCONNECTUM hardware interface.
1 Electrical characteristics
2 System requirements
3 External connection
SW DIP-6
Imax 2A S2 GND
Imax 2A P4 P2
SOURCE2 1 12 P6
SOURCE3 2 11 DRAIN2
1 24 23 1 2 R1 1K
SOURCE4 3 10 DRAIN3 IN0
GND 2 22 21 R2 1K 3 4
SOURCE5 4 9 DRAIN4 IN1 R3 1K SI
3 20 19 5 6
SOURCE6 5 8 DRAIN5 SO R4 1K CLK
4 18 17 7 8
SOURCE7 6 7 DRAIN6 NCS
5 16 15 9 10 R5 1K
DRAIN7 GND PTS GND PTS
6 14 13 R6 1K 11 12
SW DIP-6
C5 C6 C7 C8 C9 C10 Header 6 12 11 R7 1K 13 14
IDLE
10nF 10nF 10nF 10nF 10nF 10nF 10 9 15 16
P5 8 7 17 18
Imax 2A 100V100V 100V 100V 100V 100V VCC_PTS
SOURCE0 6 5 19 20
1 GND
SOURCE1 4 3 21 22
2
SOURCE2 2 1 23 24
3
SOURCE3 This capacitor must
4 Header 12X2 Header 12X2
SOURCE4 be placed as close as
5
SOURCE5 possible to connector
6
SOURCE6 GND
7
SOURCE7
8
C11 C12 C13 C14 C15 C16 C17 C18 Header 8
SOURCE5
SOURCE6
SOURCE7
SOURCE0
SOURCE1
SOURCE2
SOURCE3
SOURCE4
DRAIN5
DRAIN6
DRAIN7
DRAIN2
DRAIN3
DRAIN4
10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF
VBAT
CLK
NCS
IN0
IN1
SO
SI
This capacitor must
be placed as close as
possible to connector
GND L9026
EXPAD
Revision history
Contents
1 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 System requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 External connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
4 Evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Appendix A Reference documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
List of figures
Figure 1. Connection with an arbitrary microcontroller board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Connection using PT&S Connect tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. Evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5