PIC Microcontrollers

PIC stands for Peripheral Interface Controller given by Microchip Technology to identify its single-chip microcontrollers. These
devices have been very successful in 8-bit microcontrollers. The main reason is that Microchip Technology has continuously
upgraded the device architecture and added needed peripherals to the microcontroller to suit customers' requirements. The
development tools such as assembler and simulator are freely available on the internet at www.microchip.com .

The architectures of various PIC microcontrollers can be divided as follows.

Low - end PIC Architectures :
Microchip PIC microcontrollers are available in various types. When PIC microcontroller MCU was first available from General
Instruments in early 1980's, the microcontroller consisted of a simple processor executing 12-bit wide instructions with basic I/O
functions. These devices are known as low-end architectures. They have limited program memory and are meant for applications
requiring simple interface functions and small program & data memories. Some of the low-end device numbers are

12C5XX
16C5X
16C505
Mid range PIC Architectures
Mid range PIC architectures are built by upgrading low-end architectures with more number of peripherals, more number of registers
and more data/program memory. Some of the mid-range devices are

16C6X
16C7X
16F87X

Program
C
F
RC = Mask ROM

memory

type

is

indicated

by

=
=

an

alphabet.
EPROM
Flash

Popularity of the PIC microcontrollers is due to the following factors.

1.

Speed: Harvard Architecture, RISC architecture, 1 instruction cycle = 4 clock cycles.

2.

Instruction set simplicity: The instruction set consists of just 35 instructions (as opposed to 111 instructions for 8051).

3.

Power-on-reset and brown-out reset. Brown-out-reset means when the power supply goes below a specified voltage (say
4V),
it
causes
PIC
to
reset;
hence
malfunction
is
avoided.
A watch dog timer (user programmable) resets the processor if the software/program ever malfunctions and deviates from
its normal operation.

4.

PIC microcontroller has four optional clock sources.

o

Low power crystal

Mid range crystal

High range crystal

RC oscillator (low cost).

5.

Programmable timers and on-chip ADC.

6.

Up to 12 independent interrupt sources.

7.

Powerful output pin control (25 mA (max.) current sourcing capability per pin.)

8.

EPROM/OTP/ROM/Flash memory option.

9.

I/O port expansion capability.

10. Free assembler and simulator support from Microchip at www.microchip.com

CPU Architecture:
The CPU uses Harvard architecture with separate Program and Variable (data) memory interface. This facilitates instruction fetch
and the operation on data/accessing of variables simultaneously.

Fig 16.1 CPU Architecture of PIC microcontroller

PIC Memory Organisation:
PIC microcontroller has 13 bits of program memory address. Hence it can address up to 8k of program memory. The program
counter is 13-bit. PIC 16C6X or 16C7X program memory is 2k or 4k. While addressing 2k of program memory, only 11- bits are
required. Hence two most significant bits of the program counter are ignored. Similarly, while addressing 4k of memory, 12 bits are
required. Hence the MSb of the program counter is ignored.

Fig 16.2 Program Memory map

The
program
memory
map
of
PIC16C74A
is
shown
in
Fig
16.2.
On reset, the program counter is cleared and the program starts at 00H. Here a 'goto' instruction is required that takes the processor
to the mainline program.
When a peripheral interrupt, that is enabled, is received, the processor goes to 004H. A suitable branching to the interrupt service
routine (ISR) is written at 004H.

Data memory (Register Files):

Data Memory is also known as Register File. Register File consists of two components.

1.

General purpose register file (same as RAM).

2.

Special purpose register file (similar to SFR in 8051).

Fig 16.3 Data Memory map

The special purpose register file consists of input/output ports and control registers. Addressing from 00H to FFH requires 8 bits of
address. However, the instructions that use direct addressing modes in PIC to address these register files use 7 bits of instruction
only. Therefore the register bank select (RP0) bit in the STATUS register is used to select one of the register banks.
In indirect addressing FSR register is used as a pointer to anywhere from 00H to FFH in the data memory.

Specifications of some popular PIC microcontrollers are as follows:

Device

Program
Memory
(14bits)

Data RAM
(bytes)

I/O
ADC
Pins

16C74A

4K EPROM

192

33

16F877

8K Flash

368 (RAM)
256 (EEPROM)

33

Timers
8/16
bits

CCP
(PWM)

USART
SPI / I2C

8 bits x
2/1
8 channels

USART
SPI / I2C

10 bits x 2/1
8 channels

USART
SPI / I2C

Device

Interrupt
Sources

Instruction
Set

16C74A

12

35

16F877

15

35

PIC Microcontroller Clock

Most of the PIC microcontrollers can operate upto 20MHz. One instructions cycle
(machine cycle) consists of four clock cycles.

Fig 17.1 Relation between instruction cycles and clock cycles for PIC
microcontrollers
Instructions that do not require modification of program counter content get
executed in one instruction cycle.
Although the architectures of various midrange 8 - bit PIC microcontroller are not
the same, the variation is mostly interns of addition of memory and peripherals. We
will discuss here the architecture of a standard mid-range PIC microcontroller,
16C74A. Unless mentioned otherwise, the information given here is for a PIC
16C74A microcontroller Chip.Architecture of PIC16C74A

Fig 17.2 Basic Architecture of PIC 16C74A

The basic architecture of PIC16C74A is shown in fig 17.2. The architecture consists
of Program memory, file registers and RAM, ALU and CPU registers. It should be
noted that the program Counter is 13 - bit and the program memory is organised as
14 - bit word. Hence the program Memory capacity is 8k x 14 bit. Each instruction of
PIC 16C74A is 14 - bit long. The various CPU registers are discussed here.
CPU registers (registers commonly used by the CPU)
W, the working register, is used by many instructions as the source of an operand.
This is similar to accumulator in 8051. It may also serve as the destination for the
result of the instruction execution. It is an 8 - bit register.

Fig 17.3

W register

STATUS Register
The STATUS register is a 8-bit register that stores the status of the processor. This
also stores carry, zero and digit carry bits.
STATUS - address 03H, 83H

Fig 17.4 STATUS register

C = Carry bit
DC = Digit carry (same as auxiliary carry)
Z = Zero bit
NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode
RP0- Register bank select bit used in conjunction with direct addressing mode.
FSR Register
(File Selection Register, address = 04H, 84H)
FSR is an 8-bit register used as data memory address pointer. This is used in indirect
addressing mode.
INDF Register
(INDirect through FSR, address = 00H, 80H)
INDF is not a physical register. Accessing INDF access is the location pointed to by
FSR in indirect addressing mode.
PCL Register
(Program Counter Low Byte, address = 02H, 82H)
PCL is actually the lower 8-bits of the 13-bit program counter. This is a both
readable and writable register.
PCLATH Register
(Program Counter Latch, address = 0AH, 8AH)
PCLATH is a 8-bit register which can be used to decide the upper 5bits of the
program counter. PCLATH is not the upper 5bits of the program counter. PCLATH can
be read from or written to without affecting the program counter. The upper 3bits of
PCLATH remain zero and they serve no purpose. When PCL is written to, the lower
5bits of PCLATH are automatically loaded to the upper 5bits of the program counter,
as shown in the figure.

Fig 17.5 Schematic of how PCL is loaded from PCLATH

Program Counter Stack
An independent 8-level stack is used for the program counter. As the program
counter is 13bit, the stack is organized as 8x13bit registers. When an interrupt
occurs, the program counter is pushed onto the stack. When the interrupt is being
serviced, other interrupts remain disabled. Hence, other 7 registers of the stack can
be used for subroutine calls within an interrupt service routine or within the
mainline program.
Register File Map

Fig 17.6 Register File Map

It can be noted that some of the special purpose registers are available both in
Bank-0 and Bank-1. These registers have the same value in both banks. Changing
the register content in one bank automatically changes its content in the other
bank.
Port Structure and Pin Configuration of PIC 16C74A
As mentioned earlier, there is a large variety of PIC microcontrollers. However, the
midrange architectures are widely used. Our discussion will mainly confine to
PIC16C74A whose architecture has most of the required features of a mid-range PIC
microcontroller. Study of any other mid-range PIC microcontroller will not cause
much variation from the basic architecture of PIC 16C74A ..
PIC 16C74A has 5 I/O Ports. Each port is a bidirectional I/O port. In addition, they
have the following alternate functions.

In addition to I/O pins, there is a Master clear pin (MCLR) which is equivalent to reset
in 8051. However, unlike 8051, MCLR should be pulled low to reset the micro
controller. Since PIC16C74Ahas inherent power-on reset, no special connection is
required with MCLR pin to reset the micro controller on power-on.
There are two VDD pins and two VSS pins. There are two pins (OSC1 and OSC2) for
connecting the crystal oscillator/ RC oscillator. Hence the total number of pins with a
16C74A is 33+7=40. This IC is commonly available in a dual-in-pin (DIP) package.

Fig 17.7 Pin configuration of PIC 16C74A

Guidelines from Microchip Technology
For writing assembly language program Microchip Technology has suggested the following
guidelines.
1. Write instruction mnemonics in lower case. (e.g., movwf)
2. Write the special register names, RAM variable names and bit names in upper case.
(e.g., PCL, RP0, etc.)
3. Write instructions and subroutine labels in mixed case. (e.g., Mainline, LoopTime)
Instruction Set:
The instruction set for PIC16C74A consists of only 35 instructions. Some of these instructions
are byte oriented instructions and some are bit oriented instructions.
The byte oriented instructions that require two parameters (For example, movf f, F(W))
expect the f to be replaced by the name of a special purpose register (e.g., PORTA) or the name
of a RAM variable (e.g., NUM1), which serves as the source of the operand. 'f' stands for file
register. The F(W) parameter is the destination of the result of the operation. It should be
replaced by:
F, if the destination is to be the source register.
W, if the destination is to be the working register (i.e., Accumulator or W register).
The bit oriented instructions also expect parameters (e.g., btfsc f, b). Here 'f' is to be
replaced by the name of a special purpose register or the name of a RAM variable. The 'b'

parameter is to be replaced by a bit number ranging from 0 to 7.

For example:
Z equ 2
btfsc STATUS, Z
Z has been equated to 2. Here, the instruction will test the Z bit of the STATUS register and will
skip the next instruction if Z bit is clear.
The literal instructions require an operand having a known value (e.g., 0AH) or a label that
represents a known value.
For example:
NUM equ 0AH ;
movlw NUM ;

Assigns 0AH to the label NUM ( a constant )

will move 0AH to the W register.

Every instruction fits in a single 14-bit word. In addition, every instruction also executes in a
single cycle, unless it changes the content of the Program Counter. These features are due to
the fact that PIC micro controller has been designed on the principles of RISC (Reduced
Instruction Set Computer) architecture.
Instruction set:
Mnemonics

Description

Instructi
on Cycles

bcf f, b

Clear bit b of register f

bsf f, b

Set bit b of register f

clrw

Clear working register W

clrf f

Clear f

movlw k

Move literal 'k' to W

movwf f

Move W to f

movf f, F(W)

Move f to F or W

swapf f, F(W)

Swap nibbles of f, putting result in F or W

andlw k

And literal value into W

andwf f, F(W)

And W with F and put the result in W or F

andwf f, F(W)

And W with F and put the result in W or F

iorlw k

inclusive-OR literal value into W

iorwf f, F(W)

inclusive-OR W with f and put the result in F or W 1

xorlw k

Exclusive-OR literal value into W

xorwf f, F(W)

Exclusive-OR W with f and put the result in F or W 1

addlw k

Add the literal value to W and store the result in

W

addwf f, F(W)

Add W to f and store the result in F or W

sublw k

Subtract the literal value from W and store the

result in W

subwf f, F(W)

Subtract f from W and store the result in F or W

rlf f, F(W)

Copy f into F or W; rotate F or W left through the

carry bit

rrf f, F(W)

Copy f into F or W; rotate F or W right through the

1
carry bit

btfsc f, b

Test 'b' bit of the register f and skip the next

instruction if bit is clear

1/2

btfss f, b

Test 'b' bit of the register f and skip the next

instruction if bit is set

1/2

decfsz f, F(W)

Decrement f and copy the result to F or W; skip

the next instruction if the result is zero

1/2

incfcz f, F(W)

Increment f and copy the result to F or W; skip the

1/2
next instruction if the result is zero

goto label

Go to the instruction with the label "label"

call label

Go to the subroutine "label", push the Program

Counter in the stack

retrun

Return from the subroutine, POP the Program

Counter from the stack

retlw k

Retrun from the subroutine, POP the Program

Counter from the stack; put k in W

retie

Return from Interrupt Service Routine and re-

enable interrupt
clrwdt

Clear Watch Dog Timer

sleep

Go into sleep/ stand by mode

nop

No operation

Encoding of instruction:
As has been discussed, each instruction is of 14-bit long. These 14-bits contain both op-code
and the operand. Some examples of instruction encoding are shown here.
Example-1:
bcf f, b

Clear 'b' bit of register 'f'

Operands:

0 f 127
0b7

Encoding:

The instruction is executed in one instruction cycle, i.e., 4 clock cycles. The activities in various
clock cycles are as follows.

Example-2:
goto K

Go to label 'k' instruction

Operand:

0 K 2047 (11-bit address is specified)

Operation:

Encoding:

PC <10:0>
PCLATH <4:3>

PC <12:11>

Since this instruction requires modification of program Counter, it takes two instruction cycles
for execution.
Q-Cycle activities are shown as follows.

Discussion on I/O ports of PIC16C74A:

PIC16C74A has five I/O ports. Port-B, Port-C and Port-D have 8 pins each. Port-A and Port-E have
6 and 3 pins respectively. Each port has bidirectional digital I/O capability. In addition, these I/O
ports are multiplexed with alternate functions for the peripheral devices on the microcontroller.
In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O
pin. Each port latch has a corresponding TRIS (Tri-state Enable) register for configuring the port
either as an input or as an output. The port pins are designated by the alphabet R, followed by
the respective port (viz. A, B, C, D or E) and the pin number. For example, Port-A pins are
named as RA0, RA1, etc.
Port-A
Port-A pins RA0-RA3 and RA5 are similar. These pins function (alternate function) as analog
inputs to the analog-to-digital converter.

Fig 19.1 RA0-RA3 and RA5 pin of Port-A

The structure of Port-A pins RA0-RA3 and RA5 is shown in the figure. TRISA register decides
whether the port-pin is configured as an input or as an output (digital) pin. Setting a TRISA
register bit puts the corresponding output driver in high impedance mode. In this mode, the pin
can be used as a digital or analog input. Clearing a bit in the TRISA register puts the contents
of the data latch on the selected pins, i.e., the pin functions as a digital output. Pins RA0-RA
and RA5 have current sourcing capability of 25mA.
The alternate function of RA4 pin is Timer-0 clock input (T0CKI). RA4 pin is an open drain pin
and hence requires external pull-up when configured as output pin. It is shown in the following
figure.

Fig 19.2 RA4 pin Configuration

Configuration of Port-A pins
Example :

Set RA0-RA3 as outputs and RA4 - RA5 as inputs.

bcf STATUS, RP0 ;

clrf PORTA ;
bsf STATUS, RP0 ;
movlw 30H ;
movwf TRISA ;

Select Bank-0
Clears the data latch
Select Bank-1
W
03H ( data direction )
Set RA0-RA3 as outputs, RA4-RA5 as inputs

Port-B
Port-B is an 8-bit bidirectional I/O port. The data direction in Port-B is controlled by TRISB
register. Setting a bit in TRISB register puts the corresponding output in high impedance input
mode. When a bit in TRISB is made zero, the corresponding pin in Port-B outputs the content of
the latch (output mode).
Each port pin has a weak internal pull-up that can be enabled by clearing bit
of OPTION
register (bit-7). When a pin is configured in the output mode, the weak pull-up is automatically
turned off. Internal pull-up is used so that we can directly drive a device from the pins.

Fig 19.3 Pins RB0-RB3 of Port-B

Configuration of Port-B pins
Example :
bcf STATUS, RP0
clrf PORTB
bsf STATUS, RP0
movlw 70H
movwf TRISB

Set RB0-RB3 as outputs, RB4-RB5 as inputs, RB7 as output.

Overview of Timer Modules :

PIC 16C74A has three modules, viz., Timer-0, Timer-1 and Timer-2. Timer-0 and Timer-2 are 8-bit timers. Timer-1 is a 16-bit timer.
Each timer module can generate an interrupt on timer overflow.

Timer-0 Overview:

The timer-0 module is a simple 8-bit UP counter. The clock source can be either the internal clock (f osc /4) or an external clock. When
the clock source is external, the Timer-0 module can be programmed to increment on either the rising or falling clock edge. Timer-0
module has a programmable pre-scaler option. This pre-scaler can be assigned either to Timer-0 or the Watch dog timer, but not to
both.
The Timer-0 Counter sets a flag T0IF (Timer-0 Interrupt Flag) when it overflows and can cause an interrupt at that time if that
interrupt source has been enabled, (T0IE = 1), i.e., timer-0 interrupt enable bit = 1.
OPTION Register Configuration :
Option Register (Addr: 81H) Controls the prescaler and Timer -0 clock source. The following OPTION register configuration is for
clock source = fosc /4 and no Watchdog timer.

Timer-0 use without pre-scalar

Internal clock source of f osc /4. (External clock source, if selected, can be applied at RA4/TOCKI input at PORTA).
The following diagram shows the timer use without the prescaler.

Fig 20.1 Timer - 0 operation without prescaler

Timer-0 use with pre-scalar:

The pre-scalar can be used either with the Timer-0 module or with the Watchdog timer. The pre-scalar is available for Timer-0 if the
pre-scalar assignment bit PSA in the OPTION register is 0. Pre-scalar is a programmable divide by n counter that divides the
available clock by a pre-specified number before applying to the Timer-0 counter.

Fig 20.2 Timer - 0 with prescaler

imer - 1 Module
Timer 1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L)
which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from
0000H to FFFFH and rolls over to 0000H. The TMR1 interrupt, if enabled, is generated on
overflow, which sets the interrupt flag bit TMR1IF (bit-0 of PIR1 register). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (bit-0 of the PIE1
register).
The operating and control modes of Timer1 are determined by the special purpose register
T1CON.
Various bits of T1CON register are given as follows:-

Fig 21.1 T1CON Register

TMR1 ON :
TMR1CS :

Timer1 ON bit
0 = stops Timer 1;

1 = Enables Timer 1

Timer 1 Clock source Select Bit

1 = External Clock (RCO/T1OSO/T1CKI)
0 = Internal Clock (

Timer 1 External Clock Input Synchronization Bit

(Valid if TMR1CS = 1)
1 - Do not synchronize
0 - Synchronize

T1OSCEN:

Oscillator enable control bit

1 = Oscillator is enabled
0 = Oscillator is shut off

Timer 1 Input Clock Prescaler

Select bits

Prescaler Value

T1CKPS T1CKPS
1
0
1

1:8

1:4

1:2

1:1

Fig 21.2

Operation of Timer 1

Timer 1 can operate in one of the two modes

As a timer (TMR1CS = 0). In the timer mode, Timer 1 increments in every instruction
cycle. The timer 1 clock source is
. Since the internal clock is selected, the timer is
always synchronized and there is no further need of synchronization.

As a counter (TMR1CS = 1). In the counter mode, external clock input from the pin
RCO/T1CKI is selected.

Reading and writing Timer 1

Reading TMR1H and TMR1L from Timer 1, when it is running from an external clock source,
have to be done with care. Reading TMR1H or TMR1L for independent 8 - bit values does not
pose any problem. When the 16-bit value of the Timer is required, the high byte (TMR1H) is
read first followed by the low byte (THR1lL). It should be ensured that TMR1L does not
overflow (that is goes from FFH to 00H) since THR1H was read. This condition is verified by
reading TMR1H once again and comparing with previous value of TMR1H.
Example Program
Reading 16bit of free running Timer 1
movf TMR1H
;
read high byte
movwf TMPH
;
store in TMPH
movf TMR1L
;
read low byte
movwf TMPL
;
store in TMPL
movf TMR1H, W
;
read high byte in W
subwf TMPH, W
;
subtract 1 st read with 2 nd read
btfsc STATUS, Z
;
and check for equality
goto next ;
; if the high bytes differ, then there is an overflow
; read the high byte again followed by the low byte
movf TMR1H, W
;
read high byte
movwf TMPH
movf TMR1L, W
;
read low byte
movwf TMPL
next : nop

Timer 2 Overview

Fig 21.3

Schematic diagram showing operation of Timer 2

Timer 2 is an 8 - bit timer with a pre-scaler and a post-scaler. It can be used as the PWM time
base for PWM mode of capture compare PWM (CCP) modules. The TMR2 register is readable
and writable and is cleared on device reset.
The input clock (
) has a pre-scaler option of 1:1, 1:4 or 1:16 which is selected by bit 0
and bit 1 of T2CON register respectively.
The Timer 2 module has an 8bit period register (PR2). Timer-2 increments from 00H until it is
equal to PR2 and then resets to 00H on the next clock cycle. PR2 is a readable and writable
register. PR2 is initailised to FFH on reset.
The output of TMR2 goes through a 4bit post-scaler (1:1, 1:2, to 1:16) to generate a TMR2
interrupt by setting TMR2IF.

Fig 21.4 The T2CON Register

Interrupt Logic in PIC 16C74A
PIC 16C74A microcontroller has one vectored interrupt location (i.e., 0004H) but has 12
interrupt sources. There is no interrupt priority. Only one interrupt is served at a time. However
interrupts can be masked. The interrupt logic is shown below :

Fig 21.5

Schematic diagram showing the interrupt logic for PIC

Capture / Compare /PWM (CCP) Modules:

PIC16C74A has two CCP Modules. Each CCP module contains a 16 bit register (two 8-bit registers) and can operate in one of the
three modes, viz., 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM). The details of the two modules
(CCP1 and CCp2) are given as follows.

CCP1 Module:

CCP1 Module consists of two 8-bit registers, viz., CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the
operation of CCP1 Module.
CCP2 Module:
CCP2 Module consists of two 8 bit registers, viz., CCPR2L (Low byte) and CCPR2H (high byte). The CCP1CON register controls
the operation of CCP2 Module.
Both CCP1 and CCP2 modules are identical in operation with the exception of the operation of special event trigger.

The following table shows the timer resources for the CCP Mode.

CCP Mode

Timer Used

Capture

Timer 1

Compare

Timer 1

PWM

Timer 2

CCP1CON Register (Address 17H )

CCP2CON Register is exactly similar to CCP1CON register. CCP2CON Register address is 1DH. CCP1CON controls CCP
module1 where as CCP2CON controls CCP Module2.

Bit
5-4:
CCP1X CCP1Y: PWM least significant bits. These bits are of no use in Capture mode. In PWM Mode, these bits are the two Lsbs of
the PWM duty cycle. The eight Msbs are found in CCPR1L. Thus the PWM mode operates in 10-bit mode.
Bit
3-0:
CCP1M3:CCP1MO
(CCP1
Mode
select
bits)
0000=Capture/Compare/PWM
Mode
off

ADC Module

An analog-to-digital converter (ADC) converts an analog signal into an equivalent digital number. PIC 16C74A has an inbuilt ADC
with the following features -

8-bit conversion

8 analog input channels

An analog multiplexer

A sample and hold circuit for signal on the selected input channel

Alternative clock sources for carrying out conversion

Adjustable sampling rate

Choice of an internal or external reference voltage

Interrupt to microcontroller on end of conversion

Port A and Port E pins are used for analog inputs/reference voltage for ADC. In A/D conversion, the input analog voltage is digitized
and an equivalent digital output is generated as shown in the figure.

Fig 23.1 Digital output versus analog input

Port-A pins (Alternate functions)

Most of mid range PIC microcontrollers include a Synchronous Serial Port (SSP) Module. The discussion in this section is relevant
to PIC16C74A only. SSP Module section can be configured in either of the following two modes.

Serial Peripheral Interface (SPI)

Inter Integrated Circuit (I2C)

Either of these modes can be used to interconnect two or more PIC chips to each other using a minimal number of wires for
communication. Alternatively, either can be used to connect a PIC microcontroller to a peripheral chip. When I 2C mode is selected,
the peripheral chip must also have an I 2C interface. On the other hand, the SPI mode provides the clock and serial data lines for
direct connection to shift registers. This leads to increased I/O interface capability and an arbitrary number of I/O devices can be
connected to a PIC microcontroller. SPI can also achieve data rate significantly higher than I2C. Both the communication methods
are synchronous, i.e., the data transfer is synchronized with an explicit clock signal.
Two special purpose registers control the synchronous serial port (SSP) operations. These registers are:

SSPCON (Synchronous Serial Port Control Register), Address: 14H

SSPSTAT(Synchronous Serial Port status Register), Address: 94H

Serial Peripheral Interface (SPI)

Port-C three pins, viz., RC5/SDO, RC4/SDI and RC3/SCK/SCL are mainly used for SPI mode. In addition, one Port-A pin, viz.,
RA5/
/AN4 is used for slave select. The schematic block diagram of SPI is shown in the figure

Fig 24.1 Schematic diagram under SPI Mode

The SPI port requires RC3/SCK pin to be an output that generates the clock signal used by the external shift registers. When SPI is
configured in the slave mode, RC3/SCK pin works as the input for the clock.
When a byte is written to SSPBUF register, it is shifted out of RC5/SDO pin in synchronous with the emitted clock pulses on
RC3/SCK pin. The MSB of SSPBUF is the first bit to appear on RC5/SDO pin. Simultaneously, the same write to SSPBUF also
initiates the 8 bit data reception into SSPBUF of whatever appears on RC4/SDI pin at the time of rising edges of the clock on SCK
pin. Hence shifting-in and shifting-out of data occur simultaneously.

Fig 24.2 SPI Master / Slave Connection

The schematic diagram of SPI Master/Slave connection is shown in the figure.
Timing diagram for data transfer in 'Master mode' :

SSPIF interrupt flag is cleared by the user software if already in the set mode. The interrupt is enabled. Any write to SSPBUF
initiates the data transfer, i.e., transmission and reception. The clock pulses (8 clock pulses) are output through SCK pin. The data is
received through SDI. When CKP=1 (SSPCON<4>), data changes at SDO at negative clock transition and is read through SDI at
positive clock transition. The idle state of clock is high. If CKP=0, data appears at SDO at positive clock transition and is read
through SDI at negative clock transition. The idle state of the clock is low. These are shown in the following diagrams.

(i) Timing diagram for CKP=1

(ii) Timing diagram for CKP=0

Fig 24.3 Timing Diagram under SPI mode

Though SPI is a serial communication interface, it can be used to realize multiple output parallel ports and multiple input parallel ports.
We will consider this realization of an output parallel port and an input port separately.
Parallel Output Port Realization
A parallel 8-bit output port can be realized through SPI with the help of a shift register chip (74HC595) as shown in Fig 25.1. RC5/SD0
pin outputs serial data while RC3/SCK oin outputs the serial clock. Since input data transfer is not required, port pin RC4/SDI is used to
latch the shift register data to the output pins of the shift register. Hence RC4 is configured as an output pin.

Fig 25.1 PIC connection (in SPI mode) with a shift register
When an 8-bit data is written to SSPBUF, the data is shifted out of RC5/SD0 pin. With CKP = 1, the data is stable at the positive
transition but changes at the negative transition. The shift shifts the data at the positive clock transition. After 8 clock pulses, all 8-bits
are shifted in the shift register. The completion of data transfer is indicated by SSPIF interrupt flag becoming ' 1' . The interrupt service
routine make RC4 ' 1' , thus latching the 8-bit data to the output of the shift register. The configuration of various registers are shown in
Fig 25.2
Port configurations

Fig 25.2 Various Register Configurations

Parallel Input Port Realization
A shift register (74HC165) is connected to the PIC microcontroller as shown in Fig 25.3. Pin RD7 is configured as an output and is used
to load 8-bit data to the shift register. A dummy write to SSPBUF initiates data transfer. Data bit is read into RC4/SDI at the negative
clock transition (CKP = 0) where the data bit is stable. Data is shifted in the shift register at the position clock transition as shown in the
timing diagram. After the completion of data transfer, SSPIF interrupt flag goes high. Therafter the 8-bit data can be read by reading
SSPBUF.

Fig 25.3 Realization of an 8-bit parallel input port with PIC in SPI mode.
Port configurations
Fig 25.4 gives the configurations various registers for inputs parallel port realization.

Fig 25.4 Configurations of various registers for parallel input port

I2C Communication in PIC Microcontroller

I 2C stands for Inter-Integrated circuit. I 2C communication is a two wire bi-directional interface for connecting one or more master
processors with one or more slave devices, such as an EEPROM, ADC, RAM, LCD display, DAC, etc. I 2C interface requires two
open drain I/O pins, viz. SDA (Serial Data) and SCL (Serial Clock).

The reason for open drain connection is that the data transfer is bi-directional and any of the devices connected to the I 2C bus can
drive the data line (SDA). The serial clock line (SCL) is usually driven by the master. Since SDA and SCL pins are open drain pins,
external pull-up resistances are required for operation of I 2C bus.
A typical I2C bus showing the connection of multi-master and multi-slave configuration is shown in the following figure.

Fig 26.1 Multimaster Multislave Connection

Some conventions are followed in I 2C communication. Let us assume that there is one master and one slave and 8-data bits are
sent. We will initially assume that the master is the transmitter and the slave is the receiver. The clock is driven by the master. On
receiving 8-bits, an acknowledgement bit is driven by the receiver on SDA line. The acknowledgement bit is usually Low (0). The
following diagram shows the data communication pattern having 8 data bits and one acknowledgement bit.

Fig 26.2 Timing diagram for data transfer

The following features are to be noted -

1.

SDA line transmits/ receives data bits. MSB is sent first.

2.

Data in SDA line is stable during clock (SCL) high. A new bit is initiated at the negative clock transition after a specified hold
time.

3.

Serial clock (SCL) is driven by the master.

4.

An acknowledgement bit (0) is driven by the receiver after the end of reception. If the receiver does not acknowledge, SDA
line remains high (1).

I2C bus transfer consists of a number of byte transfers within a START condition and either another START condition or a STOP
condition. During the idle state when no data transfer is taking place, both SDA and SCL lines are released by all the devices and
remains high. When a master wants to initiate a data transfer, it pulls SDA low followed by SCL being pulled low. This is called
START condition. Similarly, when the processor wants to terminate the data transfer it first releases SCL (SCL becomes high) and
then SDA. This is called a STOP condition. START and STOP conditions are shown in the diagram as follows.

Fig 26.3 Timing diagram for START and STOP Conditions

START and STOP conditions are unique and they never happen within a data transfer.
Data Communication Protocol:
In I2C communication both 7-bit and 10-bit slave addressing are possible. In 7-bit addressing mode 128 slaves can be interfaced
with a single master. Similarly, in 10-bit addressing mode, 1024 slaves can be interfaced with the master. We will discuss here 7-bit
addressing mode only. 10-bit addressing mode is similar to 7-bit addressing except from the fact that the number of address bits is
more.
Following a 'start' condition, the master sends a 7-bit address of the slave on SDA line. The MSB is sent first. After sending 7-bit
address of the slave peripheral, a R/
(8th bit) bit is sent by the master. If R/
bit is '0', the following byte (after the
acknowledgement bit) is written by the master to the addressed slave peripheral. If R/ =1, the following byte (after the
acknowledgement bit) has to be read from the slave by the master.

After sending the 7-bit address of the slave, the master sends the address (usually 8 bit) of the internal register of the slave
wherefrom the data has to be read or written to. The subsequent access is automatically directed to the next address of the internal
register.

The following diagrams give the general format to write and read from several peripheral internal registers.

Fig 26.4 Data transfer protocol for writing to a slave device

R/
(Read / Write) bit indicates whether the data is to be written by the master or read by the master. If R/
is 1, the subsequent
data are to be read by the master. If R/
= 0, the subsequent data are to be written by the master to the addressed slave. It has to
be noted that the slave address is sent first, following a 'start' condition. The addressed slave responds by acknowledging and gets
ready for data transfer.
If data has to be read from a specific address of the slave device, the master sends the 7-bit address of the slave first following a
'start' condition. R/
bit is sent as 'low'. The addressed slave acknowledges by pulling the ACK line low. The master then sends the
8-bit internal address of the slave from which data has to be read. The slave acknowledges. Since R/
bit was initially 0, the
master is in the write mode. To change this to read mode, the 'start' condition is again generated followed by 7-bit address of the
slave with R/
= 1. The slave acknowledges. The slave then sends data from previously specified internal address to the master.
The master acknowledges by pulling ACK bit low. The data transfer stops when the master does not acknowledge the data
reception and a 'stop' condition is generated.

Software for I2 C Communication

The data transfer in I2C mode is not automatically controlled by hardware unlike UART. The Master has to be programmmed by
suitable software to generate 'Start' / 'Stop' conditions, various data bits from sending / receving , acknowledgement bit and clock
signal. Here, we will discuss some examples of I2C software.
Since SDA (RC4) and SCL (RC3) are both open drain pins, they can be configured either as an output or as an input. When a PIC
Processor is configured is I2C master, the SCL pin will function as open drain output while the SDA pin can be either an input or an
open drain output. Hence, the software I 2C will repeatedly access TRISC, the data direction register for PORT C. However, TRISC
is located in bank-1 at an address 87H, which cannot be accessed by direct addressing without changing RP0 bit to 1 as given in
the following instruction.
bsf STATUS, RP0
Then required bit of TRISC can be changed followed by clearing RP0 and reverting back to Bank-0.

bcf STATUS, RP0

Alternately, the indirect pointer FSR can have the address of TRISC and the required bit setting and bit clearing can be done
indirectly.

Consider the following definitions.

SCL
SDA equ 4

equ

The instruction bsf INDF, SDA will release the SDA line(as RC4/SDA pin is configured as an input, hence tristated), letting the
external pullup resister pull it high or some I 2C Slave device/Chip pull it low.

When FSR is used for indirect addressing, care should be taken to restore FSR value when subroutine is completed and the
program returns to the main line program.

I 2 C Subroutine

SDA
SCL equ 3

equ

The following subroutine DATA_OUT transfers out three bytes, i.e., ADDRDEV, ADDR8, and DATAWRTE

DATA_OUT:

call
START
movf
ADDRDEV,
W
call

;
;
Sends
TRBYTE

7-bit

Generate
peripheral

start
address
;

with

condition
R/
=0
Transmit

Parallel slave port (PSP)

PIC Microcontroller offers a mechanism by which an 8-bit parallel bidirectional data transfer can be achieved between a PIC
Microcontroller and a PC. PIC Microcontroller's Port-D and Port-E are used in this data transfer. For this data transfer, Port-D of PIC
Microcontroller is configured as a Parallel slave Port (PSP) by setting bit-4 of TRISE Register. The pins of Port-E function as control
pins
(
,
and
)
for
data
The connection diagram between PC and the PIC Microcontroller in PSP Mode is shown below.

Fig 28.1 Interfacing a PIC-microcontroller with a PC using Parallel Slave Port

Registers used for PSP Mode
ADCON1:
Three low significant bits (PCFG2-PCFG0) are set to enable Port-E pins for digital I/O

ADCON1, ADD: 9F H

TRISE:

transfer.

This register plays a crucial role in PSP configuration and control. The lower three bits control the data direction of PortE. the upper
four bits are used in conjunction with parallel slave port as shown here.

TRISE, ADD: 89 H

As explained, PSP Mode facilitates bidirectional 8-bit parallel data transfer. After ADCON1<b2-b0> and TRISE<b4, b2-b0> bits are
set by the user program, PORTD and PORTE are configured for PSP. When PC wants to write an 8-bit data to PIC, it addresses the
PIC microcontroller and the I/O address decoding circuit makes
go low selecting the PIC chip. PC also makes
(I/O write)
pin low and floats the data through its data bus (b7-b0). The data is written to PORTD and IBF flag in TRISE Register is set
indicating that a byte is waiting at PORTD input buffer to be read by the PIC. Simultaneously PSPIF flag bit of PIR1 register is set
and an interrupt is generated if PSPIE, PEIE and GIE bits have been set (i.e., the peripheral PSP interrupt is enabled.). After the
data is read from PORTD, IBF bit automatically becomes zero; however PSPIF bit has to be cleared by software. If a second byte is
written by the PC before the first byte is read, the second byte is lost and the IBOV flag in TRISE register is set indicating this loss.

Similarly a byte can also be read by the PC from the PIC microcontroller. When PIC writes a byte to PORTD, OBF flag is set
indicating that the byte is waiting to be read by the PC. When the PC reads this bytes, OBF flag in TRISE Register is automatically
cleared and the interrupt flag bit PSPIF is set indicating that the byte has been read by the PC from PIC microcontroller.