JPS63281524A - Data compressing arithmetic encoding device - Google Patents

Abstract

PURPOSE:To compress an information digit, to send a control digit and to save a transmitting time and a memory capacity by being equipped with a mixer to output an expanded digit from the same line, a P/S converter, an output breaker, a probability forecasting device, a generator, the same selector and an arithmetic encoder. CONSTITUTION:An information digit and a control digit are respectively inputted to terminals 101 and 102, the bit of the different value is added with a mixer 103 and an expanded digit is outputted from the same line. By a P/S converter 108, a bit string is obtained, encoded by an arithmetic encoder 109 and outputted in the sequence from a terminal 110. A breaker 104 identifies by the bit value added to the expanded digit and only when the expanded digit corresponds to the information digit, the information digit is supplied to a forecasting device 105. The forecasting device 105 calculates the appearance probability value of the bit of the information digit and supplies it to a selector 107 together with the output of a fixed probability generator 106. The selector 107, when the arithmetic encoder 109 encodes the bit corresponding to the information digit out of the expanded digit, selects the output of the forecasting device 105 and in other case, selects the output of the fixed probability generator 106. By the constitution, a transmitting time and a memory capacity can be saved.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention is a compression encoding device that removes redundancy contained in information and compresses it when transmitting or recording information, thereby saving transmission time and storage capacity. It is related to.

(Prior Art) A method of compressing redundant data and restoring original redundant data from compressed data that has been well known and used in the past is a method that uses a code called an arithmetic code. For details on arithmetic code data compressors and arithmetic code data decoders, see, for example, International Business Machines Corporation of the United States.
Machines Corporation) to 19
IBM Journal published in 1976.
of Research and Development (IBMJ)
Our own of Re5earch and De
Volume 20, No. 3, 198-203 of
Pages 135-149 of Vol. 28, No. 2 of the same magazine published in 1984, and Stanford University in the United States (
Stanford University) in 1976
Richard Clarke Pasco (Ric
The doctoral dissertation "Source Coding Algorithm for First Data Complexion" by Hard C1arkPasco
ing algorithm for fast
Data compression is detailed in the following section. In the following, an arithmetic code data compressor is simply referred to as an arithmetic encoder or an arithmetic coding device, and an arithmetic code data decoder is simply referred to as an arithmetic decoder or an arithmetic decoding device.

Of these methods, to briefly describe the method for compressing data, a signal sequence, that is, an information digit string x1s
x2+·,·,XN are code digit strings 'N1, W2, . =・town, for example, as follows, and the redundancy of the information digit string is removed.

First, let F be the value at the smaller end (ie, 0) of a predetermined interval on a number line (between 0 and less than 1), and T be the convergence of that interval (ie, 1). Next, follow step A
Execute I) to A5). In addition, in the following, z+-y is xG
: means to substitute the value of y.

It is also assumed that all operations are performed in the b-adic system.

AI) Set the value of i to 1.

A2) Input the i-th information digit as Xi.

A3) Appearance probability qi (xi
) and the cumulative appearance probability C1(xi)=Σy<xqi(y).

A4) F4-F〇, (xs)・TT+-qi(x
i) T , and truncate T to a predetermined significant figure.

A5) If i<N, increase the value of i by 1 and move on to A2).

If i=N, end.

Finally, from among the real numbers included in the interval determined by the final values of F and T, a real number with the least number of digits when expressed numerically is selected, and the representation depth of the selected real number is 0. Wl, W
2"...wl, the part below the decimal point is the sign digit"
Is "2"...Define as wL. Above procedure AI)
~A5), the length L of the code word is generally smaller than the length N of the information digit string, and it is shown in the above-mentioned document that data can be compressed.

On the other hand, to briefly describe how to restore data:
Code digit string Wl, W2. ...t"L is converted as follows, for example, and the original information digit string"
1>x2...XN is restored.

First, W is 0. wl, w2. −, substitute WL and S
Assign 1 to . Next, the following steps B1) to B5) are executed. Note that in the following, z+y means to substitute the value of y for X. It is also assumed that all operations are performed in the b-adic system.

Bl) Set the value of i to 1.

B2) Let xi be the largest digit among y that satisfies CiO')≦W/S.

B3) Output xi as restored information digits.

B4) W4-W-C1(xi)・S S””qi(Xi)・S and truncate S to a predetermined significant figure.

B5) If i<N, increase the value of i by 1 and move on to B2).

If i=N, the process ends.

If you follow the above steps Bl) to B5), the code digit string W
1. W2=Original information digit string xb from WL
The above-mentioned literature shows that 2''' A predictor with equal functionality is installed on the side to adaptively estimate the probability of occurrence of information digits and compress them efficiently.In order to improve the compression efficiency, the length of the information digits must be set to a sufficient length. Furthermore, although the case where information is generally encoded in units of digits has been described here, in actual encoding devices, encoding is often performed in units of binary digits, that is, bits.

Now, an arithmetic encoder and an arithmetic decoder for compressing data and restoring data as described above are described, for example, in US Pat. This can be realized with a circuit that includes arithmetic operation circuits such as addition and multiplication, as shown in the figure below.

(Problem to be Solved by the Invention) However, in the conventional method, the control digits cannot be sent while the information digit string is encoded and the coded digit string is sent out, so compression efficiency is reduced. If the length of the information digit string is made sufficiently long to improve the performance, there is a drawback that the period during which no control digits cannot be sent becomes longer.

However, depending on the application, it may be necessary to send control codes urgently even while encoding is being performed. For example, in data where text data and image data are mixed,
Text data and image data have different probability structures, and when the data changes, the method of calculating the probability value must also be changed accordingly. Therefore, a control digit to switch the calculation method is added to the predictor on the decoder side. I need to send it. Furthermore, in applications where the length of the information digit string is not known in advance, it is necessary to send a control digit during encoding to notify the decoder of the break in the information digit string.

The present invention aims to provide a data compression arithmetic encoding device that can send control digits even during encoding.

(Means for Solving the Problem) The present invention sequentially changes predetermined intervals on a number line using a predetermined method according to the input digits, and A data compression arithmetic coding device that outputs a numerical representation of a real number included in the interval obtained as a code bit string for an input digit string, and adds bits of different values to each of the information digits and control digits. a mixer that outputs the expanded digits obtained by the mixer from the same line, a parallel-to-serial converter that converts the digit string output from the mixer into a bit string, and a digit that corresponds to the information digit among the digits output from the mixer. a predictor that calculates the occurrence probability value of an information digit based on the output of the circuit breaker, a fixed probability generator that outputs a pre-fixed probability value, and a predictor output and fixed probability generator. , and an arithmetic encoder that performs arithmetic encoding on the output bit string of the parallel-to-serial converter according to the probability value output by the selector, thereby compressing information digits and simultaneously It is characterized by transmitting control digits.

(Function) The present invention basically allows control digits to be sent even during encoding as follows. First, bits of different values are added to the information digit and the control digit to form a new extended digit. That is, if a 0 is added to the information digit to form an extended digit, a 1 is added to the control digit to form the extended digit. Encoding is then performed on the expanded digits. In this way, even if the control digits are embedded in the information digit string and transmitted, the decoder can separate the information digits and control digits by checking the value of the added bits, so the original information digits and control digits can be separated. can be restored correctly.

Note that if the encoder and decoder sides are equipped with a predictor that adaptively estimates the probability of occurrence of information digits, if the prediction is simply made according to the expanded digit string, there will be errors during encoding. When the number of transmitted control digits increases, the internal state of the predictor is disturbed and the accuracy of prediction decreases. Therefore, in the present invention, if the expanded digit corresponds to the control digit, the supply to the predictor is cut off to ensure prediction accuracy.

However, if the extended digits are simply added with bits, the compression efficiency will decrease. For example, if the length of the information digit is 8 bits, the length of the expanded digit is 9 bits, which is 12.5% longer. In the present invention, deterioration in compression ratio is suppressed to a minimum in the following manner. In the following, for convenience of explanation, it is assumed that "θ" is added to the enlarged information symbol and "1" is added to the control code. Note that in reality, the length of the control digits is not necessarily equal to the length of the information digits, but it expands to the length of the information digits when it is shorter than the information digits, and into several when it is shorter than the information bits. It shall be sent in parts. Further, the accuracy of the probability value given by the predictor to the arithmetic code is assumed to be J bits. Then, the minimum value of the probability value is 2-J and the maximum value is 1-2-J. In the present invention, three fixed probabilities of 1/2, 2-J, and 1-2-J are generated, and when the arithmetic encoder encodes the bits to which the extended digit is added, "1'" and "0" are generated. The probability of `` appearing is 2-J, respectively.

1-2-J, and when encoding the bits other than the additional bits among the bits of the extended digit corresponding to the control digit, select 1/2 and 172 as the probabilities that "091" and "1" will appear, respectively. In other cases, the probability value output by the predictor is selected.If the increase in the length of the code bit string due to the addition of bits is calculated according to the above literature, the length of the code bit string per digit due to the bits added to the information digit is The increase in is -1og2 (
1-2-J) bits, and the increase in the code length per digit due to the bits added to the control digits is J bits.If the accuracy of the probability is chosen to be about J = 8, -1
og2(1-2-')=5.6X10-'', and the deterioration in compression ratio can be almost ignored. However, when J=8, the code bit string is 8 bits longer than the bits added to the control digit. However, since the control digits are not sent very often, the overall deterioration in compression efficiency due to the addition of bits is almost negligible.

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, information digits are input from input terminal 101, and control digits are input from input terminal 102, respectively. The input information digits and control digits are mixed in a mixer 103.
Bits of different values are added and output from the same line as enlarged digits. The expanded digit is converted into a bit string by a parallel-to-serial converter 108 and then encoded by an arithmetic encoder 109. The bit string obtained by encoding by the arithmetic encoder 109 is sequentially output from the output terminal 110. The magnified digits are also supplied to predictor 105 via circuit breaker 104 .

The circuit breaker 104 identifies whether the extended digit corresponds to either an information digit or a control digit based on the value of the bit added to the extended digit, and supplies the information digit to the predictor 105 only when the extended digit corresponds to an information digit. do. The predictor 105 calculates the appearance probability value of each bit of the next input information digit, and sends the probability value to the arithmetic encoder 109 via the selector 107.
supply to. It is not only the predictor 105 that supplies probability values to the arithmetic encoder 109 , but also the fixed probability generator 106 that supplies probability values via the selector 107 . Selector 1
07 selects the output of the predictor when the arithmetic encoder 109 encodes the bit corresponding to the information digit among the expanded digits, and selects the fixed probability generator otherwise. The method of selecting the fixed probability value has already been described.

(Example) FIG. 2 shows an example of the present invention. In the figure, blocks having the same functions as those in FIG. 1 are given the same numbers. In the figure, information digits and control digits each having a length of 8 bits are input from input terminals 201 and 203, respectively. The input information digit has the bit "θ'' supplied from terminal 205, and the control digit has the bit "θ'' supplied from terminal 205.
The bit “1” supplied from 06 is added to mixer 1.
The signals are respectively input to buffers 207 and 208 inside 03. Input terminals 202 and 204 each have a buffer 2.
A clock for inputting information digits and control digits is input to input terminal 202.2.
When a clock pulse is received at 04, the expanded information digits and control digits are input to buffers 207 and 208, respectively. Buffers 207 and 208 are FIFs in which the first input digit is output first.
It is an O type buffer. The buffers 207 and 208 supply not only the expanded digit but also a signal indicating whether or not data is held inside the buffer to the selector 209. Based on this signal, the selector 209 determines which of the buffers 207 and 208 the data is held. The output of the buffer being read out is read out, and the read expanded digit is set as the output of the selector 209. Note that when there is data in both buffers, the output of the buffer 207 is read out preferentially. The selector 209 outputs not only the selected expanded digit but also a clock pulse for holding the expanded digit, and these are output to the circuit breaker 1.
04 and the parallel/serial converter 108.

In the circuit breaker 104, an AND circuit 220 performs an AND operation between the additional bit of the expanded digit outputted from the selector 209 and a clock pulse for holding the expanded digit, and supplies the output to the input clock terminal of the predictor 105. This prevents the predictor 105 from retaining the digits when the expansion digits correspond to control digits.

The parallel-to-serial converter 108 holds the enlarged digit with the clock pulse supplied from the selector 209,
This is subjected to parallel-to-serial conversion and supplied to an arithmetic encoder 109. The parallel-to-serial converter 108 not only performs parallel-to-serial conversion, but also outputs clock pulses for holding output bits and positional information indicating the position of the enlarged digit of the output bit. The initial value of the position information is 0, and the added bit of the expanded digit is output first.

In the selector 107, a NOR circuit 230 performs a NOR operation on the 4-bit position information supplied from the parallel-to-serial converter 108, and the result is sent to the selector 2.
It is output to 28.229. When the output of the NOR circuit 230 is 1, that is, the bit output from the parallel-serial converter is an additional bit, the selectors 228 and 22
9 are the values 2- supplied from terminals 222 and 223, respectively.
J and 1-2-J (that is, 0.00000001 and 0.11111111 in 8-bit binary decimal notation are selected and supplied to the arithmetic encoder, and the output of the NOR circuit 230 is 0.
When , the outputs of the selectors 225 and 226 are selected and supplied to the arithmetic encoder. The output of the NOR circuit 230 is also supplied to the AND valve 227, and after being ANDed with the clock pulse supplied to the serial-parallel converter 108, the output is applied to the clock signal terminals of the flip-flops 2 and 24. It has been entered. flip 70 tube 224
The data input is an input bit to the serial-parallel converter 108, and when a clock pulse is input to the clock signal terminal, the data input is held and its value is output. Since the output of the NOR circuit 230 is 1 only when the serial-parallel converter 108 is outputting the additional bit, the flip 70 tube 224 holds the value of the additional bit. The output of the flip 70 knob 224 is sent to the selector 225.
226, and when the output of the flip-flop 224 is 0, the selectors 225 and 226 are connected to the terminal 221.
The value 0.5 (i.e. 0.10000000 in 8-bit binary decimal notation) supplied from The probability values are selected and supplied to selectors 228 and 229, respectively.

Selectors 225 and 228 operate on the probability of occurrence of 0, and selectors 226 and 229 operate on the probability of occurrence of 1.

(Effects of the Invention) As described above, according to the present invention, unlike conventional data arithmetic compression encoding devices, it is possible to easily construct a data compression arithmetic encoding device that can send control digits even during encoding. Moreover, as shown in this embodiment, since it can be configured with a simple circuit, it can be applied to high-speed data transmission systems and data storage devices.

Therefore, it is clear that the present invention can be effective in improving efficiency and performance in the future development of high-speed digital communication networks and the widespread use of mass storage devices.

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of the present invention, and FIG. 2 is a diagram showing an embodiment of the present invention. 101, 102... Output terminal, 103... Mixer 1
04... Breaker, 105... Predictor 106... Fixed probability generator, 107... Selector 108... Parallel-serial converter 109... Arithmetic encoder, 110... Output terminal 207
, 208...Buffer, 209...Selector 225
, 226.228.229...Selector 1st

Claims (1)

[Claims] Using a predetermined method according to the information digits that are input in sequence, predetermined intervals on the number line are sequentially changed, and the numerical representation of the real numbers included in the finally obtained interval is obtained. In a data compression arithmetic coding device that outputs a code bit string for an input information digit string, a mixed method that outputs expanded digits obtained by adding bits of different values to each of the information digits and control digits from the same line. a parallel-to-serial converter that converts the expanded digit string output from the mixer into a bit string, a circuit breaker that outputs only the expanded digits corresponding to the information digits among the expanded digits output from the mixer, and an output of the circuit breaker. a predictor that calculates the appearance probability value of an information digit by Data compression characterized in that information digits are compressed and control digits are transmitted at the same time by comprising an arithmetic encoder that performs arithmetic encoding on the output bit string of a parallel-to-serial converter according to a probability value to be output. Arithmetic encoder.