Category:x86 architecture

E

• X86 emulators (17 P)

I

• X86 instructions (53 P)

M

• X86 memory management (1 C, 27 P)
• X86 microarchitectures (72 P)
• X86 microprocessors (6 C, 14 P)

O

• X86 operating modes (7 P)
• X86 operating systems (9 C, 79 P)

X

• X86-based computers (23 C, 27 P)

• X86

*

• List of former IA-32 compatible processor manufacturers

0–9

• 3 GB barrier
• 3DNow!

A

• A20 line
• Advanced Programmable Interrupt Controller
• AES instruction set
• Appendix H

C

• Call gate (Intel)
• CLMUL instruction set
• Cool'n'Quiet
• CPU core voltage
• CPUID

D

• Direction flag
• DL Boost
• DOS API

F

• FLAGS register

G

• Global Descriptor Table

H

• Half-carry flag
• Hertzbleed
• High memory
• Hyper-threading

I

• IA-32
• ICOMP (index)
• Intel 5-level paging
• Intel Dynamic Acceleration
• Intel Turbo Boost
• Interrupt descriptor table
• IOPL

K

• Kernel page-table isolation

L

• List of CPU sockets
• List of Rockchip products
• List of x86 manufacturers
• Local Descriptor Table
• LogoFAIL

M

• Machine Check Architecture
• Model-specific register
• MultiProcessor Specification

N

• NX bit

P

• Page attribute table
• Page Size Extension
• PCI hole
• Pentium F00F bug
• Pentium FDIV bug
• Physical Address Extension
• Platform Environment Control Interface
• PowerNow!
• Privilege level
• PSE-36

R

• Ralf Brown's Interrupt List
• RDRAND

S

• Segment descriptor
• SHA instruction set
• Sinkclose
• SpeedStep

T

• Task state segment
• Test register
• Time Stamp Counter
• Trusted Execution Technology
• AMD Turbo Core

V

• VIA PadLock
• Virtual legacy wires

W

• Wintel

X

• X32 ABI
• X86 assembly language
• X86 calling conventions
• X86 virtualization
• X86-64
• X87