DATA MEMORY DEFINITION

CODE MEMORY DEFINITION

ENTRY
INSTRUCTIONS
TERMINATION
FUNCTION DEFINITION
END
Assembler directives
• Directives, or as they are sometimes called, pseudo-ops or
pseudo-instructions, are used by the assembler to translate
Assembly language programs into machine language.
• Unlike the microprocessor’s instructions, directives do not
generate any opcode; therefore, no memory locations are
occupied by directives in the final hex version of the
assembly program.
• Directives give directions to the assembler program to tell
it how to generate the machine code;
• Instructions are assembled into machine code to give
instructions to the CPU at execution time.
AREA directive
Format: AREA sectionname, attribute, attribute, …
• The AREA directive tells the assembler to define a new
section of memory.
• The memory can be code or data and can have
attributes such as ReadOnly, ReadWrite, and so on.
• This is widely used to define one or more blocks of
indivisible memory for code or data to be used by the
linker.
• Every assembly language program has at least one AREA.
• Sectionname in the directive is user defined name.
• The widely used attributes are CODE, DATA, READONLY, READWRITE,
COMMON, and ALIGN.
Code attribute
• It is an attribute given to an area of memory used for executable
machine instruction.
• Since it is used for code section of the program it is by default
READONLY memory.
• In ARM Assembly language we use this area to write our instructions.
DATA attribute
• It is an attribute given to an area of memory used for data and no
instruction (machine instructions) can be placed in this area.
• Since it is used for data section of the program it is by default a
READWRITE memory.
• In ARM Assembly language we use this area to set aside SRAM
memory for scratch pad and stack.
READWRITE attribute
• It is an attribute given to an area of memory which can be read from
and written to.
• Since it is READWRITE section of the program it is by default for DATA.
• In ARM Assembly language we use this area to set aside SRAM
memory for scratch pad and stack.
READONLY attribute
• It is an attribute given to an area of memory which can only be read
from.
• Since it is READONLY section of the program it is by default for CODE.
• In ARM Assembly language we use this area to write our instructions
for machine code execution.
• AREA MYCODE,CODE,READONLY
• MOV R1,#0X25
• …..
HERE B HERE
END
COMMON attribute
• It is an attribute given to an area of DATA memory section which can be used
commonly by several program codes.
• We do not initialize the COMMON section of the memory since it is used by
compiler exclusively.
• The compiler initializes the COMMON memory area with all zeros.
ALIGN attribute
• It is another attribute given to an area of memory to indicate how memory should
be allocated according to the addresses.
• When the ALIGN is used for CODE and READONLY it aligned in 4-bytes address
boundary by default since the ARM instructions are all 32-bit (4-bytes) word.
• The ALIGN attribute of AREA has a number after like ALIGN=3 which indicates the
information should be placed in memory with addresses of 23 , that is 0x50000,
0x50008, 0x50016, 0x50020, and so on.
• This ALIGN attribute of the AREA should not be confused with the ALIGN directive.
ENTRY directive
• The ENTRY directive shows the entry point of a program
to the assembler.
• Each program must have one entry point.
• But in keil it is optional
• Example
AREA PROG_C2, CODE, READONLY
ENTRY
…
END
END directive
• Every program must have an entry and an END point.
• The labels for the entry and end points must match.
• The END directive tells the assembler that it has
reached the end of source file.
• Example
AREA PROG_C2, CODE, READONLY
ENTRY
…
END
EQU (equate)
• This is used to define a constant value or a fixed
address.
• The EQU directive does not set aside storage for a data
item, but associates a constant number with a data or
an address label so that when the label appears in the
program, its constant will be substituted for the label.
• The following uses EQU for the counter constant, and
then the constant is used to load the R2 register:
COUNT EQU 0x25
… … ….
MOV R2, #COUNT ;R2 = 0x25
• When executing the above instruction “MOV R2,
#COUNT”, the register R2 will be loaded with the
value 0x25.
What is the advantage of using EQU?
• Assume that a constant (a fixed value) is used
throughout the program, and the programmer wants
to change its value everywhere.
• By the use of EQU, the programmer can change it
once and the assembler will change all of its
occurrences throughout the program.
• This allows the programmer to avoid searching the
entire program trying to find every occurrence.
RN (equate)
• This is used to define a name for a register.
• The RN directive does not set aside a seperate storage
for the name, but associates a register with that name.
• It improves the clarity.
• Example
VAL1 RN R1 ;define VAL1 as a name for R1
VAL2 RN R2 ;define VAL2 as a name for R2
SUM RN R3 ;define SUM as a name for R3
• AREA MYCODE,CODE,READONLY
• VAL1 RN R1
• VAL2 RN R2
• SUM RN R3
• MOV VAL1,#0X15 OR LDR VAL1,=0X12345678
• MOV VAL2,#0X15 OR LDR VAL2,=0X12345678
• ADD SUM,VAL1,VAL2
HERE B HERE
END
•
Assembler data allocation directives
• In most Assembly languages there are some directives to
allocate memory and initialize its value.
• In ARM Assembly language DCB, DCD, and DCW allocate
memory and initialize them.
• The SPACE directive allocates memory without initializing it.
DCB directive (define constant byte)
• The DCB directive allocates a byte size memory and
initializes the values.
• Example
MYVALUE DCB 56 ,67,84 ;MYVALUE = 5
A DCB 78, 89
MYMSAGE DCB “HELLO WORLD” ;string
DCW directive (define constant half-word)
• The DCW directive allocates a half-word size memory
and initializes the values.
• Example
MYDATA DCW 0x20, 0xF230, 5000, 0x9CD7
A DCW 0X25
DCD directive (define constant word)
• The DCD directive allocates a word size memory and
initializes the values.
• Example
MYDATA DCD 0x200000, 0xF30F5, 5000000,
0xFFFF9CD7
• Data definition directives and description
SPACE directive
• Using the SPACE directive we can allocate
memory for variables.
• Example
LONG_VAR SPACE 4 ; Allocate 4 bytes
OUR_ALFA SPACE 2 ; Allocate 2 bytes
Memory space allocation in the ARM
• The ARM has 4G bytes of directly accessible
memory space.
• This memory space has addresses 0 to 0xFFFFFFFF.
• The 4G bytes of memory space can be divided into
five sections. They are as follows:
1. On-chip peripheral and I/O registers
2. On-chip data SRAM
3. On-chip EEPROM
4. On-chip Flash ROM
5. Off-chip DRAM space
1. On-chip peripheral and I/O registers
• This area is dedicated to general purpose I/O (GPIO) and special
function registers (SFRs) of peripherals such as timers, serial
communication, ADC, and so on.
• ARM uses memory-mapped I/O, The function and address
location of each SFR is fixed by the chip vendor at the time of
design because it is used for port registers of peripherals.
• The number of locations set aside for GPIO registers and SFRs
depends on the pin numbers and peripheral functions supported
by that chip.
• That number can vary from chip to chip even among members
of the same family from the same vendor.
• Due to the fact that ARM does not define the type and number
of I/O peripherals one must not expect to have same address
locations for the peripheral registers among various vendors.
2. On-chip data SRAM:
• A RAM space ranging from a few kilobytes to several hundred
kilobytes is set aside mainly for data storage.
• The data RAM space is used for data variables and stack and is
accessed by the microcontroller instructions.
• The data RAM space is read/write memory used by the CPU
for storage of data variables, scratch pad, and stack.
• The ARM microcontrollers’ data SRAM size ranges from 2K
bytes to several thousand kilobytes depending on the chip.
• Even within the same family, the size of the data SRAM space
varies from chip to chip.
• A larger data SRAM size means more difficulties in managing
these RAM locations if you use Assembly language
programming.
• In today’s high-performance microcontroller, however, with over a
thousand bytes of data RAM, the job of managing them is handled
by the C compilers.
• Indeed, the C compilers are the very reason we need a large data
RAM since it makes it easier for C compilers to store parameters and
allows them to perform their jobs much faster.
• The amount and the location of the SRAM space vary from chip to
chip in the ARM chips.
• many of the ARM microcontrollers used in embedded products the
SRAM space is used for data; one can also buy or design an ARM-
based system in which the RAM space is used for both data and
program codes.
• This is what we see in the x86 PCs. In such systems normally one
connects the ARM CPU to external DRAM and the DRAM memory is
used for both code and data.
• Microsoft Windows 8 uses such a system for ARM-based Tablet
computers.
3. On-chip EEPROM
• A block of memory from 1K bytes to several
thousand bytes is set aside for EEPROM
memory.
• The amount and the location of the EEPROM
space vary from chip to chip in the ARM
microcontrollers.
• Although in some applications the EEPROM is
used for program code storage, it is used most
often for saving critical data.
• Not all ARM chips have on-chip EEPROM.
4. On-chip Flash ROM
• A block of memory from a few kilobytes to several
hundred kilobytes is set aside for program space.
• The program space is used for the program code.
In today’s ARM microcontroller chips, the code
ROM space is of Flash type memory.
• The amount and the location of the code ROM
space vary from chip to chip in the ARM products.
• The code ROM memory can also be used for
storage of static fixed data such as ASCII data
strings and look-up tables.
• ARM memory allocation
5. Off-chip DRAM space
• A DRAM memory ranging from few megabytes to
several hundred mega bytes can be implemented
for external memory connection.
• Although many of the ARM microcontrollers used in
embedded products use the on-chip SRAM for data,
one can also design an ARM-based system in which
the RAM is used for both data and program codes.
• This is what we see in the x86 PCs. In such systems
one connects the ARM CPU to external DRAM and
the DRAM memory is used for both code and data,
just like the x86 PCs.
• Many ARM vendorsare pushing the ARM11 chip for
the high-end of the market such as servers and
database computers.
• In an ARM11-based server computers, the external
(off-chip) DRAM is used and managed by the
operating system while on-chip Flash, EEPROM, and
SRAM memories are used for BIOS (basic input
output system), POST (power on self test), and CPU
scratch pad, respectively. In such cases the system is
not different from x86 computers currently in use,
except it uses ARM CPU instead of a Pentium chip
from Intel or x86 from AMD. The Microsoft Windows
8 uses ARM motherboard with off-chip DRAM
Data movement or transfer instructions
• Move data between registers and memory
• The data items can be a 8-bit byte, 16-bit half-word
or 32 bit word.
• Addresses must be word or 32-bit word and must
be boundary aligned. (e.g. 4’s multiple for LDR/STR)
• Three basic forms are
– Single register load/store
– Multiple register load/store
– Single register swap: SWP(B),atomic instruction for
semaphore
Single register load/store
• General Syntax
LDR instruction
Syntax LDR Rd,[Rx]
• load Rd with the contents of location pointed ;to by Rx
register. Rx is an address between ;0x00000000 to 0xFFFFFFFF
• The LDR instruction tells the CPU to load (bring in) one word
(32-bit or 4 bytes) from a base address pointed to by Rx into
the GPR.
• After this instruction is executed, the Rd will have the same
value as four consecutive locations in the memory.
• Obviously since each memory location can hold only one byte
(ARM is a byte addressable CPU), and our GPR is 32-bit, the
LDR will bring in 4 bytes of data from 4 consecutive memory
locations.
• The locations can be in the SRAM or a Flash memory.
• Example,
LDR R2,[R5]
• This instruction will copy the contents of memory
locations pointed to by R5 into register R2.
• Since the R2 register is 32-bit wide, it expects a 32-
bit operand in the range of 0x00000000 to
0xFFFFFFFF.
• That means the R5 register gives the base address of
the memory in which it holds the data.
• Therefore if R5=0x80000, the CPU will fetch into
register R2, the contents of memory locations
0x80000, 0x80001,0x80002, and 0x80003.
• Example 2
LDR R7,[R5]
• Assume R5 = 0x40000200
• It load R7 with the contents of locations
0x40000200-0x40000203
STR instruction
• Syntax
STR Rx,[Rd]
• It store register Rx into locations pointed to by Rd
• The STR instruction tells the CPU to store (copy) the
contents of the GPR to a base address location pointed to
by the Rd register.
• Notice that the source register of STR instruction is
placed before the destination register.
• Obviously since GPR is 32-bit wide (4-byte) we need four
consecutive memory locations to store the contents of
GPR.
• The memory locations must be writable such as SRAM.
• Example
STR R3,[R6]
• This instruction will copy the contents of R3 into locations
pointed to by R6.
• Locations 0x40000200 through 0x40000203 of the SRAM
memory will have the contents of R3 since R6 = 0x40000200.
• LDRB instruction
Syntax LDRB Rd, [Rx]
• It load Rd with the contents of the location,
pointed to by Rx register.
• The LDRB instruction tells the CPU to load (copy)
one byte from an address pointed to by Rx into
the lower byte of Rd.
• After this instruction is executed, the lowerbyte
of Rd will have the same value as memory
location pointed to by Rx.
• It must be noted that the unused portion (the
upper 24 bits) of the Rd register will be all zeros
• Example
LDRB R7,[R5]
• STRB instruction
Syntax STRB Rx, [Rd]
• It store the byte in register Rx into, location
pointed to by Rd.
• The STRB instruction tells the CPU to store
(copy) the byte value in Rx to an address
location pointed to by the Rd register.
• After this instruction is executed, the memory
locations pointed to by the Rd will have the
same byte as the lower byte of the Rx
• Example
STRB R1,[R5]
• LDRH instruction
Syntax LDRH Rd, [Rx]
• It load Rd with the half-word pointed to by Rx register
• The LDRH instruction tells the CPU to load (copy) half-
word (16-bit or 2 bytes) from a base address pointed
to by Rx into the lower 16-bits of Rd Register.
• After this instruction is executed, the lower 16-bit of
Rd will have the same value as two consecutive
locations in the memory pointed to by base address of
Rx.
• It must be noted that the unused portion (the upper
16 bits) of the Rd register will be all zeros,
• Example
LDRH R7,[R5]
• STRH Instruction
Syntax STRH Rx, [Rd]
• It store half-word (2-byte) in register Rx , into locations pointed
to by Rd
• The STRH instruction tells the CPU to store (copy) the lower 16-
bit contents of the Rx to an address location pointed to by the
Rd register.
• After this instruction is executed, the memory locations pointed
to by the Rd will have the same value as the lower 16-bit of Rx
Register.
• The locations are part of the data read/write memory space
such as on-chip SRAM.
• Example,
– STRH R3,[R6]
• instruction will copy the 16-bit lower contents of R3
into two consecutive locations pointed to by base
register R6.
• Unsigned Data Range in ARM and associated
Load Instructions
• Unsigned Data Range in ARM and associated
Store Instructions
• LDR, LDRH, LDRB for 32, 16, 8 bits
• STR, STRH, STRB for 32, 16, 8 bits
Examples
• LDR R0, [R1] ; R0= 32 bit data pointed by the
@ R0 := mem32[R1]
• STR R0, [R1] @ mem32[R1] := R0
• AREA MYCODE,CODE,READONLY
• LDR R1,=0X40000400
• LDR R2,=0X40000800
• LDRB R3,[ R1 ]
• STRB R3,[R2]
• ADD R1,R1,#1
• ADD R2,R2,#1
• LDRB R3,[ R1 ]
• STRB R3,[R2]
• Area mycode,code,readonly
• Ldr r0,=A
• Ldrb r1,[ro]

Here b here
A dcb 0x25
end
Addressing modes
• The CPU can access operands (data) in various
ways, called addressing modes.
• The number of addressing modes is determined
when the microprocessor is designed and
cannot be changed.
• Some of the simple ARM addressing modes are
– Register
– Immediate
– Memory addressing
• register indirect (indexed addressing mode)
Register addressing mode
• The register addressing mode involves the use of
registers to hold the data to be manipulated.
• Memory is not accessed when this addressing
mode is executed; therefore, it is relatively fast.
• Examples
MOV R6,R2 ;copy the contents of R2 into R6
ADD R1,R1,R3 ;add the contents of R3 to
contents of R1
SUB R7,R7,R2 ;subtract R2 from R7
Immediate addressing mode
• In the immediate addressing mode, the source
operand is a constant.
• In immediate addressing mode, as the name implies,
when the instruction is assembled, the operand
comes immediately after the opcode. For this reason,
this addressing mode executes quickly.
• Examples
MOV R9,#0x25 ;move 0x25 into R9
MOV R3,#62 ;load the decimal value 62 into R3
ADD R6,R6,#0x40 ; add 0x40 to R6
Memory addressing mode
• In the first two addressing modes, the operands
are either inside the microprocessor or tagged
along with the instruction.
• In most programs, the data to be processed is
often in some memory location outside the
CPU. There are many ways of accessing the data
in the data memory space.
• The ARM supports Register indirect or indexed
addressing mode
Register Indirect Addressing Mode (Indexed
addressing mode)
• Register indirect addressing means that the location
of an operand is held in a register.
• It is also called indexed addressing or base
addressing.
• Example
STR R5,[R6] ;move R5 into the memory location
;pointed to by R6
LDR R10,[R3] ;move into R10 the contents of the
;memory location pointed to by R3.
Register Indirect Addressing with an Offset
• ARM supports a memory-addressing mode
where the effective address of an operand is
computed by adding the content of a register
and a literal offset coded into load/store
instruction.
• This offset can be specified in one of three
ways
– Immediate
– Register
– Scaled register
Immediate offset
• The offset is an unsigned integer that is stored as part of
the instruction.
• It can be added to or subtracted from the value in the
base register.
• If a label is used to specify the address, the assembler uses
the pc as the base register and computes the appropriate
offset.
• If no offset is specified an immediate constant value of
zero is assumed.
• Example
LDR R0, [R1] ; Zero offset
LDR R0, [R1, #4] ; R1=R1+4 offset with value 4
Register offset
• The offset is an unsigned integer that is in a
register other than the pc.
• It can be added to or subtracted from the value in
the base register.
• Example
LDR R1,=0x40000000
MOV R2,#0x4
LDR R0, [R1, R2] ;R1=R1+R2=0x40000004
Scaled Register Offset
• The offset is an unsigned integer that is in a
register other than the pc.
• It is shifted by an immediate amount before it
is added to or subtracted from the value in the
base register.
• Example
LDR R0, [R1, R2, LSL #2]
• These addressing modes can affect the offset
value in the base register in three different
ways
– Pre-index addressing (LDR R0, [R1, #4]!)
• Pre-index with write back
• calculation before accessing with a write back
– Auto-indexing addressing (LDR R0, [R1, #4])
• Without a write back
– Post-index addressing (LDR R0, [R1], #4)
• Calculation after accessing with a write back
Pre-index addressing
• The offset is combined with the value in the
base register, and the base register is updated
with this new address before being used to
access memory.
– Immediate Pre-indexed
• Ex: LDR R0, [R1, #4]!
– Register Pre-indexed
• Ex: LDR R0, [R1, R2]!
– Scaled Register Pre-indexed
• Ex: LDR R0, [R1, R2, LSL #2]!
Auto-indexing addressing
– Immediate Pre-indexed
• Ex: LDR R0, [R1, #4]
– Register Pre-indexed
• Ex: LDR R0, [R1, R2]
– Scaled Register Pre-indexed
• Ex: LDR R0, [R1, R2, LSL #2]
Post-Index Addressing
– Immediate Post-indexed
• LDR R0, [R1], #4
– Register Post-indexed
• LDR R0, [R1], R2
– Scaled Register Post-indexed
• LDR R0, [R1], R2, LSL #2