Be Project Final Presentation
Be Project Final Presentation
Team Members
Kishan S. (1RN08EC040) Nikhil M. (1R08EC057) Nishant K. (1RN08EC059) Nitesh Kumar (1RN08EC060)
Objective
To design a CMOS camera system in a nano-satellite for remote sensing applications. Intermediate Goals: To select an appropriate CMOS image sensor for small satellite application. To interface the camera sensor to the on-board microcontroller. To control the camera using the snapshot signal generated by the microcontroller. To store the captured image in the FRAM chip for further operations by the other subsystems. To design an integrated flight-model camera module.
Introduction
Small Satellites
a.
Image Sensors
a. b. c.
d.
Implementation methodology
Prototype Model: Initial implementation on discrete components: AVR32 evaluation board (EVK1100), the KAC-9618 Headboard, and the Ramtron FM22L16 FRAM chip. Final implementation on integrated Payload PCB: Embedded AVR32 chip, Ramtron FM22L16. Provision for interface to KAC-9618 headboard. Flight Model: Long term plans include design of space-qualified system using the Aptina MT9M032 sensor and LPC1769 controller board. Design of lens system for optimum satellite imagery.
Sensor Comparison
Sensor Parameter Aptina MT9M032 Kodak KAC9618
Array Size 1472H x 1096V 648H x 504V
Pixel Size
2.2 m x 2.2 m
7.5 m x 7.5 m
Chroma
Monochrome
Monochrome
Ground Resolution
30.8 m
93 m
Swath
45.34 km x 33.76 km
60.26 km x 46.87 km
Power Consumption
364.6 mW
168 mW
Shutter
Global
Rolling
Dynamic Range
70.1 dB
62 dB
2.30 MB
0.301 MB
Operating Temperature
-30 to +70 C
-40 to 85 C
Requirements
Hardware:
o o o o o o
Kodak KAC-9618 image sensor (640x480) AVR32 microcontroller board Ramtron FRAM FM22L16 (512 KB) TTL-RS232 logic level converter Edmund Optics NT56-531 (Focal Length: 50 mm) JTAG Debugger - AVR JTAGICE mkII
Software:
Kodak KAC-9618
Number of Pixels: 640 x 480 pixels i.e. 0.3 Mega Pixels Data rate: Flexible according to MCLK and internal divider Dynamic Range: 62dB in linear mode, 110dB in non linear mode Temperature Range: -40 C to +85C Power Consumption: 160 mW active and 1.68 mW standby
Memory
Non Volatile Memory: FM22L16 parallel memory with 8/16 data lines and 19/18 address lines by Ramtron Inc. Important Features: 512 kB of non volatile memory enough to store one image and telemetry FRAM technology is radiation resistant FRAM ICs consume lesser power than EEPROMs Data can be written at a maximum rate of 9 MBps. FRAM memory is less prone to data corruption FRAM memory is reliable even at higher temperatures
Hardware Implementation
Flowchart
Algorithm
Define a value img_mode as 0 or 1 for the two different modes of image capture. 0 => 664 x 504 and 1 => 332 x 252. Define a look up table of the address of the registers to be configured in the image sensor and their configuration values. The image sensor is configured as follows: {Register address, Register value} {0x03,0x80 for img_mode 0 or 0xB0 for img_mode 1} Monochrome Sensor {0x05,0x1F} Hclk=Mclk/31 {0x06,0x80} 8-bit data o/p {0x07,0xE0} Pclk in data ready mode, Vsync and Hsync in pulse mode {0x09,0x61} Snap enable, one frame readout {0x2B, 0x00} Offset value {0x00,0x01} Update settings Unmask only the necessary modules like FLASHC, PBA bridge, PBB bridge, GPIO, INTC, PM, TC and HSB matrix.
Algorithm (continued)
Configure the power manager for the main clock as the PLL output of 64 MHz. Configure the Generic clock to give an output of 64/3 i.e. 21.33 MHz to be connected to the MCLK of the image sensor. Configure the timer 0 to overflow every 10 us and enable the timer overflow interrupt. This is for the function delay 10us. Enable all the GPIOs required for the payload. Reset the image sensor by giving an active low pulse of about 10us. Unmask the clock to the TWI module Configure the TWI master to send the data at SCLK of 400 KHz. Configure the required image sensors register through I2C using the look up table defined by sending the data and waiting for acknowledgement. Check for the PwrUpBusy bit in the image sensor by reading the register Main Configuration0 with the address 0x02 and wait for it to clear. Mask the clock to the TWI module.
Algorithm (continued)
Unmask the USART2 module, enable its pins and configure it for a
baud rate 115200 bps in a normal UART mode with one stop bit. Call a delay of 4.1s, because during this time the image sensors output was active and was not responding to snapshot signal. Unmask and configure the external bus interface header files for the parallel memory and initialize the parameters. Write the first four bytes with the values of image_width and image _height as a part of the protocol to identify the type of image. Give a snap signal to the image sensor i.e. is a high pulse of about 10 us (Min = 2 x MCLK). Set the data pins of the EBI in open drain mode (high impedence).
Algorithm (continued)
Till VSYNC is low On the falling edge of the the pclk send the CE, WE and address to the FRAM from starting address specified to store the data from the image sensor in the memory. After every falling edge of PCLK increment the FRAM address. Put the image sensor in reset state. Enable the data pins of the EBI. From the starting address read from the memory and send it through UART to the computer. This is done till (image_width) x (image_height) amount of data is read and sent. Mask the USART2, EBI and SMC module.
Results
Data was received serially
through COM port, and stored as a binary file. The size of the binary file matched the theoretical size of the image. The KODAK SNAPS Tool was used to reconstruct the image from the binary data. The resulting image was found to be severely affected by noise.
Results Discussion
Challenges faced
Corruption of data retrieved from the FRAM. Testing the KAC-9618 sensor proved to be difficult, because the sensor evaluation kit was found to be faulty. Delay in procurement process of shortlisted sensor. Coordination with different subsystem members across multiple colleges, to obtain parameters such as available power, data rate, etc. Lack of documentation and support for the Kodak sensor.
Future work
Reviewing the program code to address possible errors. Testing the setup with a new FRAM board. Interfacing the camera with an integrated PCB comprising of the AVR32 microcontroller and the FM22L16 memory chip. Writing a batch file to receive data serially from the COM port and dump it into a binary file.
References
"Project STUDSAT-1: Payload Design Document" - Chetan Angadi, Zohra Aziz Ali Manjiyani 32-bit AVR UC3 Microcontrollers Application Note, Atmel Corporation EVK1100 Hardware Reference Manual, Atmel Corporation AVR32bit Microcontroller data sheet - AT32UC3A0512 FM22L16 datasheet, Ramtron Corporation "Using and Programming the I2C BUS" - Keil Support Small satellites open opportunities in communication, remote sensing Dr. T. K. Alex Development of Camera Electronics for a Pico-Satellite Payload - Prithvi Raj Narendra, Kushal V. Kodak KAC-9618 CMOS Image Sensor Device Performance Specification The AVR Microcontroller and Embedded Systems- Muhammed Ali Mazidi, Sarmad Naimi, Sepehr Naimi