MM54HC195/MM74HC195 4-Bit Parallel Shift Register

November 1995

MM54HC195/MM74HC195
4-Bit Parallel Shift Register
General Description
The MM54HC195/MM74HC195 is a high speed 4-bit SHIFT trol input is high. Serial data for this mode is entered at the
REGISTER utilizes advanced silicon-gate CMOS technolo- J-K inputs. These inputs allow the first stage to perform as a
gy to achieve the low power consumption and high noise J-K or TOGGLE flip flop as shown in the truth table.
immunity of standard CMOS integrated circuits, along with The 54HC/74HC logic family is functionally as well as pin-
the ability to drive 10 LS-TTL loads at LS type speeds. out compatible with the standard 54LS/74LS logic family.
This shift register features parallel inputs, parallel outputs, J- All inputs are protected from damage due to static dis-
K serial inputs, SHIFT/LOAD control input, and a direct charge by internal diode clamps to VCC and ground.
overriding CLEAR. This shift register can operate in two
modes: PARALLEL LOAD; SHIFT from QA towards QD. Features
Parallel loading is accomplished by applying the four bits of Y Typical operating frequency: 45 MHz
data, and taking the SHIFT/LOAD control input low. The Y Typical propagation delay: 16 ns (clock to Q)
data is loaded into the associated flip flops and appears at Y Wide operating supply voltage range: 2 – 6V
the outputs after the positive transition of the clock input. Y Low input current: 1 mA maximum
During parallel loading, serial data flow is inhibited. Serial Y Low quiescent current: 80 mA maximum (74HC Series)
shifting occurs synchronously when the SHIFT/LOAD con-
Y Fanout of 10 LS-TTL loads

Connection Diagram
Dual-In-Line Package

TL/F/5324 – 1
Top View

Order Number MM54HC195 or MM74HC195

Function Table
H e high level (steady state)
Inputs Outputs L e low level (steady state)
Serial Parallel X e irrelevant (any input, including transitions)
Clear Shift/ Clock QA QB QC QD QD u e transition from low to high level
Load J K A B C D
a, b, c, d e the level of steady-state input at inputs A, B, C,
L X X X X X X X X L L L L H or D, respectively.
H L u X X a b c d a b c d d QA0, QB0, QC0, QD0 e the level of QA, QB, QC, or QD,
H H L X X X X X X QA0 QB0 QC0 QD0 QD0 respectively, before the indicated steady-state input condi-
H H u L H X X X X QA0 QA0 QBn QCn QCn tions were established.
H H u L L X X X X L QAn QBn QCn QCn QAn, QBn, QCn e the level of QA, QB, QC, respectively,
H H u H H X X X X H QAn QBn QCn QCn before the most-recent transition of the clock.
H H u H L X X X X QAn QAn QBn QCn QCn

C1995 National Semiconductor Corporation TL/F/5324 RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions
If Military/Aerospace specified devices are required, Min Max Units
please contact the National Semiconductor Sales Supply Voltage (VCC) 2 6 V
Office/Distributors for availability and specifications. DC Input or Output Voltage 0 VCC V
Supply Voltage (VCC) b 0.5 to a 7.0V (VIN, VOUT)
DC Input Voltage (VIN) b 1.5 to VCC a 1.5V Operating Temp. Range (TA)
DC Output Voltage (VOUT) b 0.5 to VCC a 0.5V MM74HC b 40 a 85 §C
MM54HC b 55 a 125 §C
Clamp Diode Current (IIK, IOK) g 20 mA
Input Rise or Fall Times
DC Output Current, per pin (IOUT) g 25 mA
(tr, tf) VCC e 2.0V 1000 ns
DC VCC or GND Current, per pin (ICC) g 50 mA VCC e 4.5V 500 ns
Storage Temperature Range (TSTG) b 65§ C to a 150§ C VCC e 6.0V 400 ns
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temp. (TL) (Soldering 10 seconds) 260§ C

DC Electrical Characteristics (Note 4)

74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
VIH Minimum High Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
VIL Maximum Low Level 2.0V 0.5 0.5 0.5 V
Input Voltage** 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
VOH Minimum High Level VIN e VIH or VIL
Output Voltage lIOUTl s20 mA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
VIN e VIH or VIL
lIOUTl s4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
lIOUTl s5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VOL Maximum Low Level VIN e VIH or VIL
Output Voltage lIOUTl s20 mA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
VIN e VIH or VIL
lIOUTl s4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
lIOUTl s5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
IIN Maximum Input VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA
Current
ICC Maximum Quiescent VIN e VCC or GND 6.0V 8.0 80 160 mA
Supply Current IOUT e 0 mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,
ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.

2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Symbol Parameter Conditions Typ Guaranteed Limit Units
fMAX Maximum Operating Frequency 45 30 MHz
tPHL, tPLH Maximum Propagation Delay, Clock to Q 14 24 ns
tPHL Maximum Propagation Delay, Reset to Q 16 25 ns
tREM Minimum Removal Time, Shift/Load to Clock 0 ns
tREM Minimum Removal Time, Reset Inactive to Clock 5 ns
tS Minimum Setup Time, (A, B, C, D, J, K to Clock) 20 ns
tS Minimum Setup Time, Shift/Load to Clock 20 ns
tW Minimum Pulse Width Clock or Reset 16 ns
tH Minimum Hold Time, any Input except Shift/Load 0 ns

AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)

74HC 54HC
TA e 25§ C
Symbol Parameter Conditions VCC TA eb40 to 85§ C TA eb55 to 125§ C Units
Typ Guaranteed Limits
fMAX Maximum Operating 2.0V 10 6 5 4 MHz
Frequency 4.5V 45 30 24 20 MHz
6.0V 50 35 28 24 MHz
tPHL Maximum Propagation 2.0V 70 150 189 224 ns
Delay, Reset to Q or Q 4.5V 15 30 38 45 ns
6.0V 12 26 32 38 ns
tPHL, tPLH Maximum Propagation 2.0V 70 145 183 216 ns
Delay, Clock to Q or Q 4.5V 15 29 37 43 ns
6.0V 12 25 31 37 ns
tTHL, tTLH Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
6.0V 7 13 16 19 ns
tREM Minimum Removal Time, 2.0V b2 0 0 0 ns
Shift Load to Clock 4.5V b2 0 0 0 ns
6.0V b2 0 0 0 ns
tREM Minimum Removal Time, 2.0V 5 5 5 ns
Reset Inactive to Clock 4.5V 5 5 5 ns
6.0V 5 5 5 ns
tS Minimum Setup Time, 2.0V 100 125 150 ns
(A, B, C, D, J, K to Clock) 4.5V 20 25 30 ns
6.0V 17 21 25 ns
tS Minimum Setup Time, 2.0V 100 125 150 ns
Shift/Load to Clock 4.5V 20 25 30 ns
6.0V 17 21 25 ns
tH Minimum Hold Time 2.0V b 10 0 0 0 ns
any Input except Shift/Load 4.5V b2 0 0 0 ns
6.0V b2 0 0 0 ns
tW Minimum Pulse Width, 2.0V 30 80 100 120 ns
Clock or Reset 4.5V 10 16 20 24 ns
6.0V 9 14 18 20 ns
tr, tf Maximum Input Rise 2.0V 1000 1000 1000 ns
and Fall Time 4.5V 500 500 500 ns
6.0V 400 400 400 ns
CPD Power Dissipation 100 pF
Capacitance (Note 5)
CIN Maximum Input Capacitance 5 10 10 10 pF

Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.

3
Logic and Timing Diagrams

TL/F/5324 – 2

TL/F/5324 – 3

4
Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number MM54HC195J or MM74HC195J
NS Package Number J16A

5
MM54HC195/MM74HC195 4-Bit Parallel Shift Register
Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number MM74HC195N
NS Package N16E

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