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Week 5 Assignment 5 with solution final

The document contains an assignment on VLSI Physical Design with Timing Analysis, featuring multiple-choice questions and answers related to circuit blocks, floorplanning, simulated annealing, and design constraints. Key concepts include the characteristics of hard and soft circuit blocks, slicing floorplans, and the implications of simulated annealing in optimization. The document also discusses the correct identification of various design elements and their relationships within the context of VLSI design.

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2 views

Week 5 Assignment 5 with solution final

The document contains an assignment on VLSI Physical Design with Timing Analysis, featuring multiple-choice questions and answers related to circuit blocks, floorplanning, simulated annealing, and design constraints. Key concepts include the characteristics of hard and soft circuit blocks, slicing floorplans, and the implications of simulated annealing in optimization. The document also discusses the correct identification of various design elements and their relationships within the context of VLSI design.

Uploaded by

rishiKumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI Physical Design with Timing Analysis

Assignment – 5
Ques.1:Which of the following is/are correct?
a. Hard circuit blocks have fixed area and dimension.
b. Soft circuit blocks have fixed area but adjustable aspect ratio.
c. Floorplanning divides the design into individual circuit module.
d. In floorplanning we determine appropriate shape for each block.
Ans: (a,b,d) Refer lecture notes.

Ques.2:Which of following is/are slicing floorplan?


a.

b.

c.
d.

Ans (a,d)

Option b and c contains “wheels” which cannot be created by silicing the floorplan. So these
are not slicing floorplans.
Ques3.Which of the following is the polish expression of the floorplan given below

a. AB+CDEF*++*
b. AB*CDEF++**
c. AB+CDEF+++*
d. AB+CDEF*+++

Ans: (a)

V * H +
Ques4. Consider the following floorplan

Which of the following is the slicing tree of given floorplan


a.

b.

c.
d.

Ans: (a)

Ques.5: Which of the following is/are correct for simulated annealing?


a. Simulated annealing algorithm is stochastic by nature two runs basically yield two
different results.
b. Simulated annealing algorithm like a higher cost solution and emulates physical
annealing to produced lower cost solution.
c. If temperature is high, the probability of accepting a solution state is high.
d. If temperature is low, probability of accepting a solution state is low.

Ans: (a, b, c, d) Refer lecture notes.


Ques.6: Consider the following data. starting block a, and six nets N1-N6: N1 = (a,b), N2 =
(a,d), N3 = (a,c,e), N4 = (b,d), N5 = (c,d,e), and N6 = (d,e)

In iteration 0, we have set block 'a' as the first block in the ordering. Which of the following
table is correct for iteration:2?

a.

Iteration Block New Terminating Gain Continuing


nets nets Nets

2 c N5 -- -1 N3

d N5, N6 N2, N4 0 --

e N5, N6 -- -2 N3

b.

Iteration Block New Terminating Gain Continuing


nets nets Nets

2 c N5 -- -1 N3

d N5 N2,N4 0 --

e N5,N6 -- -2 N3
c.

Iteration Block New Terminating Gain Continuing


nets nets Nets

2 c N3 -- -1 N3

d N5,N6 N2,N4 -1 --

e N5,N6 -- -2 N3

d.

Iteration Block New Terminating Gain Continuing


nets nets Nets

2 c N5 -- -1 N3

d N5,N6 N2,N4 0 --

e N5,N6 -- -1 N3
Ans: (a)

Iteration # Block New nets Terminating nets Gain Continuing nets

0 a N1,N2,N3 -- -3 --

1 b N4 N1 0 --
c N5 -- -1 N3
d N4.N5,N6 N2 -2 --
e N5,N6 -- -2 N3

2 c N5 -- -1 N3
d N5,N6 N2,N4 0 --
e N5,N6 -- -2 N3

3 c -- -- 0 N3,N5
e -- N6 1 N3,N5

4 c -- N3,N5 2 --

Ques.7: Which of the following are correct?


a. Two pins are functionally equivalent if swapping them does not affect design logic.
b. Simulation annealing aims to improve an objective function by exploring the solution
space.
c. Greedy algorithm always accepts improving solution which can lead to local
optimum.
d. Two pins are said to be electrically equivalent if we can swap the pin without
affection the logic of design.
Ans: (a,b,c) Refer lecture notes.
Ques.8: Which of the following is/are correct?
a. Chip planning does not determine the layout of power ground distribution network.
b. Chip planning determines the placement of supply I/O pads.
c. Trunks connects rings to each other or to top level power ring.
d. Concentric circle pin assignment can enable pin assignment for external pins
located behind other blocks or obstacles.
Ans: (b,c) Refer lecture notes.

Ques 9.Which of the following is vertical constraints graph of given floorplan

a.

b.
c.

d.

Ans: c

Step 1: Create the nodes A-E for blocks A-E


Step 2: Create the source node s and sink node t.
Step 3: Add a directed edge (vi , vj ) if mi is below mj
Step 4: Remove all transitive (redundant) edges.

10. Three blocks, a and b, and their size options are given.

Which of the following is/are the possible corner points in the horizontal composition of the
final floorplan?

a. (4,7)
b. (5,5)
c. (7,4)
d. (9,3)
Ans:(b,c,d)

The possible corner points in overall shape function is (5, 5), (7, 4) and (9, 3).

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