PFS7523-7529/7533-7539

HiperPFS-3 Family
PFC Controller with Integrated High-Voltage MOSFET and Qspeed
Diode Optimized for High PF and Efficiency Across Load Range

Key Benefits
D K
+
• High efficiency and power factor across load range
• >95% efficiency from 10% load to full load PG VCC
• <60 mW no-load consumption at 230 VAC VCC
• PF >0.92 easily achievable at 20% load
FB
• EN61000-3-2 Class C and D compliant CONTROL

• Highly integrated for smallest boost PFC form factor C

DC
AC OUT
• Integrated controller, MOSFET and ultra-low reverse recovery loss IN HiperPFS-3 PGT

diode (Qspeed)
• Packaging optimized for high volume production S V G REF

• Eliminates insulating pad/heat-spreader

• Enhanced features
• Programmable Power Good (PG) signal
• User selectable power limit: Enables different HiperPFS-3 family PI-7224-061615
members to be tested in the same design for optimum device Figure 1. Typical Application Schematic.
selection
• Integrated non-linear amplifier for fast output OV and UV
protection and transient response Output Power Table
• Digital line peak detection that provides robust performance even
Universal Input Devices
with distorted input voltage from UPS or generators
• Digital power factor enhancer compensates for EMI filter and Maximum Continuous
bridge distortion, providing high-line PF >0.92 @ 20% load Peak Output Power
Product Output Power Rating at
• Frequency adjusted over line voltage and each line cycle (Full Power Mode)
90 VAC (Full Power Mode)
• Spread-spectrum across >60 kHz window simplifies EMI filtering
requirements PFS7523L/H 110 W 120 W
• Lower boost inductance PFS7524L/H 130 W 150 W
• Provides up to 450 W peak output power for universal PFS7525L/H 185 W 205 W
applications, 1 kW for high-line only applications
• Protection features include: UVLO, UV, OV, OTP, brown-in/out, PFS7526H 230 W 260 W
cycle-by-cycle current limit and power limiting for overload PFS7527H 290 W 320 W
protection PFS7528H 350 W 385 W
• Halogen free and RoHS compliant
PFS7529H 405 W 450 W
Applications High-Line Only Input Devices
• E-bike and EV 2-Wheeler • 80 Plus™ Platinum
chargers designs Maximum Continuous
Peak Output Power
• Power tool chargers • High-power adaptors Product Output Power Rating at
(Full Power Mode)
• PC • High-power LED lighting 180 VAC (Full Power Mode)
• Printer • Industrial and appliance
PFS7533H 255 W 280 W
• LCD TV • Generic PFC converter
• Video game consoles PFS7534H 315 W 350 W
PFS7535H 435 W 480 W
PFS7536H 550 W 610 W
PFS7537H 675 W 750 W
PFS7538H 810 W 900 W
PFS7539L/H 900 W 1000 W
Table 1. Output Power Table (See Table 2 on page 11 for Maximum Continuous
Output Power Ratings.)

eSIP-16D (H Package) eSIP-16G (L Package)

Figure 2. Package Options.

www.power.com July 2024

This Product is Covered by Patents and/or Pending Patent Applications.

PFS7523-7529/7533-7539

Description HiperPFS-3’s advanced power packaging technology and high

efficiency simplify the complexity of mounting the IC and thermal
The HiperPFS -3 devices incorporate a continuous conduction mode
™
management, while providing very high power capabilities in a single
(CCM) boost PFC controller, gate driver, ultra-low reverse recovery compact package; these devices are suitable for PFC applications
(Qspeed™) diode and high-voltage power MOSFET in a single, from 75 W to 900 W.
low-profile (GROUND pin connected) power package. HiperPFS-3
devices eliminate the PFC converter’s need for external current sense Product Highlights
resistors and the associated power loss, and use an innovative control Protected Power Factor Correction Solution
technique that adjusts the switching frequency over output load, • Incorporates high-voltage power MOSFET, ultra-low reverse
input line voltage, and even input line cycle. recovery loss Qspeed diode, controller and gate driver.
• EN61000-3-2 Class C and Class D compliance.
This control technique maximizes efficiency over the entire load range • Integrated protection features reduce external component count.
of the converter, particularly at light loads. Additionally, it significant- • Accurate built-in brown-in/out protection.
ly minimizes the EMI filtering requirements due to its wide bandwidth • Accurate built-in undervoltage (UV) protection.
spread spectrum effect. The HiperPFS-3 uses advanced digital • Accurate built-in overvoltage (OV) protection.
techniques for line monitoring functions, line feed-forward scaling, and • Hysteretic thermal shutdown (OTP).
power factor enhancement, while using analog techniques for the • Internal power limiting function for overload protection.
core controller in order to maintain extremely low no-load power • Cycle-by-cycle power switch current limit.
consumption. The HiperPFS-3 also features an integrated non-linear • Internal non-linear error amplifier for enhanced load transient
error amplifier for enhanced load transient response, a user program- response.
mable Power Good (PG) signal as well as user selectable power limit • No external current sense resistor required.
functionality. HiperPFS-3 includes Power Integrations’ standard set of • Provides ‘lossless’ internal sensing via sense-FET.
comprehensive protection features, such as integrated UV, OV, • Reduces component count and system losses.
brown-in/out, and hysteretic thermal shutdown. HiperPFS-3 also • Minimizes high current gate drive loop area.
provides cycle-by-cycle current limit and Safe Operating Area (SOA) • Minimizes output overshoot and stresses during start-up
protection of the power MOSFET, power limiting of the output for • Integrated power limit.
overload protection, and pin-to-pin short-circuit protection. • Improved dynamic response.
• Digitally controlled input line feed-forward gain adjustment for
HiperPFS-3’s innovative variable frequency continuous conduction flattened loop gain across entire input voltage range.
mode operation (VF-CCM) minimizes switching losses by maintaining • Eliminates up to 40 discrete components for higher reliability and
a low average switching frequency, while modulating the switching lower cost.
frequency in order to suppress EMI, the traditional challenge with Solution for High Efficiency, Low EMI and High PF
continuous conduction mode solutions. Systems using HiperPFS-3 • Continuous conduction mode PFC uses novel constant amp-second
typically reduce the total X and Y capacitance requirements of the [on-time] volt-second [off-time] control engine.
converter, the inductance of both the boost choke and EMI noise • High efficiency across load.
suppression chokes, thereby reducing overall system size and cost. • High power factor across load.
Additionally, HiperPFS-3 devices dramatically reduce component count • Low cost EMI filter.
and board footprint while simplifying system design and enhancing • Frequency sliding technique for light load efficiency improvements.
reliability, when compared with designs that use discrete MOSFETs • >95% efficiency from 10% load to full load achievable at
and controllers. The innovative variable frequency, continuous nominal input voltages.
conduction mode controller enables the HiperPFS-3 to realize all of • Variable switching frequency to simplify EMI filter design.
the benefits of continuous conduction mode operation while leverag- • Varies over line input voltage to maximize efficiency and
ing low-cost, small, simple EMI filters. minimize EMI filter requirements.
Many regions mandate high power factor for many electronic • Varies with input line cycle voltage by >60 kHz to maximize
products with high power requirements. These rules are combined spread spectrum effect.
with numerous application-specific standards that require high power Advanced Package for High Power Applications
supply efficiency across the entire load range, from full load to as low • Up to 450 W [universal], 1 kW [high-line only] peak output power
as 10% load. High efficiency at light load is a challenge for traditional capability in a highly compact package.
PFC solutions in which fixed MOSFET switching frequencies cause • Simple adhesive or clip mounting to heat sink.
fixed switching losses on each cycle, even at light loads. In addition • No insulation pad required and can be directly connected to heat
to featuring relatively flat efficiency across the load range, HiperPFS-3 sink.
also enables high power factor of >0.92 at 20% load. HiperPFS-3 • Staggered pin arrangement for simple routing of board traces and
simplifies compliance with new and emerging energy-efficiency high-voltage creepage requirements.
standards over a broad market space in applications such as PCs, LCD • Single package solution for PFC converter reduces assembly costs
TVs, notebooks, appliances, pumps, motors, fans, printers and LED and layout size.
lighting.

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PFS7523-7529/7533-7539

Pin Functional Description After start-up, the output voltage threshold at which the PG signal
becomes high-impedance depends on the threshold programmed by
BIAS POWER (VCC) Pin: the POWER GOOD THRESHOLD pin resistor. When not in use, the
This is a 10.2-15 VDC [operating, 12 V typical] bias supply used to POWER GOOD pin is left unconnected.
power the IC. The bias voltage must be externally clamped to
prevent the BIAS POWER pin from exceeding 15 VDC to ensure POWER GOOD THRESHOLD (PGT) Pin:
long-term reliability. This pin is used to program the output voltage threshold at which the
PG signal becomes high-impedance representing the PFC stage falling
REFERENCE (REF) Pin: out of regulation. The low threshold for the PG signal is programmed
This pin is connected to an external bypass capacitor and is used to with a resistor between the POWER GOOD THRESHOLD and SIGNAL
program the IC for either FULL or EFFICIENCY power mode. The GROUND pins. Tying POWER GOOD THRESHOLD to the REFERENCE
external capacitor is connected between the REFERENCE and SIGNAL pin disables the power good function (i.e. POWER GOOD pin remains
GROUND [G] pins. Note: the return trace to G must not be shared with high impedance).
other return traces with a potential for large return currents during
surge events. The REFERENCE pin has two valid capacitor values to SOURCE (S) Pins:
select ‘Full’ (1.0 µF ±20%) and ‘Efficiency’ (0.1 µF ±20%) power These pins are the source connection of the power switch as well as
modes. the negative bulk capacitor terminal connection.

SIGNAL GROUND (G) Pin:

Discrete components used in the feedback circuit, including loop
compensation, decoupling capacitors for the BIAS POWER (VCC), H Package (eSIP-16D)
REFERENCE (REF) and VOLTAGE MONITOR (V) must be referenced to (Front View)
the SIGNAL GROUND (G) pin. The SIGNAL GROUND pin is also
connected to the tab of the device. The SIGNAL GROUND pin should
Pin 1 I.D.
not be tied directly to the SOURCE pin external to the IC.

VOLTAGE MONITOR (V) Pin:

The VOLTAGE MONITOR pin is tied to the rectified high-voltage DC
rail through a 100:1, 1% high-impedance resistor divider to minimize
power dissipation and standby power consumption. The recommend-
1 3 4 5 6 7 8 91011 1314 16
ed resistance value is between 8 MΩ and 16 MΩ. Modifying this

VCC
REF
G
V
C
FB
PG
PGT
S
S
D
NC
K
divider ratio affects peak power limit, brown-in/out thresholds and
will degrade input current quality (reduce power factor and increase
THD). A small ceramic capacitor forming an 80 µs nominal time- Exposed Metal (Both H and L
constant is required from the VOLTAGE MONITOR pin to the SIGNAL Packages) (On Package Edge)
Internally Connected to G Pin
GROUND pin to bypass any switching noise present on the rectified
DC bus.
Exposed Pad (Backside)
This pin also features brown-in/out detection thresholds and Internally Connected to
G GROUND (G) Pin G
incorporates a weak current source into the IC in order to act as a
pull-down in the event of an open circuit condition.
H Package
COMPENSATION (C) Pin: (eSIP-16D)
This pin is used for loop pole/zero compensation of the OTA error (Back View)
amplifier via the connection of a network of capacitors and a resistor
between the COMPENSATION pin and SIGNAL GROUND pin. The
COMPENSATION pin connects internally to the output of the OTA error
amplifier and the input to the on-time and off-time controllers.
16 1413 1110 9 8 7 6 5 4 3 1
FEEDBACK (FB) Pin:
K

S
PGT
PG
C
V
NC
D
S

FB

G
REF
VCC

This pin is connected to the main voltage regulation feedback resistor

divider network and is also used for fast over and undervoltage
protection. This pin also detects the presence of the feedback L Package (eSIP-16G)
voltage divider network at start-up and during operation. The divider (Front View)
ratio should be the same as the VOLTAGE MONITOR pin for proper and
optimized power limit and power factor. A large upper resistor
Pin 1 I.D.
between 8 MW and 16 MΩ ±1% is recommended. A small ceramic
capacitor between FEEDBACK and SIGNAL GROUND, forming a nominal Exposed Pad
80 µs time-constant with the bottom resistor, is required. (Backside)
1 4 6 8 10 13 16 Not Shown
POWER GOOD (PG) Pin:
VCC

PG

Use of the PG function is optional. The POWER GOOD pin is an 3 5 7 9 11 14

active low, open-drain connection which sinks current when the
REF

FB

PGT

NC

output voltage is in regulation. At start-up, once the FEEDBACK pin PI-7225-061615

voltage has risen to ~95% of the internal reference voltage, the

Figure 3. Pin Configuration.
POWER GOOD pin is asserted low.

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PFS7523-7529/7533-7539

DRAIN (D) BOOST DIODE CATHODE (K) BIAS POWER (VCC) VOLTAGE MONITOR (V)

INPUT LINE INTERFACE

VV PEAK PF
ADC DETECTOR ENHANCER
12 V GATE DRIVER +
REF SERIES/SHUNT BROWN-IN/ LOW/HIGH
REGULATOR - UVLO OUT DETECT LINE DETECT

Integrated Qspeed BO, BI HL/LL MON(PFE)

Ultrafast Diode
VBRST FBREF VPG(H) FBUV FBOFF FBOV IOCP
Off-Time Controller
MOFF × (VFB - VV) VCC
REFERENCE
~(VO-VIN) - IPGT (REF)
CINT REFERENCE
+ AND BAND GAP

PON

VOFF is a function of the error-voltage

(VE) and is used to reduce
FEEDBACK Pin the average operating frequency Feedback OV
OV/UV/OFF - FBOV
as a function of output power
senseFET VCC Latch +
Power -
Frequency
SUPERVISOR

MOSFET VOFF Slide

HL/LL
+

VOFF
TIMER

VE Non-Linear OTA
VE
+ FBREF
+
ISNS LEB - FEEDBACK
OTA
(FB)
-
OCP +
+ Feedback UV Buffer and
IOCP - POWER LIMIT
SOA RAMP - De-Glitch
-
+ FBUV Filter
+
HL/LL
- VBRST Feedback OFF
-
On-Time Controller + FBOFF

CINT PON × MON(PFE) × ISNS

MON(PFE) is the switch VFB REF
VPG(H) POWER GOOD
current sense scale + THRESHOLD
factor which is a function IPGT
of the peak input voltage (PGT)
-

START-UP,
FMEA CHECKS POWER GOOD
(PG)

SOURCE (S) SIGNAL GROUND (G) COMPENSATION (C)

PI-7226-062215

Figure 4. Functional Block Diagram.

DRAIN (D) Pin: Since the volt-seconds during the on-time must equal the volt-sec-
This is the drain connection of the internal power switch. onds during the off-time, to maintain flux equilibrium in the PFC
choke, the on-time (tON) is controlled such that:
BOOST DIODE CATHODE (K) Pin:
This is the cathode connection of the internal Qspeed Diode.
V IN # t ON = K 1 (2)
Functional Description The controller also sets a constant value of charge during each
on-cycle of the power MOSFET. The charge per cycle is varied
The HiperPFS-3 is a variable switching frequency boost PFC solution. gradually over many switching cycles in response to load changes so
More specifically, it employs a constant amp-second on-time and it can be regarded as substantially constant for a half line cycle. With
constant volt-second off-time control algorithm. This algorithm is this constant charge (or amp-second) control, the following relation-
used to regulate the output voltage and shape the input current to ship is therefore also true:
comply with regulatory harmonic current limits (high power factor).
Integrating the switch current and controlling it to have a constant I IN # t ON = K 2
(3)
amp-sec product over the on-time of the switch allows the average Substituting tON from (2) into (3) gives:
input current to follow the input voltage. Integrating the difference
between the output and input voltage maintains a constant volt- I IN = V IN # 2 K
(4)
second balance dictated by the electro-magnetic properties of the K1

boost inductor and thus regulates the output voltage and power. The relationship of (4) demonstrates that by controlling a constant
More specifically, the control technique sets constant volt-seconds for amp-second on-time and constant volt-second off-time, the input
the off-time (tOFF). The off-time is controlled such that: current IIN is proportional to the input voltage VIN, therefore providing
^ V O - V IN h # t OFF = K 1 (1) the fundamental requirement of power factor correction.

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PFS7523-7529/7533-7539

This control produces a continuous mode power switch current The line-sense feed-forward gain is also important in providing a
waveform that varies both in frequency and peak current value across switch power limit over the input line range.
a line half-cycle to produce an input current proportional to the input
This characteristic is optimized to maintain a relatively constant
voltage.
internal error-voltage level at full load from an input line of 90 to
Control Engine 230 VAC.
The controller features a low bandwidth, high gain OTA error-amplifi-
Beyond the specified peak power rating of the device, the internal
er of which its non-inverting terminal is connected to an internal
power limit feature will regulate the output voltage below the set
voltage reference of 3.85 V. The inverting terminal of the error-am-
regulation threshold as a function of output overload to maintain a
plifier is available on the external FEEDBACK pin which connects to
constant output power. Figure 6 illustrates the typical regulation
the output voltage divider network with a divider ratio of 1:100 to
characteristic as a function of load.
regulate the output voltage to 385 V nominally. The FEEDBACK pin
connects directly to the divider network for fast transient load Below the brown-in threshold (VBR+) the power limit is reduced when
response. the device is operated in the ‘Full’ power mode as shown in Figure 7.
As the input line voltage is reduced toward the brown-out threshold
The internally sensed FET switch current is scaled by the input
(VBR-) and if the load exceeds the power limit derating, the boost
voltage peak detector current sense gain (MON) then integrated and
output voltage will drop out of regulation in accordance with Figure 6.
compared with the error-amplifier signal (VE) to determine the cycle
on-time. Internally the difference between the input and output The rated peak power shown in Table 1 is not derated for voltages
voltage is derived and the resultant is scaled, integrated, and below the brown-in threshold when the device is operated in the
compared to a voltage reference (VOFF) to determine the cycle ‘Efficiency’ mode.
off-time. Careful selection of the internal scaling factors produces
input current waveforms with very low distortion and high power Start-Up with Pin-to-Pin Short-Circuit Protection
factor. At start-up, the engine performs a sequence of operational checks
and pin short/open evaluations, as illustrated in Figure 8, prior to the
Line Feed-Forward Scaling Factor (MON) and PF Enhancer commencement of switching. When the input voltage peak is above
The VOLTAGE MONITOR (V) pin voltage is sampled and converted by brown-in, the engine enables switching.
a Δ-Σ ADC to a quantized digital value. A digital line cycle peak detec-
tor, with dynamic time constants and multi-cycle filtering, derives and The OTA error amplifier provides a non-linear amplifier (NLA)
smooths the peak of the input line voltage. This peak is used mechanism to overcome the inherently slow feedback loop response
internally to scale the gain of the current sense signal through the when the sensed output voltage on the FEEDBACK pin is outside its
MON variable. This contribution is required to reduce the dynamic regulation window. This allows the error amplifier function to limit
range of the control feedback signal as well as flatten the loop gain the maximum overshoot and undershoot during load transient events.
over the operating input line range. The line-sense feed-forward gain To reduce switch and output diode current stress at start-up, the
adjustment is proportional to the square of the peak rectified AC line HiperPFS-3 calculates off-time based upon output voltage (VOUT) during
voltage and is adjusted as a function of the VOLTAGE MONITOR pin start-up, resulting in a relatively soft controlled start-up.
voltage.
Once the applied VCC is above the VCCUVLO+ threshold, and the output
At high-line and light load, the feed-forward MON variable is dynami- of the on-chip VREF regulator is above REFUV+, the value of the
cally adjusted throughout the line cycle in order to compensate for REFERENCE pin capacitor is detected and the full or efficiency power
the line current distortion through the EMI filter and full bridge mode is latched. The pin open/short tests are performed, and if the
network, thereby improving power factor. FEEDBACK pin voltage is valid the over-temperature OTP is checked
to be false. Once the preceding checks are satisfied the input voltage
PI-5335-061615

is monitored via the VOLTAGE MONITOR pin until it exceeds the VBR+
VE threshold [but the peak detector is not saturated]. It is at this point
that switching is enabled.
IS dt
Latch Timing Supervisor and Operating Frequency Range
RESET
VOFF Since the controller is expected to operate with a variable switching
frequency over the line frequency half-cycle, typically spanning a
(VOUT-VIN)dt
Latch range of 22 – 123 kHz when operating in CCM, the controller also
SET features a timing supervisor function which monitors and limits the
maximum switch on-time and off-time as well as ensures a minimum
Gate
Drive (Q) cycle on-time. Figure 9(a) shows the typical half-line frequency
profile of the device switching frequency as a function of input
Maximum
ON-time voltage at peak load conditions. Figure 9(b) shows for a given line
Minimum Timing condition of 115 VAC, the effect of EcoSmart™ on the switching
OFF-time Supervisor
frequency as a function of load. The switching frequency is not a
function of boost choke inductance in CCM (continuous conduction
mode) operation.
Figure 5. Idealized Converter Waveforms.

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PFS7523-7529/7533-7539

1.2 1.2
Normalized to Set Output Voltage

Normalized Minimum Power Limit

PI-7227-061615

PI-7544-061615
1.0 1.0
Regulation Threshold

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2

0.0 0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 PFS7523-29 70 75 80 85 90 95 100
PFS7533-39 160 170 180 190
Normalized to Peak Output Power Rating Input Voltage (VAC)
Figure 6. Typical Normalized Output Voltage Characteristics as Function of Figure 7. Normalized Minimum Power Limit as Function of Input Voltage.
Normalized Peak Load Rating.

Start

Apply Current to
VCC > UVLO+ C Pin for 65 µs
NO and
REF > REFUV+?

YES
YES (C > 2.5 V) or
Feedback < FBOFF

NO Reference
Capacitor Valid?
NO

Remove Current
YES Source on
C Pin, Short C to G

Capacitor Reset:
Short C to G
for 230 µs

YES
OTP Fault

NO
Feedback > FBOFF
NO

YES
NO Peak Valid and
Peak > VBR+
Remove Short
on C Pin

YES

Remove C to G
Short, Start
Switching

PI-7249-061615

Figure 8. Start-Up Flow Chart.

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EcoSmart switching in bursts in order to maintain regulation when leakage

The HiperPFS-3 includes an EcoSmart function wherein the internal currents constitute the majority of the load. Higher output voltage
error signal (VE) is used to detect the converter output power. Since ripple at light load is an artifact of efficient burst mode operation.
the internal error-signal is related to the output power, this signal
Power Good Signal (PG)
level is used to set the average switching frequency as a function of
The HiperPFS-3 features a ‘power good’ (PG) circuit which comprises
output power.
an internal comparator that turns ‘on’ an open-drain switch during
As shown in Figure 10, the off-time integrator control reference (VOFF) start-up when the sensed output voltage on the FEEDBACK pin rises
is controlled with respect to the internal error-voltage level (output to ~95% (VPG+) of the set output voltage threshold. During start-up,
power) to allow the converter to maintain output voltage regulation prior to the output voltage reaching VPG+, the PG signal is in a
and relatively flat conversion efficiency from 20% to 100% of rated high-impedance state (internal switch is in ‘off’ state).
load, which is essential to meet many efficiency directives. The
The power good signal transitions from ‘on’ to ‘off’ state when the
degree of frequency slide is also controlled as a function of input line
sensed output voltage on the FEEDBACK pin falls to a user selected
voltage. The lower VOFF slope as a function of input voltage reduces
threshold, programmed with a resistor on the POWER GOOD
the average frequency extremes for high input line operation.
THRESHOLD (PGT) pin. The POWER GOOD THRESHOLD pin sources a
Burst-Mode for No-Load Power Consumption Reduction fixed current IPGT. This current combined with the power good thresh-
Under no-load conditions the HiperPFS-3 engine is architected to old resistor sets the threshold when the power good signal transitions
enter a burst mode which gates the power switch on and off between from the ‘on’ state to the high-impedance ‘off’ state as the PFC
fixed error voltage levels. This ensures low power consumption by output falls out of regulation.

130 135 VAC

PI-7231-061615
230 VAC
120 1.12

PI-8231-011217
110 1.10
100
1.08
to Room Temperature
Frequency (kHz)

90 180 VAC 90 VAC

1.06
IOCP Normalized
80
70 1.04
60
115 VAC 1.02
50
40 1.00
30
0.98
20
10
Peak Load 0.96
0 0.94
0 45 90 135 180
0.92
Line Conduction Angle (°) 0.90
Figure 9. -40 over
(a) Frequency Variation over Line Half-Cycle as a Function of Input Voltage (b) Frequency Variation -20 Line0Half-Cycle
20 as40a Function
60 of80Load.100
120
Note: Frequency Profiles Shown were Analytically Derived and Reflect CCM Operation Across the Entire Line Cycle.
Temperature (˚C)

VA VA
VOFF(MAX)

VIN < 140 VAC

VOFF

VB VIN > 170 VAC VB

4.0 V
(Full Power)
4 V 5.2 V 140 VAC 170 VAC
VE VIN
PI-7228-061615

Figure 10. EcoSmart Frequency Slide VOFF vs. VE and VOFF(MAX) vs. Input Voltage.

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The power good comparator has an internal 81 µs de-glitch filter Selectable Power Limit
(tPGD) to prevent noise events from falsely triggering the programmed The capacitor on the REFERENCE pin allows user selection between
VPG- threshold. ’full’ and ‘efficiency’ power limit for each device. The ‘efficiency’
power mode will permit user selection of a larger device for a given
In the event a load fault prevents the boost from achieving regulation
output power requirement for increased conversion efficiency.
(above ~95% of the set output voltage threshold) the PG function will
remain in the high-impedance state and will not indicate when an In ‘full’ power mode the REFERENCE pin capacitor is 1.0 µF ±20%
output voltage has fallen below the user programmed VPG- threshold. and the ‘efficiency’ power limit mode is selected with a 0.1 µF ±20%
The VPG- user programmed threshold is enabled once the VPG+ capacitor.
threshold has been reached.
If the REFERENCE pin is accidentally shorted to ground, the IC will
If the POWER GOOD THRESHOLD programming pin is tied to disable switching and remain disabled until all conditions for the
REFERENCE pin, the power good function is disabled and PG remains start-up sequence are satisfied.
in the high-impedance (‘off’) state. This is the preferred configuration
when PG is not in use. If the POWER GOOD THRESHOLD pin is shorted If the REFERENCE pin is open-circuit, the absence of a bypass
to the SIGNAL GROUND pin, the PG signal will transition to the ‘on’ capacitor will prevent start-up. During operation, an open-circuit may
state at VPG+ and remain low (‘on’) until the PFC output voltage has result in enough REFERENCE pin noise to result in a VREF REFUV- shut-
fallen below the VFB_UV threshold for greater than tFB_UV seconds. down.

Similar to the disable condition described above, if the value of the Protection Modes
PGT resistor is such that the VPG- threshold is greater than the VPG+ Brown-In Protection (VBR+)
threshold, the PG signal will latch off and remain in the high-imped- The VOLTAGE MONITOR pin features an input line under-voltage
ance off-state. detection to limit the minimum start-up voltage. This detection
The Power Good function is not valid under the following conditions: threshold will inhibit the device from starting at input AC voltages
below brown-in and above input peak voltages of 400 VPK.
A. VCC or VREF are not in a valid range of operation. VCC below
UVLO- or VREF below REFUV- the power good function is not valid Brown-Out Protection (VBR-)
with the POWER GOOD pin in a high-impedance state. The VOLTAGE MONITOR pin features a brown-out protection mode
B. Power Good will go to high-impedance state when a soft- shut- wherein the HiperPFS-3 will turn-off when the VOLTAGE MONITOR
down is initiated by an over-temperature fault to provide early pin voltage is below the line undervoltage threshold (VBR-) for a period
indication to secondary circuits of an OT fault. exceeding tBRWN_OUT (brown-out debounce period). In the event a
C. PGT is outside the valid programming range of between 225 V and single half-line cycle is missing (normal operating line frequency is
360 V. PGT voltages above this range, including PGT floating, will 47 Hz to 63 Hz) the brown-out detection will not be initiated. Once
prevent PG from transitioning to active pull-down. PGT voltages brown-out has been triggered, the HiperPFS-3 soft-shutdown
below this range result in PG deassertion at the output undervolt- gradually reduces the internal error-voltage to zero volts over a period
age (VFB_UV) threshold. of 1 ms to ramp the power MOSFET on-time to zero. The onset of
D. Once the start-up sequence check has passed and the converter this soft-shutdown is aligned to the next line cycle zero crossing to
goes into start-up, if PGT is opened, then the PG signal will minimize reactive component di/dt transients and allow time for the
remain latched in the high-impedance state until the controller is energy stored within the boost choke as well as the input EMI filter to
reset. dissipate. This helps minimize voltage transients after the bridge
rectifier, which helps to prevent false restarts. The device will

Set internally
100% VOUT (385 V) by VPG+
95% VOUT (365 V)
Output Voltage
Rising

Set externally
by RPGT
87.5% VOUT (337 V)
R PG = 0.875 # 3.85 = 3.37 V = 337 kX
I PG 10 nA
Output Voltage
tPGD Falling
tPGD

PG = High Impedance PG = On-State PG = High Impedance

tPG
PI-7229-061615

Figure 11. Power Good Function Description.

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perform an auto-restart, including FMEA pin fault checks and other

start-up qualifications prior to checking for the line voltage being
IOCP(LL)
above the brown-in voltage by virtue of the VOLTAGE MONITOR pin
being above VBR+.

IOCP
After a brown-in event, until after the tSTARTUP timer has expired, the line
voltage brown-out threshold is reduced to VBR-NTC and the brown-out
timer is extended to tBRWN_OUT_NTC to allow for the detected drop in line IOCP(HL)
voltage due to an in-rush limiting negative temperature coefficient
(NTC) thermistor in series with the input line.

If the tBRWN_OUT_NTC debounce timer is triggered by the sensed line

voltage dropping below the VBR-NTC threshold but the line voltage VIN
recovers to above the VBR-NTC threshold before the tBRWN_OUT_NTC expires,
~140 VAC ~170 VAC
then the tSTARTUP timer will be re-started. If the line does not recover
above the VBR-NTC threshold before the tBRWN_OUT_NTC debounce timer PI-7255-061615
expires a shutdown will occur.
Figure 12. Line Dependent OCP.
After the tSTARTUP timer has expired, if the VOLTAGE MONITOR pin
voltage is qualified above VBR-NTC, the brown-out debounce timer will below the low-line threshold VHIGH-. In the event of a line drop-out,
switch to normal period (tBRWN_OUT) and the brown-out threshold will the controller may revert from high-line to low-line parameters if the
switch to VBR-. If the VOLTAGE MONITOR pin voltage is not qualified drop-out exceeds 37 ms (nominal). High-line only input parts use a
above VBR- after the subsequent tBRWN_OUT timer has expired then a single fixed OCP threshold.
brown-out shutdown will occur. A follower-mode feature updates the controller to high-line status
HiperPFS-3 incorporates input waveform discrimination to determine rapidly, as soon as the input voltage exceeds VHIGH+. This feature has
if the line signal peak-to-average ratio is more representative of a particular benefit for high-line hard-start conditions after a long AC
sinewave or a high duty cycle square wave. The brown-out threshold line drop-out where the peak detector may initially indicate a low
is reduced to VBR_SQ when a high duty cycle (UPS) square wave is input line condition.
detected. A leading edge blanking circuit inhibits the current limit comparator
VCC Undervoltage Protection (UVLO) for a short time (tLEB) after the power MOSFET is turned on. This
The BIAS POWER (VCC) pin has an undervoltage lock-out protection leading edge blanking time is set so that switch current spikes caused
which inhibits the IC from starting unless the applied VCC voltage is by drain capacitance and rectifier reverse recovery time will not cause
above the VCCUVLO+ threshold. The IC initiates a start-up once the premature termination of the MOSFET conduction period.
BIAS POWER pin voltage exceeds the VCCUVLO+ threshold. After Safe Operating Area (SOA) Mode
start-up the IC will continue to operate until the BIAS POWER pin Since the cycle-by-cycle OCP mechanism described above does not
voltage has fallen below the VCCUVLO- level. The absolute maximum prevent the possibility of inductor current ‘stair-casing’, an SOA mode
voltage of the BIAS POWER pin is 17.5 V which must be externally is also featured. Rapid build-up of the switch current can occur in the
limited to prevent long term damage to the IC. event of inductor saturation or when the input and output voltage
Line Dependent Over Current Protection (OCP) limit differential is small combined with too little inductor reset time.
The device includes a cycle-by-cycle over-current protection mech- The SOA mode is triggered whenever the switch current reaches
anism which protects the device in the event of a fault. The intent of current limit (IOCP) and the on-time is less than tSOA. The SOA mode
OCP protection in this device is protection of the internal power forces an off-time equal to tOFF(SOA) and pulls the internal error-voltage
MOSFET and is not specifically intended to protect the converter from (VE) down by 1/2 of its maximum value in order to ensure the switch
output short-circuit or overload fault conditions. remains within its SOA.
For universal line input parts, the OCP limit is set as a function of the Fast Output Voltage Overvoltage Protection (FBOV)
input line voltage, one setting for low-line voltages and another The HiperPFS-3 features a voltage feedback threshold comparator on
setting for high-line voltages. This helps to bound power limit into the FEEDBACK pin which detects an output voltage overvoltage
short-circuits as well as helps to minimize the stress on the switch condition to allow rapid response, independent of the COMPENSA-
due to current overloads at higher input line conditions. Figure 12 TION pin response, to prevent hazardous voltage conditions from
illustrates the hysteretic adjustment of the OCP levels as a function occurring. The overvoltage protection is hysteretic – the voltage on
of VOLTAGE MONITOR pin line-sensing. This equates to selecting the the FEEDBACK pin must drop by 0.1 V (equating to an output voltage
low-line OCP (the greater of the two settings) when the peak of the drop of 10 V) before switching is re-started.
input line voltage drops below 140 VAC for 3 consecutive half-cycles
and selecting the high-line OCP level (the lesser of the two settings) FEEDBACK to COMPENSATION Pin Short Detection Safeguard
when the input line voltage rises above 170 VAC for 1 half-cycle, The PFC controller continuously monitors the FEEDBACK and
(except in follower mode, as described in the subsequent sections). COMPENSATION pins to ensure that there are no potential short
conditions between the adjacent FEEDBACK and COMPENSATION
The HiperPFS-3 utilizes a high input line OCP after detecting the pins, which could result in output overvoltage conditions if not
VOLTAGE MONITOR pin above the high-line threshold, VHIGH+. The detected. In the event a potential short is detected, a rapid short
controller reverts back to low-line OCP (as well as low-line frequency check is performed and a shutdown is executed in the event that a
slide) only after 3 consecutive half-line cycle peak values that are suspected short is validated.

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Open FEEDBACK Pin Protection • NLA implemented via fixed current sources for quick transient
The FEEDBACK pin continuously sinks a static current of IFBPD [VCC > response, replaces switched voltage gain in HiperPFS-2.
VCCUVLO+] to protect against a fault related to an open FEEDBACK pin • Off-time controller senses actual feedback voltage to calculate
or incomplete feedback divider network. The internal current sink off-time to prevent inductor saturation.
introduces a small static offset to the output regulation which can be • VOLTAGE MONITOR pin uses voltage-mode sensing rather than
accounted for in selecting the output feedback regulation components current-mode sensing of HiperPFS-2, allowing flexibility in selection
(FEEDBACK pin divider). of magnitude of resistor divider.
• Reduced minimum line feed-forward gain supports higher power
Hysteretic Thermal Shutdown delivery during line sag events.
The thermal shutdown circuitry senses the controller die temperature • Line feed-forward gain implemented with true squaring function,
which is well coupled to the heat sink through the exposed, grounded versus piece-wise linear approximation.
pad. The threshold is set at 117 °C typical with a 36 °C hysteresis. • Line voltage functions performed in the digital domain: peak detec-
When the controller die temperature rises above this threshold (OTP), tion, feed-forward, brown-in/brown-out and PF-enhancement.
the controller initiates a soft-shutdown and remains disabled until the • Peak detector incorporates filtering to smooth out cycle-to-cycle
controller die temperature falls by ~36 °C, at which point the device variation.
will re-initiate the start-up sequence. • Optimized brown-in/brown-out thresholds with tighter tolerances.
The maximum time delay for soft-shutdown to occur after an OTP • Most timers are derived from an internal high-speed clock
event is detected is tOTP beyond the next zero-crossing. providing accurate timing.
• eSIP-16 package pinout has been modified for optimal operation
HiperPFS-3 Additional Features and Changes and internal grounding.
• No-load/light-load power consumption optimized by re-engineered
Note: HiperPFS-3 is not a pin for pin drop-in replacement of
burst-mode operation.
HiperPFS-2 due to functional changes and optimizations.
• Reduced control-engine power consumption: standby current
• Improved operating supply voltage maximum: 15 V. reduced by ~4~5× HiperPFS-2 nominal.
• Reduced external component count. • HiperPFS-3 REFERENCE pin replaces HiperPFS-2 REFERENCE pin;
• Improved tolerance of key parameters over a wide temperature external bypass capacitor replaces external 1% resistor.
range. • VFB(REF) reduced to 3.85 V nominal from 6.0 V nominal in
• Modified architecture improving noise immunity and operational HiperPFS-2.
accuracy. • Peak detector optimized across maximum operational conditions
• Feedback network voltage divider is decoupled from the loop when operating with distorted waveforms and line drop-outs.
compensation components. • Square-wave detector feature for improved UPS operation.
• High-line only family of parts added to HiperPFS-3 family. • Power good function is independent of engine during operation
• Peak-detector supports deglitch methodology for NTC in-rush except for OTP events.
current limiting at start-up. • FBOFF fault check is always enabled during operation.
• Digital Power Factor Enhancer algorithm improves high-line light • Maximum CCM peak switching frequency has been increased from
load power factor. ~100 kHz to 123 kHz.
• OTA error amplifier replaces voltage error amplifier of
HiperPFS-2.

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Output Power Table

eSIP Package
Efficiency Power Mode CREF = 0.1 mF Full Power Mode CREF = 1.0 mF
Maximum Continuous Maximum Continuous
Product Output Power Rating at Peak Output Power Output Power Rating at Peak Output Power
90 VAC2 Rating at 90 VAC4 90 VAC2 Rating at 90 VAC4
Minimum3 Maximum Minimum3 Maximum
PFS7523L/H 65 W 90 W 100 W 85 W 110 W 120 W
PFS7524L/H 80 W 110 W 125 W 100 W 130 W 150 W
PFS7525L/H 110 W 150 W 170 W 140 W 185 W 205 W
PFS7526H 140 W 190 W 215 W 180 W 230 W 260 W
PFS7527H 175 W 235 W 265 W 220 W 290 W 320 W
PFS7528H 210 W 285 W 320 W 270 W 350 W 385 W
PFS7529H 245 W 335 W 375 W 300 W 405 W 450 W
Efficiency Power Mode CREF = 0.1 mF Full Power Mode CREF = 1.0 mF
Maximum Continuous Maximum Continuous
Product Output Power Rating at Peak Output Power Output Power Rating at Peak Output Power
180 VAC2 Rating at 180 VAC4 180 VAC2 Rating at 180 VAC4
Minimum3 Maximum Minimum3 Maximum
PFS7533H 155 W 205 W 230 W 195 W 255 W 280 W
PFS7534H 200 W 260 W 290 W 240 W 315 W 350 W
PFS7535H 275 W 360 W 400 W 335 W 435 W 480 W
PFS7536H 350 W 460 W 510 W 415 W 550 W 610 W
PFS7537H 430 W 560 W 625 W 520 W 675 W 750 W
PFS7538H 520 W 675 W 750 W 625 W 810 W 900 W
PFS7539L/H 575 W 745 W 830 W 690 W 900 W 1000 W
Table 2. Output Power Table.
Notes:
1. See Key Application considerations.
2. Maximum practical continuous power at 90 VAC in an open-frame design with adequate heat sinking, measured at 50 °C ambient.
3. Recommended lower range of maximum continuous power for best light load efficiency; HiperPFS-3 will operate and perform below this level.
4. Internal output power limit.

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Application Example limits the current to the diode in the optocoupler. IC U3 provides
optocoupler isolation through connector J2 for a power-good output
A High Efficiency, 275 W, 385 VDC Universal Input PFC signal if required.
The circuit shown in Figure 13 is designed using a device from the
HiperPFS- 3 family of integrated PFC controllers. This design is rated Capacitor C15 is used for reducing the loop length and area of the
for a continuous output power of 275 W and provides a regulated output circuit to reduce EMI and overshoot of voltage across the
output voltage of 385 VDC nominal, maintaining a high input power drain and source of the MOSFET inside U1 at each switching edge.
factor and overall efficiency from light load to full load.
The PFS7527H IC requires a regulated supply of 12 V for operation
Fuse F1 provides protection to the circuit and isolates it from the AC and must not exceed 15 V. Resistors R6, R7, R8, Zener diode VR1,
supply in the event of a fault. Diode bridge BR1 rectifies the AC input and transistor Q2 form a series pass regulator that prevents the
voltage. Capacitors C1-C7 together with inductors L2 and L3 form supply voltage to IC U1 from exceeding 15 V. Capacitors C8, and C9
the EMI filter which reduces the common mode and differential mode filter the supply voltage and provide bypassing and decoupling to
noise. Resistors R1, R2 and CAPZero, IC U2 are required to discharge ensure reliable operation of IC U1. Diode D3 provides reverse
the EMI filter capacitors once the circuit is disconnected. CAPZero polarity protection.
eliminates static losses in R1 and R2 by only connecting these
Resistor R15 programs the output voltage level [via the power good
components across the input when AC is removed.
threshold (PGT) pin] below which the power good [PG] pin will go
Metal oxide varistor (MOV) RV1 protects the circuit during line surge into a high-impedance state. Capacitor C14 provides noise immunity
events by effectively clamping the input voltage seen by the power on the POWER GOOD THRESHOLD pin.
supply.
IC U1 is configured in full power mode by capacitor C10 which is
The boost converter stage consists of inductor L1, and the Hiper- connected to the REFERENCE pin.
PFS-3 IC U1. This stage functions as a boost converter and controls
The rectified AC input voltage of the power supply is sensed by IC U1
the input current of the power supply while simultaneously regulating
using resistors R10-R13. These resistors values are large to minimize
the output DC voltage. Diode D2 prevents a resonant buildup of
power consumption. Capacitor C11 connected in parallel with the
output voltage at start-up by bypassing inductor L1 while simultane-
bottom resistor R13 filters noise coupled into the VOLTAGE MONITOR
ously charging output capacitor C17.
pin.
Thermistor RT1 limits the inrush input current of the circuit at
Output voltage divider network comprising of resistors R16 – R19 are
start-up and prevents saturation of L1. In most high-performance
used to scale the output voltage and provide feedback to the IC.
designs, a relay will be used to bypass the thermistor after start-up to
Capacitor C16 in parallel with resistor R19 attenuates high frequency
improve power supply efficiency. Thermistor RT1 is bypassed by the
noise.
electro-mechanical relay RL1 after the output voltage is in regulation
and a power-good signal from U1 is asserted low. Resistor R3, R4, R14, C12 and C13 are required for shaping the loop response of the
and Q1 drive relay RL1 and optocoupler U3. Diode D1 clamps the feedback network.
relay coil reverse voltage during de-assertion transitions. Resistor R5

D2
1N5408-T

D K
VO
BR1
C3 GBU8K-BP L1 +
F1 330 nF RT1 800 V 400 µH J3-1
L 5A 275 VAC 2.5 Ω R16
3.74 MΩ
t 1%
O

R10
R1 6.2 MΩ
510 kΩ 1% R17
C1 C5 6.2 MΩ
680 pF D1 680 pF 1%
250 VAC 250 VAC
CAPZero L2 R11 PG
90 - 264 9 mH R18
U2 6.2 MΩ 6.2 MΩ
VAC CAP003DG C4 1% VCC
RV1 C7 1%
330 nF CONTROL
320 VAC 275 V 680 nF FB
450 V
R12
E C2 3.74 MΩ HiperPFS-3 C
C6
680 pF D2 680 pF 1% U1
250 VAC 250 VAC PFS7527H PGT
R2
510 kΩ S V G REF
N
L3
330 µH
R14
30.1 kΩ
1% C17
180 µF DC
450 V OUT
R4
16.2 kΩ R3 R13
1% 10 kΩ 162 kΩ
R6 1%
1% 1Ω C15
Q1 Q2 10 nF
MMBT4403 J4-1 1% MMBT4401LT1G
R15 1 kV
+ 332 kΩ
1%
R8
2.21 kΩ
1%
R5
3.01 kΩ 3
J2-2 1%
S1AB-13-F

1 C8 C10 C9 C12 C13 C14

VCC
+
D3

Supply 47 µF 1 µF 1 µF 100 nF 1 µF 1 nF
BZX384-B13,115

50 V 50 V 35 V 25 V 50 V 50 V
Power U3
2
Good LTV817A
13 V
VR1

C16 R19
D1 4 470 pF 162 kΩ
S1AB-13-F R7 50 V 1%
J2-1 RL1 1Ω
1%

J4-2 C11
470 pF VO
50 V

PI-7257-061615 J3-3

Figure 13. 275 W PFC using PFS7527H.

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Design, Assembly, and Layout Considerations Input EMI Filter

The variable switching frequency of the HiperPFS-3 effectively
Power Table modulates the switching frequency and reduces conducted EMI peaks
The data sheet power table as shown in Table 2 represents the associated with the harmonics of the fundamental switching frequency.
maximum practical continuous output power based on the following This is particularly beneficial for the average detection mode used in
conditions: EMI measurements.
For the universal input devices (PFS7523L/H – PFS7529H): The PFC is a switching converter and will need an EMI filter at the
1. An input voltage range of 90 VAC to 264 VAC. input in order to meet the requirements of most safety agency
2. Overall efficiency of at least 93% at the lowest operating voltage. standards for conducted and radiated EMI. Typically a common mode
3. 385 V nominal output. filter with X capacitors connected across the line will provide the
4. Sufficient heat sinking to keep device temperature ≤100 ºC. required attenuation of high frequency components of input current
Operation beyond the limits stated above will require derating. to an acceptable level. The leakage reactance of the common mode
Operation at elevated temperatures could result in reduced MTBF and filter inductor and the X capacitors form a low pass filter. In some
performance degradation, e.g. reduced efficiency, reduced power designs, additional differential filter inductors may have to be used to
limit, PF, and potential of observing hysteretic brown-out, etc., and is supplement the differential mode inductance of the common-mode
not recommended. Use of a nominal output voltage higher than 395 V choke.
is not recommended for HiperPFS-3 based designs. Operation at A filter capacitor with low ESR and high ripple current capability
voltages higher than 395 V can result in higher than expected should be connected at the output of the input bridge rectifier. This
drain-source voltage during line and load transients. capacitor reduces the generation of the switching frequency compo-
HiperPFS-3 Selection nents of the input current ripple and simplifies EMI filter design.
Selection of the optimum HiperPFS-3 part depends on required Typically, 0.33 mF per 100 W should be used for universal input
maximum output power, PFC efficiency and overall system efficiency designs and 0.15 mF per 100 W of output power should be used for
(when used with a second stage DC-DC converter), heat sinking 230 VAC only designs.
constraints, system requirements and cost goals. The HiperPFS-3 It is often possible to use a higher value of capacitance after the
part used in a design can be easily replaced with the next higher or bridge rectifier and reduce the X capacitance in the EMI filter.
lower part in the power table to optimize performance, improve
efficiency or for applications where there are thermal design Regulatory requirements require use of a discharge resistor to be
constraints. Minor adjustments to the inductance value and EMI filter connected across the input X capacitance on the AC side of the
components may be necessary in some designs when the next higher bridge rectifier. This is to ensure that residual charge is dissipated
or the next lower HiperPFS-3 part is used in an existing design for after the input voltage is removed when the capacitance is higher
performance optimization. than 0.1 mF. Use of CAPZero integrated circuits from Power Integra-
tions, helps eliminate the steady- state losses associated with the use
Every HiperPFS-3 family part has an optimal load level where it offers of discharge resistors connected permanently across the X capacitors.
the most value. Operating frequency of a part will change depending
on load level. Change of frequency will result in change in peak to Inductor Design
peak current ripple in the inductance used. Change in current ripple For ferrite inductors the optimal design has KP of 0.3 to 0.45. (KP is
will affect input PF and total harmonic distortion of input current. defined as the current peak-to-peak value divided by the peak value
at minimum AC voltage and 90* phase angle, full load). KP <0.3
Input Fuse and Protection Circuit (more continuous) tends towards excessive inductor size, while higher
The input fuse should be rated for a continuous current above the KP >0.45 tends towards excessive winding AC resistance losses due to
input current at which the PFC turns-off due to input under- voltage. large high-frequency AC currents, especially since most ferrite
This voltage is referred to as the brown-out voltage. inductor designs will require >3 winding layers. Flux density at
The fuse should also have sufficient I2t rating in order to avoid maximum current limit should be <3900 gauss to prevent core
nuisance failures during start-up. At start-up a large current is drawn saturation.
from the input as the output capacitor charges to the peak of the If Sendust core material is used, 90m or 125m material is recommended,
applied voltage. The charging current is only limited by any inrush because the higher m materials tend to produce greater inductance at
limiting thermistors, impedance of the EMI filter inductors and the lower currents, and thus reduced peak- to-peak inductor currents at
forward resistance of the input rectifier diodes. A MOV will typically be lower line phase angles (<45*) which reduces losses and improves PF
required to protect the PFC from line surges. Selection of the MOV at lighter loads and higher input voltages. The design target is for H
rating will depend on the energy level (EN1000-4-5 Class level) which at the peak current (low-line, full-load, 90* line phase angle) to be
the PFC is required to withstand. ~60 A-t/cm. Higher H tends towards excessive core loss, and lower
A suitable NTC thermistor should be used on the input side to provide than this increases AC copper losses.
inrush current limiting. Choice of this thermistor should depend on The HiperPFS-3 design spreadsheet simplifies this process and
the inrush current specification for the power supply. NTC thermis- automatically recommends a core size and design for either ferrite or
tors may not be placed in any other location in the circuit as they fail Sendust.
to limit the stress on the part in the event of line transients and also
fail to limit the inrush current in a predictable manner. The example For high performance designs, use of Litz wire is recommended to
in Figure 13 shows the circuit configuration that has the inrush reduce copper loss due to skin effect and proximity effect. For
limiting NTC thermistor on the input side which is bypassed with a toroidal inductors the numbers of layers should be less than 3 and for
relay after PFC start-up. This arrangement ensures that a consistent bobbin wound inductors, inter layer insulation should be used to
inrush limiting performance is achieved by the circuit. minimize inter layer capacitance.

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Output Capacitor
For a 385 V nominal PFC, use of an electrolytic capacitor with 450 V D K
B+
or higher continuous rating is recommended. The capacitance
required is dependent on the acceptable level of output ripple and R1
any hold up time requirements. The equations below provide an easy
way to determine the required capacitance in order to meet the
PG R2
hold-up time requirement and also to meet the output ripple require-
ments. The higher of the two values would be required to be used: VCC
R3
CONTROL
calculated using the equation: FB

C
HiperPFS-3
PGT
R5
CO PFC output capacitance in F. S V G REF
C3 R4 C1
PO PFC output power in watts. CREF C2
tHOLD-UP Hold-up time specification for the power supply
in seconds.
VOUT Lowest nominal output voltage of the PFC in volts. PI-7258-061615
VOUT(MIN) Lowest permissible output voltage of the PFC at
the end of hold-up time in volts. Figure 14. Recommended Feedback Circuit.

Capacitance required for meeting the low frequency ripple specifica-

tion is calculated using the equation: a FEEDBACK pin divider ratio other than the recommended 100:1,
need to be evaluated for trade-offs of the key target parameters of
^ h
the specific design. E.g.: the VOLTAGE MONITOR pin divider ratio can
be modified to be equivalent to that of the feedback divider in order
fL Input frequency in Hz. to optimize power factor. However, this will have an impact on power
∆VO Peak-peak output voltage ripple in volts. limit, as well as brown-in/brown-out thresholds, etc. Modification of
ηPFC PFC operating efficiency. within ±10 V of nominal should not result in dramatically compro-
IO(MAX) Maximum output current in amps. mised performance, but should be thoroughly verified. Changes in
excess of this are not recommended. Itemized trade-offs of this type
Capacitance calculated using the above method should be appropri- are outside the scope of this data sheet.
ately increased to account for ageing and tolerances.
The recommended circuit and the associated component values are
Power Supply for the IC shown in Figure 14.
A 12 V regulated supply should be used for the HiperPFS-3. If the
VCC exceeds 15 V, the HiperPFS-3 may be damaged. In most Resistors, R1 to R4 comprise of the main output voltage divider
applications a simple series pass linear regulator made using an NPN network. The sum of resistors R1, R2 and R3 is the upper divider
transistor and Zener diode is adequate since the HiperPFS-3 only resistor and the lower feedback resistor is R4. Capacitor C1 is to filter
requires approximately ICC(ON) maximum for its operation. any switching noise from coupling into the FEEDBACK pin. Resistor R5,
It is recommended that a 1 mF or larger, low ESR ceramic capacitor capacitor C2 and C3 is the loop compensation network required to
be used to decouple the VCC supply. This capacitor should be placed tailor the loop response to ensure low cross-over frequency and
directly at the IC pin on the circuit board. sufficient phase margin. The recommended values for the compo-
nents used are as follows:
Line-Sense Network
The line-sense network connected to the VOLTAGE MONITOR pin R1 = 3.74 MW
provides input voltage information to the HiperPFS-3. A value of 16 MW R2 = 6.2 MW
is chosen in this example design to minimize power consumption in R3 = 6.2 MW
these resistors. Only 1% tolerance resistors are recommended. R5 = 30.1 kW
C1 = 470 pF
A decoupling capacitor of 470 pF is required to be connected in C2 = 1 mF
parallel with the bottom resistor from the VOLTAGE MONITOR pin to C3 = 100 nF
the GROUND pin of the HiperPFS-3. This capacitor should be placed
directly at the IC pin on the circuit board. When the above component values are used, the value of resistor R4
can be calculated using the equation below:
Feedback Network
A resistor divider network that provides 3.85 V at the FEEDBACK pin at
the rated output voltage should be used for optimal performance. It
should be scaled in direct proportion to the VOLTAGE MONITOR pin ^ h
resistor divider network in order to ensure proper regulation and VO Output voltage.
power delivery. The HiperPFS-3 controller has been optimized for VFB(REF) FEEDBACK pin voltage, 3.85 V.
operation with an output voltage of 385 VDC. Applications requiring
voltages that deviate from this nominal parameter, thereby requiring

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The value of resistor R5 will have to be adjusted in some designs and Heat Sinking and Thermal Design
as a guideline the value from the following calculation can be used: Figures 15, 16, 17 show an example of the recommended assembly
for the HiperPFS-3. In this assembly, no insulation pad is required
and HiperPFS-3 can be directly connected to the heat sink by
mechanical clip or adhesive thermal compound.
PO Maximum continuous output power in watts.
The HiperPFS-3 back metal is electrically connected to the heat sink
VO Nominal PFC output voltage in volts.
and the heat sink is required to be connected to the HiperPFS-3
CO PFC output capacitance in farads.
source terminal in order to reduce EMI.

5
2
1. Heat Sink
(2X) 2. Screw
3. Thermally Conductive Adhesive
4. HiperPFS-3
5. Eyelet Terminal − Electrical Connection to Heat Sink

Figure 15. Heat Sink Assembly – using Thermally Conductive Adhesive.

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2
8
1. Heat Sink
(2X)
6 2. Screw
3. Thermally Conductive Silicone Grease
4. HiperPFS-3
5. Metal Clip
3 6. Washer
7. Screw
4
8. Eyelet Terminal − Electrical Connection to Heat Sink
5
7

Figure 16. Heat Sink Assembly – with Metal Clip.

2
8
(2X) 1. Heat Sink
2. Screw
3. Thermally Conductive Silicone Grease
4. HiperPFS-3
5. Plastic Clip
6. Washer
3
7. Screw
4 8. Eyelet Terminal − Electrical Connection to Heat Sink
5
6

Figure 17. Heat Sink Assembly – with Plastic Clip.

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PCB Design Guidelines and Design Example The connection between the HiperPFS-3 drain node, output diode
drain terminal and the PFC inductor should be kept as short as
The line-sense network and the feedback circuit use large resistance possible.
values in order to minimize power dissipation in the feedback network
and the line-sense network. Care should be taken to place the A low loss ceramic dielectric capacitor should be connected between
feedback circuit and the line-sense network components away from the cathode of the PFC output diode and the source terminal of the
the high-voltage and high current nodes to minimize any interference. HiperPFS-3. This ensures that the loop area of the loop carrying high
Any noise injected in the feedback network or the line-sense network frequency currents at the transition of the MOSFET and helps to
will typically manifest as degradation of power factor. Excessive reduce radiated EMI due to the high frequency pulsating nature of
noise injection can lead to waveform instability or dissymmetry. the diode current traversing through the loop.

The EMI filter components should be clustered together to improve During placement of components on the board, it is best to place the
filter effectiveness. The placement of the EMI filter components on voltage monitor, feedback, reference and bias power decoupling
the circuit board should be such that the input circuit is located away capacitors as close as possible to the pins before the other components
from the drain node of the PFC inductor. are placed and routed. REFERENCE pin decoupling capacitor needs
to have dedicated return path to GROUND pin. Failing to do so could
A filter or decoupling capacitor should be placed at the output of the reduce the noise immunity during surge and ESD test. Power supply
bridge rectifier. This capacitor together with the X capacitance in the return trace from the GROUND pin should be separate from the trace
EMI filter and the differential inductance of the EMI filter section and connecting the feedback circuit components to the GROUND pin.
the source impedance, works as a filter to reduce the switching
frequency current ripple in the input current. This capacitor also helps To minimize the effects of trace impedance on regulation, output
to minimize the loop area of the switching frequency current loop feedback should be taken directly from the output capacitor positive
thereby reducing EMI. terminal. The upper end of the line-sense resistors should be
connected to the high frequency filter capacitor connected at the
output of the bridge rectifier.

Input Bridge PFC

Capacitor Rectifier Inductor

HiperPFS-3

EMI
Auxiliary Filter
Supply
for PFC

L E N
PFC Output AC
Capacitor Input
PFC Thermistor
Output Shorting Relay
PI-7312-062215

Figure 18. PCB Layout Example.

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Quick Design Checklist 2. Maximum drain current – Drain current can be measured
indirectly by monitoring inductor current. A current probe
As with any power supply design, all HiperPFS-3 designs should be should be inserted between the bridge rectifier and inductor
verified on the bench to make sure that component specifications are connection. At maximum ambient temperature, minimum input
not exceeded under worst-case conditions. The following minimum voltage and maximum output load, verify drain current wave-
set of tests is strongly recommended: forms at start-up for any signs of inductor saturation. When
1. Maximum drain voltage – Verify that peak VDS does not exceed performing this measurement with Sendust inductor, it is typical
530 V at lowest input voltage and maximum overload output to see inductor wave-forms that show exponential increase in
power. Maximum overload output power occurs when the current due to permeability drop. This should not be confused
output is overloaded to a level just above the highest rated load with hard saturation.
or before the power supply output voltage starts falling out of 3. Thermal check – At maximum output power, minimum input
regulation. Additional external snubbers should be used if this voltage and maximum ambient temperature; verify that
voltage is exceeded. In most designs, addition of a ceramic temperature specifications are not exceeded for the HiperPFS-3,
capacitor in the range of 33 pF and 100 pF connected across the PFC inductor, output diodes and output capacitors. Enough
PFC output diode will reduce the maximum drain-source voltage thermal margin should be allowed for the part-to-part variation
to a level below the BVDSS rating. When measuring drain-source of the RDS(ON) of HiperPFS-3, as specified in the data sheet. A
voltage of the MOSFET, a high-voltage probe should be used. maximum package temperature of 100 °C is recommended to
When the probe tip is removed, a silver ring in the vicinity of the allow for these variations.
probe tip can be seen. This ring is at ground potential and the 4. Input PF should improve with load, if performance is found to
best ground connection point for making noise free measure- progressively deteriorate with loading, it is a sign of possible
ments. Wrapping stiff wire around the ground ring and then noise pick-up by the VOLTAGE MONITOR pin circuit or the
connecting that ground wire into the circuit with the shortest feedback divider network and the compensation circuit.
possible wire length, and connecting the probe tip to the point
being measured, ensures error free measurement. Probe should
be compensated according to probe manufacturer’s guidelines to
ensure error-free measurement.

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Absolute Maximum Ratings(1,2)

DRAIN Pin Peak Current: PFS7523/PFS7533..............................7.5 A Notes:
PFS7524/PFS7534............................. 9.0 A 1. All voltages referenced to SOURCE, TA = 25 °C.
PFS7525/PFS7535............................11.3 A 2. Maximum ratings specified may be applied one at a time without
PFS7526/PFS7536............................13.5 A causing permanent damage to the product. Exposure to Absolute
PFS7527/PFS7537.............................15.8 A Maximum Ratings conditions for extended periods of time may
PFS7528/PFS7538............................18.0 A affect product reliability.
PFS7529/PFS7539............................21.0 A 3. The absolute maximum rating of the VCC is 17.5 V. This is an
DRAIN Pin Voltage . ................................... -0.3 V to 530 V / 540 V(6) absolute maximum condition that must not be exceeded. Voltages
VCC(3) Pin Voltage .................................................... -0.3 V to 17.5 V between the max operating voltage (15 V) and this abs max
PG .......................................................................... -0.3 V to 17.5 V rating should be very infrequent and short in duration (e.g. at
PG Pin Current........................................................................10 mA start-up or temporary fault conditions). It is not intended as a
V, PGT, FB, C, REF Pin Voltage . ..................................-0.3 V to 5.6 V guarantee of the reliability of the product up to the absolute
Storage Temperature ..............................................-65 °C to 150 °C maximum rating, but is a guideline as to the level of applied
Junction Temperature(4). ..........................................-40 °C to 150 °C voltage above which there is a risk of immediate damage to the
Lead Temperature(5) .............................................................. 260 °C product.
4. Normally limited by internal circuitry. Applies to Controller TJ(C),
MOSFET TJ(M) and Diode Junction Temperature TJ(D).
5. 1/16” from case for 5 seconds.
6. Duration less than 15 ns and IDS ≤ IOCP(TYP).
7. TC(D) diode case temperature.

Qspeed Diode
PFS7523-7529
PFS7536-7539
PFS7533-7535

Peak Repetitive Reverse Voltage (VRRM) 530 V 530 V

Average Forward Current IF(AV) TJ(D) = 150 °C 3A 6A
Non-Repetitive Peak Surge Current (IFSM) 60 Hz, ½ cycle, TC(D) (7)
= 25 °C 50 A 100 A
Non-Repetitive Peak Surge Current (IFSM) t = 500 ms, TC(D) (7)
= 25 °C 130 A 260 A

Thermal Resistance
Thermal Resistance: H/L Package: Notes:
(qJA)(1) ..................................................... 103 °C/W 1. Controller junction temperature (TJ(C)) may be less than the
(qJC)................................................(see Figure 21) MOSFET Junction Temperature (TJ(M)) and Diode Junction
Temperature (TJ(D)).

Conditions
SOURCE = 0 V; VCC = 12 V,
Parameter Symbol Pin Min Typ Max Units
-40 °C < TJ(C) < 125 °C (Note C)
(Unless Otherwise Specified)
Currents
Undervoltage Current
VCC < UVLO+(min)
Consumption After
ICC(UVLO) V = 1 V, C = 0 V, FB = 3.85 V VCC 140 mA
Power-Up of Core and
0 °C < TJ(C) < 100 °C
Zeners

Standby Current
Consumption – No V = 1 V, C = 0 V, FB = 3.85 V
ICC(STBY) VCC 320 mA
Switching Prior to 0 °C < TJ(C) < 100 °C
Brown-In

FB = 3.85 V, C < VERR_MIN,

Current Consumption
V = 1.414 V
– in Burst Mode, ICC(BURST) VCC 395 470 mA
(or 2.828 V for High-Line Only Parts)
No Switching
0 °C < TJ(C) < 100 °C

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Conditions
SOURCE = 0 V; VCC = 12 V,
Parameter Symbol -40 °C < TJ(C) < 125 °C Min Typ Max Units
(Note C) (Unless Otherwise Specified)
Currents (cont.)
PFS7523
0.64 0.75 0.90
PFS7533

PFS7524
0.67 0.79 0.95
PFS7534

PFS7525
0.74 0.88 1.05
No-load on REF PFS7535
Switching at FMIN
PFS7526
Operating Current ICC(ON) (TOFF = TOFF(MIN), 0.79 0.93 1.12 mA
PFS7536
TON = TON(MAX))
0 °C < TJ(C) < 100 °C PFS7527
0.85 1.00 1.20
PFS7537

PFS7528
0.91 1.07 1.28
PFS7538

PFS7529
0.98 1.15 1.38
PFS7539

0 < Pin Voltage < REF

Leakage Current in UVLO V, FB, C, PGT ±10 nA
Ioz 0 °C < TJ(C) < 100 °C
State
VPG = 12 V PG ±0.1 mA

Not Active When

Pull-Down Current
IFB(PD) VCC < UVLO+ FB 100 nA
on Feedback
0 °C < TJ(C) < 100 °C

Not Active When

Pull-Down Current
IV(PD) VCC < UVLO+ V 100 nA
on Voltage
0 °C < TJ(C) < 100 °C

On-Time Controller
Maximum Operating
tON(MAX) 0 °C < TJ(C) < 100 °C 29 34 40 ms
“On”-Time
Off-Time Controller
Maximum Operating
tOFF(MAX) 0 °C < TJ(C) < 100 °C 36 43 48 ms
“Off”-Time

0 °C < TJ(C) < 100 °C

V = 1.414 V (or 2.828 V for High-Line Only)
Off-Time Accuracy tOFF(ACCURACY) ±4.0 %
FB = 3.85 V
C>=4V

Feedback
TJ(C) = 25 °C 3.82 3.85 3.88
Feedback Voltage
VFB(REF) V
Reference 0 °C < TJ(C) < 100 °C 3.75 3.85 3.95

Feedback Error- 3.75 V < VFB < 3.95 V

Amplifier Transconduc- GM VC = 4 V 75 95 105 µA/V
tance Gain 0 °C < TJ(C) < 100 °C

Soft-Shutdown Time tSHUTDWN See Note A 0.86 1.00 1.16 ms

FEEDBACK Pin
Start-Up/Fault VFB(OFF) 0 °C < TJ(C) < 100 °C 0.57 0.64 0.71 V
Threshold

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Conditions
SOURCE = 0 V; VCC = 12 V,
Parameter Symbol -40 °C < TJ(C) < 125 °C Min Typ Max Units
(Note C) (Unless Otherwise Specified)
Feedback (cont.)
FEEDBACK Pin
Undervoltage VFB(UV) 0 °C < TJ(C) < 100 °C 2.09 2.25 2.36 V
Assertion Threshold

FEEDBACK Pin
Overvoltage VFB(OV+) 0 °C < TJ(C) < 100 °C 4.00 4.10 4.20 V
Assertion Threshold

FEEDBACK Pin Over-

VFBREF VFBREF VFBREF
voltage Assertion VFB(OV+REL_FB) 0 °C < TJ(C) < 100 °C
+0.19 +0.245 +0.30
Relative Threshold

FEEDBACK Pin
Overvoltage VFB(OV-) 0 °C < TJ(C) < 100 °C 3.90 4.00 4.10 V
Deassertion Threshold

FEEDBACK Pin Over-

VFBREF VFBREF VFBREF
voltage Deassertion VFB(OV-REL_FB) 0 °C < TJ(C) < 100 °C
+0.11 +0.16 +0.21
Relative Threshold

FEEDBACK Pin
Overvoltage VFB(OVHYST) 0 °C < TJ(C) < 100 °C 0.070 0.085 0.115 V
Hysteresis

COMPENSATION Pin
PF Enhancer Disable VLOW(LOAD+) See Note A 1.1 V
Threshold

COMPENSATION Pin
PF Enhancer Enable VLOW(LOAD-) See Note A 1.0 V
Threshold

COMPENSATION Pin
PF Enhancer VLOW(LOAD_HYST) See Note A 0.1 V
Threshold Hysteresis

COMPENSATION Pin
Burst Disable VERR(MIN+) 0 °C < TJ(C) < 100 °C 0.19 V
Threshold

COMPENSATION pin
VERR(MIN-) 0 °C < TJ(C) < 100 °C 0.1 V
Burst Enable Threshold

COMPENSATION Pin
Burst Threshold VERR(HYST) 0 °C < TJ(C) < 100 °C 0.09 V
Hysteresis

Line-Sense/Peak Detector
Line-Sense Input
V V(RANGE) See Note A 0 4 V
Voltage Range

Universal Input Devices

(PFS7523-PFS7529) 1.08 1.12 1.16
0 °C < TJ(C) < 100 °C
Brown-In
VBR+ V
Threshold Voltage
High-Line Only Input Devices
(PFS7533-PFS7539) 2.30 2.35 2.42
0 °C < TJ(C) < 100 °C

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Conditions
SOURCE = 0 V; VCC = 12 V,
Parameter Symbol -40 °C < TJ(C) < 125 °C Min Typ Max Units
(Note C) (Unless Otherwise Specified)
Line-Sense/Peak Detector (cont.)

Universal Input Devices

(PFS7523-PFS7529) 0.93 0.97 1.02
0 °C < TJ(C) < 100 °C
Brown-Out
VBR- V
Threshold Voltage
High-Line Only Input Devices
(PFS7533-PFS7539) 2.15 2.21 2.27
0 °C < TJ(C) < 100 °C

Brown-In/Out Hysteresis
(After NTC Warm-Up VBR(HYS) 0 °C < TJ(C) < 100 °C 0.13 0.145 0.160 V
Time)

Universal Input Devices

0.86
Brown-Out Threshold (PFS7523-PFS7529)
for High Duty Cycle VBR(SQ) V
Square Wave High-Line Only Input Devices
1.93
(PFS7533-PFS7539)

Universal Input Devices

Start-Up Brown-Out 0.74
(PFS7523-PFS7529)
Threshold Voltage
VBR(NTC) V
(During NTC Warm-Up
High-Line Only Input Devices
Time) 1.57
(PFS7533-PFS7539)

Brown-Out NTC
tBRWNOUT(NTC) See Note A 875 1000 1160 ms
Debounce Timer

Brown-Out
tBRWNOUT See Note A 43 54 66 ms
Debounce Timer

Start-Up Timer for Using

Lower brown-Out tSTARTUP See Note A 875 1000 1160 ms
Threshold (VBR-NTC)

VOLTAGE Pin High-Line

V V(HIGH+) See Note A 2.42 V
Assertion Threshold

VOLTAGE Pin High-Line

V V(HIGH-) See Note A 2.00 V
Deassertion Threshold

VOLTAGE Pin Minimum

VPK(MIN) See Note A 0.71 V
Asserted Peak Value

Current Limit/Circuit Protection

PFS7523L/H VV < 2 V 3.8 4.1 4.3
di/dt = 250 mA/ms
TJ(C) = 25 °C V V > 2.42 V 2.6 2.8 3.0
Over-Current
A
Protection
PFS7524L/H VV < 2 V 4.5 4.8 5.1
di/dt = 300 mA/ms
TJ(C) = 25 °C V V > 2.42 V 3.0 3.3 3.5

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Conditions
SOURCE = 0 V; VCC = 12 V,
Parameter Symbol -40 °C < TJ(C) < 125 °C Min Typ Max Units
(Note C) (Unless Otherwise Specfied)
Current Limit/Circuit Protection (cont.)

PFS7525L/H VV < 2 V 5.5 5.9 6.2

di/dt = 400 mA/ms
TJ(C) = 25 °C V V > 2.42 V 3.6 4.0 4.4

PFS7526H VV < 2 V 6.8 7.2 7.5

di/dt = 500 mA/ms
TJ(C) = 25 °C V V > 2.42 V 4.6 4.9 5.25

PFS7527H VV < 2 V 8.0 8.4 8.8

di/dt = 650 mA/ms
TJ(C) = 25 °C V V > 2.42 V 5.35 5.8 6.2

PFS7528H VV < 2 V 9.0 9.5 9.9

di/dt = 800 mA/ms
TJ(C) = 25 °C V V > 2.42 V 6.0 6.5 7.1

PFS7529H VV < 2 V 10 10.5 11

di/dt = 920 mA/ms
TJ(C) = 25 °C V V > 2.42 V 6.7 7.2 7.7

PFS7533H
di/dt = 250 mA/ms 3.8 4.1 4.3
TJ(C) = 25 °C
Over-Current
IOCP A
Protection
PFS7534H
di/dt = 300 mA/ms 4.5 4.8 5.1
TJ(C) = 25 °C

PFS7535H
di/dt = 400 mA/ms 5.5 5.9 6.2
TJ(C) = 25 °C

PFS7536H
di/dt = 500 mA/ms 6.8 7.2 7.5
TJ(C) = 25 °C

PFS7537H
di/dt = 650 mA/ms 8.0 8.4 8.8
TJ(C) = 25 °C

PFS7538H
di/dt = 800 mA/ms 9.0 9.5 9.9
TJ(C) = 25 °C

PFS7539L/H
di/dt = 920 mA/ms 10 10.5 11
TJ(C) = 25 °C

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Conditions
SOURCE = 0 V; VCC = 12 V,
Parameter Symbol -40 °C < TJ(C) < 125 °C Min Typ Max Units
(Note C) (Unless Otherwise Specified)
Current Limit/Circuit Protection (cont.)
CREF = 1.0 µF
Normalized Frequency ±7
TJ(C) = 25 °C
FLIM %
at Power Limit
0 °C < TJ(C) < 100 °C ±10

SOA Protection
tOFF(SOA) TJ(C) = 25 °C 200 250 300 ms
Fixed Off-Time

Leading Edge Blanking TJ(C) = 25 °C

tLEB 220 ns
(LEB) Time Period See Note A

Minimum On-Time
tON_OCP(MIN) TJ(C) = 25 °C 400 ns
in IOCP
VCC Auxiliary Power Supply
VCC Operating Range VCC UVLO+ 12 15 V

Start-Up VCC
VCCUV(LO+) 0 °C < TJ(C) < 100 °C 9.6 9.85 10.1 V
(Rising Edge)

Shutdown VCC
VCCUV(LO-) 0 °C < TJ(C) < 100 °C 9.05 9.3 9.55 V
(Falling Edge)

VCC Hysteresis VCC(HYS) 0 °C < TJ(C) < 100 °C 0.50 0.57 0.65 V

UVLO Shutdown
tUV(LO-) See Note A 500 ns
Delay Timer

Time From VCC >

V > VBR+
VCCUVLO+ Until Device tRESET 60 75 ms
See Note A
Commences Switching

Series Regulator
REFERENCE Pin Voltage VREF 0 °C < TJ(C) < 100 °C 4.95 5.25 5.45 V

Full Power Mode 0.8 1.0

REFERENCE Pin
CREF μF
Required Capacitance Efficiency Mode 0.08 0.1 0.2

REFERENCE Pin 0 °C < TJ(C) < 100 °C

REFUV+ 5.0 V
UVLO Rising Edge See Note A

REFERENCE Pin 0 °C < TJ(C) < 100 °C

REFUV- 4.4 V
UVLO Falling Edge See Note A
Power Good
Power Good Deasser-
tion Threshold Output IPG(T) 0 °C < TJ(C) < 100 °C; VPGT = 3.0 V -10.65 -10 -9.35 mA
Reference Current

Power Good Delay Time

0 °C < TJ(C) < 100 °C; PG = 20 kW Pull-Up to
(From FB > VPG+ to tPG <15 ms
VCC, See Note A
PG < 1 V)

Power Good
tPG(D) See Note A 57 81 108 ms
Deglitch Time

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Conditions
SOURCE = 0 V; VCC = 12 V,
Parameter Symbol -40 °C < TJ(C) < 125 °C Min Typ Max Units
(Note C) (Unless Otherwise Specified)
Power Good (cont.)
Power Good Internal
VPG(+) 0 °C < TJ(C) < 100 °C 3.55 3.65 3.75 V
Assertion Threshold

Power Good Relative VFBREF VFBREF VFBREF

VPG+REL(FB) 0 °C < TJ(C) < 100 °C
Threshold -0.24 -0.20 -0.16

Power Good V (PGT) = 3 V V (PGT)

VPG(-) 2.94 3.06 V
Deassertion Threshold 0 °C < TJ(C) < 100 °C ±30 mV

POWER GOOD Pin

FB < VPG-
Leakage Current in IOZHPG 500 nA
0 °C < TJ(C) < 100 °C
Off-State

POWER GOOD Pin 0 °C < TJ(C) < 100 °C

VOLPG 2 V
On-State Voltage IPG = 2.0 mA; FB = 3.85 V

Thermal Protection (OTP)

Controller Junction
Temperature (TJ(C)) for TOTP+ See Note A 117 °C
Shutdown

Controller Junction
Temperature (TJ(C)) for TOTP- See Note A 81 °C
Restart

Over-Temperature V > VBR+

TOTP(HYST) 36 °C
Hysteresis See Note A
VTS MOSFET
PFS7523 TJ(M) = 25 °C 0.61 0.76
PFS7533
TJ(M) =100 °C 1.10

PFS7524 TJ(M) = 25 °C 0.51 0.63

PFS7534
TJ(M) = 100 °C 0.92

PFS7525 TJ(M) = 25 °C 0.41 0.51

PFS7535
TJ(M) = 100 °C 0.73

PFS7526 TJ(M) = 25 °C 0.34 0.42

On-State
RDS(ON) ID = 0.5 × IOCP PFS7536 W
Resistance TJ(M) = 100 °C 0.62

PFS7527 TJ(M) = 25 °C 0.30 0.36

PFS7537
TJ(M) = 100 °C 0.52

PFS7528 TJ(M) = 25 °C 0.26 0.32

PFS7538
TJ(M) = 100 °C 0.46

PFS7529 TJ(M) = 25 °C 0.22 0.27

PFS7539
TJ(M)= 100 °C 0.40

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Conditions
SOURCE = 0 V; VCC = 12 V,
Parameter Symbol -40 °C < TJ(C) < 125 °C Min Typ Max Units
(Note C) (Unless Otherwise Specified)
VTS MOSFET
PFS7523
176
PFS7533

PFS7524
210
PFS7534

PFS7525
265
PFS7535
TJ(M) = 25 °C
Effective Output VGS = 0 V, PFS7526
Coss 312 pF
Capacitance VDS = 0 to 80% BVDSS PFS7536
See Note A
PFS7527
369
PFS7537

PFS7528
420
PFS7538

PFS7529
487
PFS7539

TJ(M) = 25 °C, VCC = 12 V

Breakdown Voltage BVDSS 530 V
ID = 250 mA, VFB= V V = 0 V

Breakdown Voltage
Temperature BVDSS(TC) See Note A 0.048 %/°C
Coefficient

PFS7523
TJ(M) =100 °C 80
PFS7533

PFS7524
TJ(M) =100 °C 100
PFS7534

PFS7525
TJ(M) =100 °C 120
VDS = 80% PFS7535
Off-State BVDSS
PFS7526
Drain Current IDSS VCC = 12 V TJ(M) =100 °C 150 mA
PFS7536
Leakage VFB = V V =
VC = 0 PFS7527
TJ(M) =100 °C 170
PFS7537

PFS7528
TJ(M) =100 °C 200
PFS7538

PFS7529
TJ(M) =100 °C 235
PFS7539

Turn-Off Voltage
tR See Notes A, B, C 50 ns
Rise Time

Turn-On Voltage
tF See Notes A, B, C 100 ns
Fall Time

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Parameter Symbol Conditions Min Typ Max Units

Qspeed Diode (3A) PFS7523-7529/7533-7535

DC Characteristics
TJ(D) = 25 °C 0.4 mA
Reverse Current IR VR = 530 V
TJ(D) = 100 °C 0.07 mA

TJ(D) = 25 °C 1.55
Forward Voltage VF IF = 3 A V
TJ(D) = 100 °C 1.47

Junction Capacitance CJ VR = 10 V, 1 MHz 18 pF

Dynamic Characteristics (Note: See Figures 19, 20 for dynamic characteristic definition)
di/dt = 200 A/μs, TJ(D) = 25 °C 26.5
Reverse Recovery Time tRR VR = 400 V ns
IF = 3 A TJ(D) = 100 °C 32

di/dt = 200 A/μs, TJ(D) = 25 °C 40.6

Reverse Recovery
QRR VR = 400 V nC
Charge
IF = 3 A TJ(D) = 100 °C 65.7

di/dt = 200 A/μs, TJ(D) = 25 °C 2.1

Maximum Reverse
IRRM VR = 400 V A
Recovery Current
IF = 3 A TJ(D) = 100 °C 3.0

di/dt = 200 A/μs, TJ(D) = 25 °C 1

Softness Factor = tB/t A S VR = 400 V
IF = 3 A TJ(D) = 100 °C 0.45

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PFS7523-7529/7533-7539

Parameter Symbol Conditions Min Typ Max Units

Qspeed Diode (6A) PFS7536-7539

DC Characteristics
TJ(D) = 25 °C 0.8 mA
Reverse Current IR VR = 530 V
TJ(D) = 100 °C 0.15 mA

TJ(D) = 25 °C 1.51
Forward Voltage VF IF = 6 A V
TJ(D) = 100 °C 1.44

Junction Capacitance CJ VR = 10 V, 1 MHz 41 pF

Dynamic Characteristics (Note: See Figures 19, 20 for dynamic characteristic definition)
Reverse di/dt = 200 A/μs, TJ(D) = 25 °C 28.5
Recovery tRR VR = 400 V ns
Time IF = 6 A TJ(D) = 100 °C 37.3

di/dt = 200 A/μs, TJ(D) = 25 °C 58

Reverse Recovery
QRR VR = 400 V nC
Charge
IF = 6 A TJ(D) = 100 °C 105.5

di/dt = 200 A/μs, TJ(D) = 25 °C 2.95

Maximum Reverse
IRRM VR = 400 V A
Recovery Current
IF = 6 A TJ(D) = 100 °C 4.05

di/dt = 200 A/μs, TJ(D) = 25 °C 0.53

Softness Factor = tB/t A S VR = 400 V
IF = 6 A TJ(D) = 100 °C 0.31

NOTES:
A. Not tested parameter. Guaranteed by design.
B. Tested in typical Boost PFC application circuit.
C. Normally limited by internal circuitry.
D. Test under this condition may require pulsed operation due to self-heat. Pulse parameters (duration, repetition) are TBD.
E. BVDSS 540 V maximum for 10 ns.

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PFS7523-7529/7533-7539

VR

tRR D1
IF L1 DUT
15 V
dIF/dt tR Pulse Generator
tB RG
Q1
0

0.4xIRRM
IRRM
PI-7614-041315

Figure 19. Reverse Recovery Definitions. Figure 20. Reverse Recovery Test Circuit.

PI-7539-061615
Thermal Resistance θJC (°C/W)

Thermal Resistance of Internal Qspeed Diode is 5.2 °C/W for

PFS7523-7529, PFS7533-7535 and 2.6 °C/W for PFS7536-7539.
2.5 Thermal Resistance of Internal Power MOSFET shown below.

1.5

0.5

0
PFS7523/ PFS7524/ PFS7525/ PFS7526/ PFS7527/ PFS7528/ PFS7529/
PFS7533 PFS7534 PFS7535 PFS7536 PFS7537 PFS7538 PFS7539
Figure 21. Thermal Resistance eSIP-16D / eSIP-16G Package ( θJC).

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PFS7523-7529/7533-7539

Typical Performance Characteristics

1.14 1.8

PI-7632-061615

PI-7633-061615
1.12 1.6
1.1
to Room Temperature

to Room Temperature
1.4

RDS(ON) Normalized
I(OCP) Normalized

1.08
1.2
1.06
1.04 1
1.02 0.8
1
0.6
0.98
0.4
0.96
0.94 0.2
0.92 0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature (˚C) Temperature (˚C)
Figure 22. I(OCP) vs. Temperature. Figure 23. Normalized RDS(ON) vs. Temperature.

280 1.08

PI-7635-061615
PI-7634-061615

Normalized Minimum On-Time

270 1.06

1.04
in IOCP (nsec)

260
tOFF(SOA) µs

1.02
250
1
240
0.98

230 0.96

220 0.94
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature (˚C) Temperature (˚C)
Figure 24. t OFF(SOA) vs. Temperature. Figure 25. Normalized On-Time in IOCP vs. Temperature.

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PFS7523-7529/7533-7539

Typical Performance Characteristics

10000 100000

PI-7637-061615

PI-7638-061615
IR-3A-200 V IR-6A-200 V
IR-3A-400 V IR-6A-400 V
IR-3A-530 V IR-6A-530 V
10000
Reverse Current (µA)

Reverse Current (µA)

1000

1000
100
100

10
10

1 1
25 50 75 100 125 150 -40 50 75 100 125 150
Temperature (˚C) Temperature (˚C)
Figure 26. Temperature Dependence of 3 A Qspeed Diode Figure 27. Temperature Dependence of 6 A Qspeed Diode
Reverse Current. Reverse Current

1000

PI-7636-052615
Scaling Factors:
PFS7523L/33H 1
IDSS at 80% of BVDSS (µA)

PFS7524L/34H 1.2
PFS7525L/25H/35H 1.5
PFS7526H/36H 1.8
100 PFS7527H/37H 2.1
PFS7528H/38H 2.4
PFS7529H/39H 2.8

10

1
75 100 125 150
Temperature (°C)
Figure 28. Typical Temperature Dependence of IDSS at 80%
of BVDSS.

31
Rev. C 07/24
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eSIP-16D (H Package)
C

www.power.com
2
0.653 (16.59) 0.586 (14.88) Ref.
A
0.647 (16.43) 0.081 (2.06)
0.077 (1.96)
B

Detail A
2
0.325 (8.25) 0.290 (7.37) 0.216 (5.49)
Pin 1 I.D. 0.320 (8.13) Ref. Ref.
PFS7523-7529/7533-7539

0.519 (13.18)
Ref.

0.016 (0.41) 0.207 (5.26)

0.140 (3.56) Ref. 0.187 (4.75)
0.120 (3.05)

1 3 4 5 6 7 8 9 10 11 13 14 16

0.016 (0.41) 13× 3 4

3 0.047 (1.19) 0.076 (1.93)
0.011 (0.28) 0.024 (0.61) 13×
0.020 M 0.51 M C 0.019 (0.48)
0.038 (0.97) 0.056 (1.42) Ref.
0.118 (3.00) 0.012 (0.30) Ref. 0.010 M 0.25 M C A B

FRONT VIEW SIDE VIEW BACK VIEW

0.038 (0.97)
0.029 Dia Hole
0.062 Dia Pad
0.019 (0.48) Ref. 0.118 (3.00)
10° Ref.
0.060 (1.52) Ref. All Around
0.020 (0.50)
0.021 (0.53)
0.019 (0.48)
0.076 (1.93)

PCB FOOT PRINT

Dimensions in inches, (mm).

0.048 (1.22) All dimensions are for reference.
0.023 (0.58) Notes:
0.046 (1.17)
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.628 (15.95) Ref. 0.027 (0.70) 2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
END VIEW including any mismatch between the top and bottom
of the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches (mm). PI-7242-010614

32
Rev. C 07/24
eSIP-16G (L Package)
2 C

www.power.com
0.653 (16.59) 0.586 (14.88) Ref.
A 0.081 (2.06)
0.647 (16.43)
0.077 (1.96)

2 Detail A
0.325 (8.25) 0.290 (7.37) 0.216 (5.49)
Pin 1 I.D. 0.320 (8.13) Ref. Ref.
0.079 (1.99)
PFS7523-7529/7533-7539

0.069 (1.74)

0.094 (2.40)
0.173 (4.39)
1 4 6 8 10 13 16 16 13 10 8 6 4 1
0.050 (1.26) Ref. 0.163 (4.14)

3 5 7 9 11 14 0.144 (3.66) Ref. 14 11 9 7 5 3

0.016 (0.41) 13×
3 0.047 (1.19) Ref.
0.011 (0.28) 0.076 (1.93)
0.038 (0.97) 3 4
0.020 M 0.51 M C Typ. 3 Pieces
Typ. 9 Places 0.128 (3.26) 0.024 (0.61) 13×
0.056 (1.42) Ref. 0.122 (3.10) 0.019 (0.48)
0.010 M 0.25 M C A B

FRONT VIEW SIDE VIEW BACK VIEW

0.038 (0.97)
0.029 Dia Hole
0.062 Dia Pad
0.019 (0.48) Ref. 10° Ref. 0.094 (2.40)
0.060 (1.52) Ref. All Around 0.020 (0.50)

0.021 (0.53)
0.019 (0.48)
0.076 (1.93)
R0.012 (0.30)
Typ., Ref. PCB FOOT PRINT

0.023 (0.58) Dimensions in inches, (mm).

0.048 (1.22) All dimensions are for reference.
0.046 (1.17) 0.027 (0.70) Notes:
0.628 (15.95) Ref.
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
END VIEW including any mismatch between the top and bottom
of the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches (mm). PI-7256-012114

33
Rev. C 07/24
PFS7523-7529/7533-7539

Part Ordering Information

Part Number Option Quantity
PFS7523L/H Tube 30
PFS7524L/H Tube 30
PFS7525L/H Tube 30
PFS7526H Tube 30
PFS7527H Tube 30
PFS7528H Tube 30
PFS7529H Tube 30
PFS7533H Tube 30
PFS7534H Tube 30
PFS7535H Tube 30
PFS7536H Tube 30
PFS7537H Tube 30
PFS7538H Tube 30
PFS7539L/H Tube 30

Part Marking Information

• HiperPFS Product Family
• HiperPFS-3 Series Number
• Package Identifier
L Plastic eSIP, L Bend
PFS 7523 L H Plastic eSIP

34
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PFS7523-7529/7533-7539

Notes

35
Rev. C 07/24
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Revision Notes Date

A Initial Release. 06/15

B Internal review. 02/20
C Added PFS7539L part. 07/24

For the latest updates, visit our website: www.power.com

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at www.power.com/ip.htm.
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POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:

1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or
death to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.

Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC,
HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI,
PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are
property of their respective companies. ©2023, Power Integrations, Inc.

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