FATIMA MICHAEL COLLEGE OF ENGINEERING & TECHNOLOGY

Madurai – Sivagangai Main Road

Madurai -625 020
An ISO 9001:2008 Certified Institution

LESSON PLAN
Academic year: 2022-2023 Semester: ODD Department : ECE
Sub. Code and Name: EC3352 –Digital System Design Staff In-charge :D.VIJITHA

No. of Page Numbers

S. Cumulative
SYLLABUS TOPICS Periods Teaching
No. Periods T1 T2 R1
required Aids
UNIT I - BASIC CONCEPTS

L1 Review of number systems 1 1 BB

BB
L2 Representation, Conversions 1 2

1-3, BB
L3 Review of Boolean algebra, theorems 1 3
1-5

Sum of product and Product of sum 1-12 BB

L4 1 4
simplification

1-13 BB
L5 Canonical forms min term and max term 1 5

Simplification of Boolean expressions, 1-21, BB

L6 1 6
karnaugh map 1-25

Completely and incompletely specified BB

L7 1 7 1-48
functions

Implementation of Boolean expressions BB

L8 1 8 1-53
using universal gates

BB
L9 Tabulation method 1 9 1-61

UNIT II- COMBINATIONAL LOGIC CIRCUITS

L1 Problem formulation and design of 1 10 3-1 BB

combinational circuits
BB
L2 Code converters 1 11 3-30

BB
L3 1 12 3-3,
Half and Full Adders, Binary Parallel
Adder 3-4

L4 1 13
PPT
Carry look ahead Adder ,BCD Adder

1 14 3-26
BB
L5 Magnitude Comparator

3-45 BB
L6 Decoder, Encoder 1 15
3-61
1 16
PPT
L7 Priority Encoder, Mux / De mux

1 17
PPT
L8 Case study: Digital trans-receiver/8 bit
arithmetic and logic unit
1 18
PPT
L9 Parity Generator/ Checker, Seven
Segment display decoder
UNIT III – SYNCHRONOUS SEQUENTIAL CIRCUITS
1 19 4-5 BB
L1 Latches, Flip Flops-SR,JK,T,D

1 20 4-16
BB
L2 Master/Slave FF, Triggering of FF

4-20,
Analysis and design of clocked 5-1 BB
L3 1 21
sequential circuits

1 22
5-2, BB
L4 Design-Moore/Mealy models
5-3
1 23 5-6
BB
L5 State Minimization

State assignment, lock-out condition BB

L6 1 24 5-8
circuit implementation

Counters , Ripple counters, Ring BB

L7 1 25 4-47
Counters

Shift Registers , Universal Shift BB

L8 1 26 4-36
Registers

Model Development: Designing of BB

L9 1 27
Rolling display/ real time clock

UNIT IV-ASYNCHRONOUS SEQUENTIAL CIRCUITS

L1 1 28 BB
Stable and Unstable states

L2 1 29
BB
Output Specifications

1 30
BB
L3 Cycles and races

1 31
BB
L4 State reduction

1 32
BB
L5 Race free assignments

1 33
BB
L6 Hazards

1 34
BB
L7 Essential Hazards

Fundamental and Pulse mode sequential BB

L8 1 35
circuits

1 36
BB
L9 Design of Hazard free circuits

UNIT V – LOGICAL FAMILIES AND PROGRAMMABLE LOIC DEVICES

1 37 9-1 BB
L1 Logic Families

Propagation Delay, Fan -In and Fan - BB

L2 1 38 9-2
Out

1 39 9-4
BB
L3 Noise Margin - RTL

1 40 9-13,
BB
L4 TTL, ECL , CMOS 9-48,
9-37
1 41 9-53
BB
L5 Comparison of Logic families

Implementation of combinational logic BB

L6 1 42
design using standard ICs

Implementation of Sequential logic BB

L7 1 43
design using standard ICs

1 44 8-2,
BB
L8 PROM,PLA and PAL 8-7,
8-17
Basic memory, Static ROM , PROM, BB
L9 1 45 7-2
EPROM, EEPROM, EAPROM

No. of hours allotted in syllabus: 45 No. of hours required as per plan: 45

Text Books:
1. M. Morris Mano and Michael D. ciletti, ‘Digital Design’,pearson,5th edition,2013(Unit I-V)

References Books:S
1. Atul. P. Godse and Mrs. Deepali A. Godse, ‘Digital Logic Circuits’ Technical publications,2011(Unit I-V)
2. Charles H.Roth, ‘Digital system Design’, Edition , 2013
3. Charles H.Roth,Jr, ‘Fundamental Logic Design’,Jaico Books, 4th Edition , 2002.
4. William I.Fletcher, “An engineering approach to digital design”, prentice- Hall of india, 1980.
5. Floyd T.L., “Digital Fundamentals”, Charles E. Merril publishing company,1982.
Web References:
http://www.slideshare.net/Estiakahmed13/multiplexer-and-demultiplexer-92563361
http://www.slideshare.net/samrinriya/bcd-adder
http://www.slideplayer.com/slide/3312074/?
_gl=1*1mlpffe*_a*RWg3Q3l2SzRaQ2RlWmNrWnJ5S1BxcGNqbjROVEZfcHpGU2toTTFLTXRQd0oy
U0R1Nzh5RTZ5cWIYOFZwYkVzUQ

STAFF IN-CHARGE HOD PRINCIPAL