Unit I

Course handled by

Dr.Saru Meena R.

Assistant Professor

Dept. of Electronics and Communication

Engineering,

Amrita School of Engineering

Amrita Vishwa Vidyapeetham

Coimbatore
Microprocessor

§ Microprocessor → a programmable device that takes in operands, performs

arithmetic and logical operations over the operands according to the program
stored in the memory and produces the output

§ Microprocessor is a silicon chip that has just the processing power. It has no
RAM, ROM or other peripherals on-chip

§ To design a microprocessor based system, the designer has to connect I/O

devices and memory externally

§ Microprocessors are responsible for carrying out the instructions of a computer

program by fetching, decoding, and executing them

§ Microprocessors are typically used in systems that require general-purpose

computing capabilities and are not dedicated to specific control functions

Microprocessor
§ Microprocessors are commonly found in personal computers, laptops,
smartphones and tablets 2
Microcontroller

§ A microcontroller is a small integrated circuit that combines a

microprocessor core, memory, and peripheral devices such as

input/output ports, timers, and analog-to-digital converters

§ Microcontrollers are designed to perform specific tasks and control

functions in embedded systems

§ Microcontrollers are used in applications that are space and cost

critical Microcontroller

§ Microcontrollers are commonly used in various electronic devices,

including home appliances, automotive systems, industrial machinery,

and consumer electronics

3
Use cases of microprocessor

§ Personal Computers (PCs): Microprocessors power the central processing units (CPUs) of PCs, laptops,

and workstations, enabling users to perform various tasks such as web browsing, document editing,

gaming, and multimedia playback

§ Smartphones and tablets: Microprocessors are integral components of smartphones and tablets,

handling tasks like running applications, managing user interfaces, processing images and videos,

and connecting to wireless networks

§ Servers and data centers: Microprocessors are used in servers and data centers to handle large-scale

computational tasks, manage network traffic, store and retrieve data, and run virtualization software

to host multiple virtual machines

4
Use cases of microcontroller

§ Embedded systems: Microcontrollers are extensively used in embedded systems for various

applications such as home appliances (microwaves, washing machines, air conditioners), automotive

systems (engine control units, airbag systems, anti-lock braking systems), industrial automation

(PLCs, robotic arms, CNC machines), consumer electronics (remote controls, digital clocks, smart

thermostats), and medical devices (blood glucose meters, infusion pumps, medical imaging

equipment)

§ IoT devices: Microcontrollers play a vital role in IoT devices for collecting sensor data, processing it

locally, and communicating with other devices or the cloud. Examples include smart home devices

(smart locks, doorbell cameras), wearable devices (fitness trackers, smartwatches), environmental

monitoring systems (weather stations), and industrial IoT solutions (predictive maintenance sensors)

5
Use cases of microcontroller

§ Robotics: Microcontrollers are used in robotics for controlling the movement, sensing, and decision-

making capabilities of robots. They power robot arms, mobile robots (like vacuum cleaners and

drones), robotic toys, educational robots, and industrial robots used in manufacturing processes

§ Automotive electronics: Microcontrollers are integral components of automotive electronics systems,

controlling various functions such as engine management, airbag deployment, anti-lock braking,

traction control, infotainment systems and advanced driver-assistance systems (ADAS).

§ Medical devices: Microcontrollers are used in medical devices for monitoring vital signs, controlling

drug delivery systems, powering prosthetic limbs, managing insulin pumps, and operating diagnostic

equipment such as blood pressure monitors, ECG machines, and pulse oximeters

6
Use cases of microcontroller

§ Remote sensing: Microcontrollers are employed in remote sensing applications for collecting data

from sensors deployed in remote or hazardous environments. Examples include environmental

monitoring, agricultural sensing (soil moisture, temperature, and humidity), and wildlife tracking

§ Security systems: Microcontrollers are used in security systems such as access control systems,

surveillance cameras, alarm systems, and biometric identification systems to monitor and protect

homes, businesses, and public spaces

§ Communication devices: Microcontrollers are used in communication devices such as modems,

routers, WiFi modules, Bluetooth modules, and RF transceivers to enable wireless communication and

data transfer between devices

In summary, microprocessors are suited for applications requiring high computational power and running
complex software, while microcontrollers excel in embedded systems that demand real-time control, low
power consumption, and cost-effectiveness 7
Difference between microprocessor and microcontroller

Basic structure of a microprocessor

Basic structure of a microcontroller

Microprocessor based system : CPU + peripherals connected externally

Microcontroller based system : CPU + peripherals built in a single chip

8
Difference between microprocessor and microcontroller

M It is just a processor. Since memory and I/O

Microprocessor is the
i Memory and I/O 03 components has to be connected
01 heart of the computer 02
components must be externally , the circuit becomes
c system
connected externally large and costly
r
o
Since memory and I/O are
p Less no.of registers ; most
Cannot be used in externally connected, each
05 of the operations are
r 04 06
compact systems instruction will need external
memory based
o operation ; hence it is relatively
c slow

e § Entire power consumption is

s high due to external
§ Clock speed : in GHz
07 components. No power Architecture : Von
s § Communication interface :
saving mode 08 09 Neuman architecture
o § Not suitable for devices USB , Ethernet
running on stored power like § Used in personal computers
r 9
batteries
Difference between microprocessor and microcontroller

M
Microcontroller has the
i Microcontroller is the Since memory and I/O components
processor, memory , I/O
01 heart of the embedded 02 03 are present internally , the circuit
c components and other
system peripherals within a becomes small and cost effective
r
single chip
o
c Since memory , I/O and all the
More no.of registers ;
o Can be used in compact 05 peripherals are internal, the
04 No.of memory based
speed is fast since most of the 06
n systems
operations are less
instructions require only
t
internal components access
r
§ Power consumption is less
o
since all the peripherals are § Clock speed : in KHz or MHz
l 07
on – chip Architecture : Harvard
08 § Communication interface : 09
l § Power saving mode to reduce architecture
SPI,I2C,UART
e the power consumption still § Used in washing machine
10
r further
Microprocessor architectures

01 § Memory architecture refers to the design and organization of a

Memory architecture
processor's memory system. It dictates how the CPU accesses and
interacts with memory

§ The two primary memory architectures are : (a) Von Neumann

architecture and (b) Harvard architecture

02
Instruction set architecture § ISA defines the set of instructions that a processor can execute,
(ISA) along with the processor's registers, data types, addressing modes,
and the overall instruction format

§ The two main types of ISA are : (a) Complex Instruction Set
Computing (CISC) and (b) Reduced Instruction Set Computing
(RISC)

11
Memory architectures of the processor

Von Neumann architecture : The memory holds both instructions

and data that the CPU needs to execute

Harvard architecture : Separate memory spaces for instructions

and data

§ In a Harvard architecture system, the CPU accesses instruction Von Neumann architecture

and data memory spaces separately, which can lead to

improved performance

System bus : The system bus is a collection of wires that connect

Harvard architecture
the CPU, instruction memory, data memory, and I/O devices

§ It is used to transmit data, instructions, and control signals

between these components

12
Memory architectures of the processor

System bus : (a) Data bus (b) Address bus and (c) Control bus

Data bus :

§ The CPU uses a data bus to transfer data

§ The data which is to be sent or retrieved from a device is placed on these lines

§ The size of the data bus = size of the data that the processor can hold

§ These lines are bidirectional, data flow in both directions between the processor and memory

and peripheral device

13
Memory architectures of the processor

Address bus :

§ The address bus carries a memory address

§ In a computer system, each peripheral or memory location is

identified by a numerical value, called an address and the

Von Neumann architecture
address bus is used to carry this numerical value

§ The address bus is unidirectional, bits flow in one direction, from

the processor to a peripheral or a memory location

Harvard architecture

14
Memory architectures of the processor

Control bus :

§ The control bus carries the control signal

§ The control signal is used for controlling and coordinating the

various activities across the computer

Von Neumann architecture

§ It is generated from the control unit within the CPU

§ Different architectures result in a differing number of lines of

wires within the control bus, as each line is used to perform a

Harvard architecture
specific task

§ The control unit generates a specific control signal for every

operation, such as memory read or input/ output operation 15

Instruction set architectures of the processor

Key features of CISC :

§ Complex instructions: Instructions can perform multiple low-level operations, such as memory access and

arithmetic operations, within a single instruction

§ Variable instruction length: Instructions vary in length, allowing more flexibility but complicating the

instruction decoding

§ Rich addressing modes: Supports multiple addressing modes, enabling more complex data manipulation

§ Since each instruction can perform multiple operations, fewer instructions are needed to do a given task ⟹

Size of the code to do a complex task is less ⟹ Code is memory efficient

§ Instruction may take more than a single clock cycle to get executed

§ Less number of general-purpose registers as operations get performed in memory itself

§ More data types and high power consumption

16
Instruction set architectures of the processor
Key features of RISC :

§ Simple Instructions: Each instruction performs a single operation, typically executed in a single clock cycle

§ Fixed instruction length: Instructions are of uniform length, simplifying instruction decoding and
pipelining

§ Load/store architecture: Memory access is limited to specific load and store instructions. The operands will
be loaded from memory to registers (via.) load instructions , the manipulation will be done on the operands
and the result of the computation will be stored from a register to a memory (via.) store instruction

§ Faster instruction execution (one clock cycle) due to the simple instruction set

§ Easier to implement pipelining and parallelism

§ Lower power consumption: RISC processors consume less power than CISC processors, making them ideal
for portable devices

§ Requires more instructions to perform complex tasks ⟹ Larger program size compared to CISC for the
17
same task
Instruction set architectures of the processor

§ More general-purpose registers

§ Simple addressing modes

§ Fewer data types

Use case : Add 2 numbers from memory and store the result back in memory

CISC processor code :

(a) ADD [memory location1], [memory location2], [memory location3]

This instruction will load the values from memory 2 and 3, add them, and store the result in memory 1

RISC processor code : Several instructions would be needed:

LOAD R1, [memory location1] // Load value from memory to register R1

LOAD R2, [memory location2] // Load value from memory to register R2

ADD R3, R1, R2 // Add values in R1 and R2, store in R3

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STORE R3, [memory location3] // Store the result from R3 back to memory
Instruction set architectures of the processor

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19
Instruction set architectures of the processor

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cycles per instruction at the nunc.. § More no.of registers
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20
Little endian vs Big endian

§ Endianness refers to the order in which bytes are arranged in memory

Little Endian System :

§ A little-endian system stores the least significant byte (LSB) at the lowest memory address

§ The “little end” (the least significant part of the data) comes first

§ In a little endian system, a 32-bit integer 0x0A0B0C0D will be stored as follows :

21
Little endian vs Big endian

Big Endian System :

§ A big -endian system stores the most significant byte (MSB) at the lowest memory address

§ The “big end” (the most significant part of the data) comes first

§ In a big endian system, a 32-bit integer 0x0A0B0C0D will be stored as follows :

22
Development board

§ A microcontroller is a single chip that cannot work

alone: Power has to be given , a proper interface to load

and flash the program into it is needed as well as

having ways to display the processed data out of it

§ Experienced electronics builders find it easy to build

circuits on breadboard

§ However, as the complexity of a circuit increases, it

becomes difficult too to use breadboards Arduino uno development board

23
Development board

§ Development boards are PCBs that contain a particular

microcontroller IC and all of the supporting external

circuitry to make the microcontroller easier to use for quick

development and prototyping

§ Take a microcontroller (or a microprocessor) and provide it

with USB port, HDMI-port, power input port, display unit

such as LCD or other meaningful ways to display

information (such as LEDs or Seven-Segment) , ways to give

Arduino uno development board
the input like switch and that is the development board

§ The most popular development boards on the market are

the Raspberry Pi and the Arduino Uno

24
Introduction to ARM

§ The ARM (Advanced RISC Machine) architecture is a family of Reduced Instruction Set Computing

(RISC) architectures for computer processors

§ ARM processors are widely used in a variety of devices due to their power efficiency and high

performance

§ The architecture is known for its simplicity, making it a popular choice in the embedded systems

industry, including smartphones, tablets, wearables, and IoT devices

25
Introduction to ARM

Key features of ARM :

RISC principle:

§ Simplified instruction set for efficient execution

§ Uniform instruction length

§ Large number of general-purpose registers

Load/store architecture:

§ Data processing operations only operate on registers, not directly on memory.

§ Memory access is only performed through specific load and store instructions.

Power efficiency:

§ Optimized for low power consumption, making it ideal for mobile and embedded applications

§ Extensive use of power-saving modes

26
Introduction to ARM

Performance:

§ High performance per watt ratio (Performance per watt ration tells how much performance is obtained

for each watt of power consumed. A higher ratio means the system is more efficient, providing more

performance while consuming minimal power)

§ Ability to execute multiple instructions per clock cycle through advanced pipeline techniques

Advantages of ARM :

§ Cheap

§ It consumes less power (Low power consumption).

§ The devices with ARM processor can have a much better battery life than other processors

§ ARM performs one operation at a time and thus work faster

§ High performance , low code size and low silicon area

27
Introduction to ARM

Enhancements done in RISC architecture for ARM :

§ Barrel shifter in the data path to perform shifting or rotation of data in one clock cycle

§ For a regular shift register, no.of clock cycles = no.of shifts to be done on data

§ Auto increment and auto decrement addressing modes to facilitate block transfer of data (multiple data

elements) in a single instruction without the intervention of CPU

28
ARM processor families

Architecture variations of ARM

29
ARM architecture

§ A processor architecture is characterized by : (a) Data path and (b) Control path

§ Datapath: Performs the actual data processing tasks within the CPU, including arithmetic and logic

operations, data movement, and storage

§ Control path: Manages the execution of instructions by generating control signals that direct the

operations of the data path

Key components of the data path include:

Registers: Small, fast storage locations within the CPU used to hold data temporarily during computation

Arithmetic Logic Unit (ALU): A critical component that performs arithmetic operations (such as addition

and subtraction) and logic operations (such as AND, OR, and NOT)

Multiplexers (MUX): Devices that select one of several input signals and forward the selected input to a

single output line

30
ARM architecture

Buses: Pathways that transfer data between different components of the CPU, such as between the

registers and the ALU

Shifters: Circuits that shift the bits of a data word left or right, often used for multiplication or division by

powers of two

Memory Access Units: Elements that manage reading data from and writing data to memory.

31
ARM architecture

Control path :

§ The control path, also known as the control unit, is responsible for managing and coordinating the

operations of the data path

§ It interprets the instructions fetched from memory, generates control signals to direct the data path,

and ensures that the correct sequence of operations is carried out

Key components of the control path include:

Instruction decoder: A circuit that translates machine language instructions into control signals that guide

the operation of the data path

Control signals: Electrical signals generated by the control unit to control the operation of the data path

components (e.g., selecting which operation the ALU should perform, directing data flow through

multiplexers)
32
ARM architecture

Program Counter (PC): A register that holds the address of the next instruction to be fetched from memory

Timing and sequencing logic: Circuits that manage the timing of operations and ensure that instructions
are executed in the correct order

Interaction between data path and control path :

§ The data path and control path work together to execute instructions in a coordinated manner

§ Instruction fetch: The control unit fetches the next instruction from memory using the program counter

§ Instruction decode: The fetched instruction is decoded by the instruction decoder to generate
appropriate control signals

§ Execution: The control signals direct the data path to perform the necessary operations (e.g., reading
data from registers, performing arithmetic operations in the ALU).

§ Memory access: If needed, the control unit directs the data path to access memory to read or write data

§ Write-back: The results of the computation are written back to the appropriate registers or memory
33
locations
ARM architecture

ARM data path :

§ Data enters the processor core through the Data bus

§ The data may be an instruction to execute or a data item

§ Figure 1 shows a Von Neumann implementation of the ARM— data

items and instructions share the same bus. In contrast, Harvard

implementations of the ARM use two different buses.

§ The instruction decoder translates instructions before they are

executed

Figure 1 : ARM data path

34
ARM architecture

ARM data path :

§ The ARM processor, like all RISC processors, uses a load-store

architecture

§ Load – store architecture has two instruction types for transferring

data in and out of the processor : load instructions copy data from

memory to registers in the core, and conversely the store

instructions copy data from registers to memory

§ There are no data processing instructions that directly manipulate

data in memory
Figure 1 : ARM data path
§ The data processing is carried out solely in registers

35
ARM architecture

ARM data path :

§ Data items are placed in the register file—a storage bank made up

of 32-bit registers

§ Since the ARM core is a 32-bit processor, most instructions treat the

registers as holding signed or unsigned 32-bit values

§ The sign extend hardware converts signed 8-bit and 16-bit numbers

to 32-bit values as they are read from memory and placed in a

register

Figure 1 : ARM data path

36
ARM architecture

ARM data path :

§ ARM instructions typically have two source registers, Rn and Rm,

and a single result or destination register, Rd

§ Source operands are read from the register file using the internal

buses A and B, respectively.

§ The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit)

takes the register values Rn and Rm from the A and B buses and

computes a result

Figure 1 : ARM data path

37
ARM architecture

ARM data path :

§ Data processing instructions write the result in Rd directly to the

register file

§ Load and store instructions use the ALU to generate an address to

be held in the address register and broadcast on the address bus

§ One important feature of the ARM is that register Rm alternatively

can be preprocessed in the barrel shifter before it enters the ALU

§ Together the barrel shifter and ALU can calculate a wide range of

expressions and addresses

Figure 1 : ARM data path
Eg. : ADD R3,R2,R1, LSL #3; R3:=R2+8R1

§ Left shift a register content by 𝑛 times = register content ×2!

38
ARM architecture

ARM data path :

§ After passing through the functional units, the result in Rd is

written back to the register file using the result bus

§ The increment/decrement logic can be done on the content of a

register independent of ALU

§ For load and store instructions, the incrementer ensures that the

address register is automatically updated to point to the next

memory location after each operation

§ This allows the CPU to efficiently read from or write to sequential

Figure 1 : ARM data path
memory locations without needing additional instructions to

manually update the address register

39
ARM architecture

ARM data path :

§ This automation is particularly useful for operations involving

arrays or blocks of data, where sequential access is common

§ The processor continues executing instructions until an exception

or interrupt changes the normal execution flow

Figure 1 : ARM data path

40
ARM programmer’s model

§ ARM programmer’s model → structured way to understand and program ARM processors

§ It includes details about processor’s register, memory, processor modes and instruction set

§ By knowing the register set, memory model, instruction set, processor modes and exception handling

mechanisms, programmers can effectively write and optimize code for ARM-based systems

Register organization of ARM :

§ There are two types of registers : (a) General purpose registers (GPRs) and (b) Special function

registers (SFRs)

§ General purpose registers → 𝑟" − 𝑟#$ . These GPRs are used to hold the operand or address of the

operand

§ Special function registers → 𝑟#% , 𝑟#&, 𝑟#' and Current program status register (CPSR)

§ 𝑟#% : Stack pointer (SP) . SP holds the address of the top of the stack
41
ARM programmer’s model

§ 𝑟#& : Link register (LR) . The LR is used to store the return address whenever

the processor control shifts to the subroutine

§ After executing the subroutine, the processor looks at the LR and comes

back to the main program to complete the execution of the remaining part

of the main program

§ 𝑟#' : Program counter (PC) . PC hold the address of the next instruction to be

executed

§ Size of each register : 32 bit

Figure 2 : Register organization in ARM

42
ARM programmer’s model

§ ARM uses CPSR to monitor and control internal

operations

§ Size of CPSR register is 32 bit

§ It consists of 4 fields: Flags, status, extension and

control

§ The extension and status fields are reserved for future

use Figure 3 : CPSR in ARM

§ The control fields contains the processor mode, state

and interrupt mask bits

43
ARM programmer’s model

§ 𝐵%# ∶ 𝐵$( → N Z C V respectively

§ N → negative flag ; N = 1 if the result of ALU is negative

; N = 0 if the result of ALU positive

§ Z → zero flag ; Z = 1 if the result of ALU is zero ; Z=1 if

the result of ALU is non. – zero

§ C → Carry flag ; C = 1 if the result of ALU has carry out ;

C=0 if the result of ALU doesn’t have carry out Figure 3 : CPSR in ARM

§ V → overflow flag ; V=1 if the result of ALU exceeds 32

bit (overflow condition); V = 0 if the result of ALU is

within 32 bit

44
ARM programmer’s model

§ 𝐵$) ∶ 𝐵( → unused ; reserved for future use

§ 𝐵) ∶ 𝐵* → Interrupt masks

§ 𝐵' : T bit

§ T = 0 ⟹ the processor is in ARM mode

§ T = 1 ⟹ the processor is in Thumb mode

§ 𝐵& ∶ 𝐵" → Processor mode bits Figure 3 : CPSR in ARM

45
Operating modes of ARM 7 processor

§ Operating modes → determine the processor's

privilege level and the set of accessible registers

§ Less privilege (a.k.a. Non privileged) ⟹ restricted

access to system resources to ensure that user

applications cannot interfere with the operating

system or other critical tasks

§ Less privilege mode allows access of only a

subset of registers and SFRs are inaccessible

Figure 4 : ARM 7 operating modes
§ Ex. : Read access to control fields in CPSR , but

still read-write access is given to the conditional

flags
46
Operating modes of ARM 7 processor

§ High privilege (a.k.a. Privileged) ⟹ full access to all system resources, including critical hardware and

SFRs

§ High privilege mode allows full read-write access to the CPSR

§ There are 7 processor mode namely : (a) User mode (b) FIQ (c) IRQ (d) Supervisor (e) Abort mode (f)

Undefined mode and (g) System mode

User mode :

§ Normal mode in which all the user programs are executed

§ It is the only non privileged mode

§ It has limited access to memory , I/O and flags

§ All the other modes are entered through interrupt

47
Operating modes of ARM 7 processor

FIQ:

§ This mode is enabled when high priority interrupt comes in nFIQ pin

§ FIQ interrupts should be served with minimum delay

IRQ :

§ This mode is enabled when a normal interrupt comes in nIRQ pin

§ These interrupts will be served with some delay

Supervisor mode :

§ This mode is enabled when the system restarts

§ It executes the BIOS program

§ The programmer can enter into the system mode from user mode via. software interrupt

48
Operating modes of ARM 7 processor

Abort mode :

§ This mode is entered when unsuccessful attempt is made to access the memory

Undefined mode :

§ This mode is entered when undefined instruction is attempted

§ This happens when a coprocessor instruction is encountered but coprocessor is not available

49
Banked registers

§ Banked registers are a special set of registers that are

used exclusively by certain processor modes

§ This means that when the processor switches to a

different mode (via.) interrupt, it uses a different set of

registers, allowing it to quickly switch contexts without

having to save and restore register values manually

§ Banked registers: Specific to each mode and do not

interfere with other modes.

Figure 5 : Complete ARM register set. Blue color cells
§ Shared registers: Common across modes and must be denote shared registers . Red color and yellow color
cells denote banked registers.
saved and restored using the stack if modified by the

Interrupt Service Routine (ISR)

50
Banked registers

§ SPSR : Saved program status register. This register stores

the CPSR of user mode when the processor switches to

another mode. For example, when the processor switches

from user mode to IRQ mode , the CPSR of user mode has

to be saved in SPSR of IRQ mode

§ The PC of the user mode has to be stored in the respective

mode’s link register (LR)

§ Therefore , when the processor switches from user mode

to any other mode, the CPSR of user mode has to be

Figure 6 : Banked register in each processor mode
loaded into SPSR of the respective mode and PC of user

mode has to be loaded into LR of the respective mode

51
Banked registers

Sequence of operations that happens when an interrupt occurs while the processor is in user mode:

§ The processor automatically switches to IRQ mode to handle the interrupt.

Stack operations:

§ Upon entering the IRQ mode, the processor typically pushes the current state of the shared registers

onto the stack. This includes any shared registers (e.g., R0-R12) that the ISR might modify

§ The stack pointer (R13) in IRQ mode is different from the stack pointer in User Mode because it is

banked, so each mode has its own stack.

52
Banked registers

Handling the Interrupt:

§ The ISR executes, possibly modifying the shared registers as needed

§ Since the original values of these registers were saved on the stack, the ISR can use them without

worrying about corrupting the main program's state.

Restoring registers:

§ Before exiting IRQ mode, the ISR pops the saved register values from the stack, restoring them to their

original state

§ This ensures that when the processor switches back to the user mode, the shared registers have the

same values they had before the interrupt occurred

53
Banked registers

Return to user mode:

§ The ISR executes a special return instruction which typically involves restoring the Program Counter

(PC) and other registers

§ The CPSR must be restored from the appropriate SPSR

§ The PC must be changed back to the relevant instruction address in the user instruction stream

§ The processor resumes execution of the main program as if the interrupt had never occurred

§ Total no.of registers : 37 (User mode : 13 GPRs + 3 SFRs + CPSR ; No.of SPSR : 5 ; Banked registers in FIQ

mode : 7 ; Banked SP and LR in other processor modes apart from user and FIQ mode : 8)

54
Addressing modes in ARM

§ Addressing mode → different ways of specifying the location of operands in an instruction

Immediate addressing mode :

§ In immediate addressing mode, the operand is a constant value specified directly in the instruction itself

Example :

MOV R0, #0x05 ; Load the immediate value 0x05 into R0

ADD R1, R0, #0x10 ; Add the immediate value 0x10 to R0 and store the result in R1

Register addressing mode :

§ In register addressing mode, the operand is located in a register

Example :

MOV R0, R1 ; Copy the value from R1 to R0

ADD R2, R0, R1 ; Add the values in R0 and R1, store the result in R2
55
Addressing modes in ARM

Register indirect addressing mode :

§ In register indirect addressing mode, the operand is located in memory, and that memory address is

held in a register

Example :

LDR R0, [R1] ; Load the value from the address in R1 into R0

STR R2, [R3] ; Store the value in R2 to the memory address in R3

Base + offset addressing mode :

§ This mode uses a base register and an offset to calculate the effective address of the operand

§ The offset can be an immediate value or a register value

56
Addressing modes in ARM

Example : Immediate offset

LDR R0, [R1, #4] ; Load the value from the address (R1 + 4) into R0

LDR R0, [R1, #8] ; Load the value from the address (R1 + 8) into R0

STR R3, [R2, #12]; Store the value in R3 to the address (R2 + 12)

Register offset

LDR R0, [R1, R2] ; Load the value from the address (R1 + R2) into R0

STR R4, [R3, R5] ; Store the value in R4 to the address (R3 + R5)

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Addressing modes in ARM

Pre-Indexed addressing mode :

§ In pre-indexed addressing mode, the address of the operand is calculated using a base register and an

offset first followed by fetching the operand the updated address

Example :

§ LDR R0, [R1, #4]! ; Load the value from the address (R1 + 4) into R0, and update R1

§ STR R2, [R3, #8]! ; Store the value in R2 to the address (R3 + 8), and update R3

Post-Indexed addressing mode :

§ In post-indexed addressing mode, the address of the operand is the value in a base register

§ After accessing the operand, the base register is updated by an offset

Example : LDR R0, [R1], #4 ; Load the value from the address in R1 into R0, then update R1 by 4

STR R2, [R3], #8 ; Store the value in R2 to the address in R3, then update R3 by 8
58
Addressing modes in ARM

Scaled addressing mode :

§ This mode uses a base register and an offset that is scaled (shifted) by a certain amount before being

added to the base register to get the effective address

Example :

LDR R0, [R1, R2, LSL #2] ; Load the value from the address (R1 + R2 * 4) into R0

STR R3, [R4, R5, LSR #1] ; Store the value in R3 to the address (R4 + R5 / 2)

59
ARM instruction set

Types of instructions:

§ Data processing instructions

§ Branch instructions

§ Load store instructions

§ Software interrupt instructions

§ Program status register instructions

§ Co – processor instructions

Load store instructions:

1) Single register load store instructions

2) Multiple registers load store instructions

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Load store instructions

Single register load store instructions:

61
Load store instructions

Sign extension and zero extension:

62
Load store instructions

63
Load store instructions

64
Load store instructions

65
Load store instructions

R1 = R1+4

66
Load store instructions

Load store pre indexing , post indexing and pre indexing with write back

67
Load store instructions

Load store pre indexing , post indexing and pre indexing with write back

68
Load store instructions
STORE instruction

69
Load store instructions
STORE instruction with pre indexing

70
Load store instructions
STORE instruction with post indexing

71
Load store instructions

Data storage in memory in ARM 7

72
Load store instructions

73
Load store instructions

74
Load store instructions

75
Load store instructions

76
Load store instructions

Addressing modes summary

77
Load store instructions

Addressing modes summary

78
Load store instructions

Multiple register load store addressing modes

LDMIA : Load the data from the memory location pointed by

memory pointer into the register first and then increment the
memory pointer by 4

79
Load store instructions

Multiple register load store addressing modes

80
Load store instructions

Multiple register load store addressing modes

LDMIB : Increment the memory pointer by 4 first and then load the
data from the memory location pointed by (memory pointer +4)
into the register

81
Load store instructions

Multiple register load store addressing modes

LDMDA R0! , {R1,R2,R3} LDMDA : Load the data from the memory location pointed by memory
pointer into the register first and then decrement the memory pointer by
Take R0 = 0x01C
4
R3 ← data from [0X01C] ; R0 = R0-4
Note : The data from the lowest memory address has to be loaded into
= 0x018
the register with lowest index and the data from the highest memory
R2← data from [0X018] ; R0 = R0-4 address has to be loaded into the register with highest index
= 0x014

R1 ← data from [0X14] ; R0 = R0-4 =

0x010

After execution ,

R1 = 20 ; R2=30 ; R3 = 40 ; R0=0X10
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Load store instructions

Multiple register load store addressing modes

LDMDB R0! , {R1,R2,R3} LDMDB : Decrement the memory pointer by 4 and then load the data
from the memory location pointed by (memory pointer -4) into the
Take R0 = 0x01C
register
R3 ← data from [R0 - 4] ; R0 = R0-4
Note : The data from the lowest memory address has to be loaded into
= 0x018
the register with lowest index and the data from the highest memory
R2← data from [0X018 - 4] ; R0 = address has to be loaded into the register with highest index
R0-4 = 0x014

R1 ← data from [0X14 - 4] ; R0 = R0-

4 = 0x010

After execution ,

R1 = 30 ; R2=20 ; R3 = 10 ; R0=0X10
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Load store instructions

Multiple register store addressing modes

STMIA : Store the data from the register to

the memory location pointed by memory
pointer first and then increment the
memory pointer by 4

Note : The data from the lowest register

index has to be stored into the lowest
memory address and data from the highest
register index has to be stored into the
highest memory address

84
Load store instructions

Multiple register store addressing modes

STMIB : Increment the memory pointer by 4

first and then store the data from the
register to the memory location pointed by
(memory pointer – 4)

Note : The data from the lowest register

index has to be stored into the lowest
memory address and data from the highest
register index has to be stored into the
highest memory address

85
Load store instructions

Multiple register store addressing modes

STMDA : Store the data from the register to

the memory location pointed by memory
pointer first and then decrement the
memory pointer by 4

Note : The data from the lowest register

index has to be stored into the lowest
memory address and data from the highest
register index has to be stored into the
highest memory address

86
Load store instructions

Multiple register store addressing modes

STMDB : Decrement the memory pointer by

4 first and then store the data from the
register to the memory location pointed by
(memory pointer – 4)

Note : The data from the lowest register

index has to be stored into the lowest
memory address and data from the highest
register index has to be stored into the
highest memory address

87
Stack operations

Push and pop operations on stack

88
Stack operations

89
Stack operations

90
Stack operations

91
Stack operations

92
Stack operations

Stack in ARM

93
Stack operations

Stack in ARM

94
Stack operations

Stack in ARM

95
Stack operations

Stack in ARM

96
Stack operations

Stack in ARM

97
Stack operations

98
Stack operations

99
Stack operations

Stack instructions

100
Stack operations

Stack examples

101
SWAP instruction

§ It swaps the contents of the memory with the contents of the register

§ This instruction is an atomic operation- it reads and write in the same bus operation preventing any

other instruction from reading or writing to that location until it completes

102
SWAP instruction

In this example :
1) Rd is the register R0
2) Rm is the register R1
3) Memory pointer is register R2
Temp = data in the memory location 0x00009000
(i.e.) temp = 0X12345678
Data in memory location 0x00009000 = data in
register R1 = 0X11112222
Data in R0 = temp = 0x12345678
103
ARM instruction for loading 32 bit constant

§ MOV instruction can move only a 8 bit constant to a register

§ Since ARM instructions are 32 bits in size , the ARM instructions cannot specify a general 32 bit constant

§ To aid programming , two pseudo instructions are used to move a 32 bit value into a register

§ Syntax : LDR Rd, = 32 bit constant ; This instruction is the load 32 bit constant pseudo instruction ; Rd = 32

bit constant

§ ADR Rd, label ; Load address pseudo instruction ; Rd = 32 bit relative address

104
Data processing instructions

105
Data processing instructions

106
Data processing instructions

107
Data processing instructions

Example of data processing instruction

108
Data processing instructions

Example of data processing instruction

109
Data processing instructions

Logical instructions

110
Data processing instructions

Data transfer instructions

111
Data processing instructions

Data transfer instructions

112
Data processing instructions

Data move instructions with condition

113
Data processing instructions

Comparison instructions

114
Data processing instructions

Comparison instructions

Note : cc stands for conditional flags which is also known as conditional codes
115
Multiplication instructions

116
Multiplication instructions

MUL , MLA instructions format

117
Multiplication instructions

MUL , MLA instructions use

118
Multiplication instructions

MUL , MLA instructions example

119
Multiplication instructions

UMULL ,UMLAL, SMULL and SMLAL instructions

120
Multiplication instructions

UMULL ,UMLAL, SMULL and SMLAL instructions

121
Multiplication instructions

UMULL ,UMLAL, SMULL and SMLAL instructions

122
Conditional execution instructions

123
Conditional execution instructions

124
Conditional execution instructions

125
Conditional execution instructions

126
Conditional execution instructions

127
Branch instructions

Branch instructions (a.k.a.) Control flow instructions

128
Branch instructions

Control flow instructions

129
Branch instructions

Control flow instructions

130
Branch instructions

Control flow instructions

131
Branch instructions

B (Branch) Instruction:

§ Purpose: The B instruction is used to branch to a specific address in the program.

§ Syntax: B {cond} label

§ B (unconditional): If no condition code is specified, the branch is unconditional, meaning it will always

jump to the target address.

§ B{cond} (conditional): If a condition code is specified (e.g., BEQ, BNE, BGT, etc.), the branch will occur only

if the condition is met.

§ Operation: The program counter (PC) is updated to the address specified by the label, causing execution

to continue from that point.

§ Example: B label – Unconditionally branches to label.

BEQ label – Branches to label only if the Zero flag (Z) is set.
132
Branch instructions

BL (Branch with Link) Instruction:

§ Purpose: The BL instruction is used to branch to a subroutine or function. It also saves the return address

in the link register (LR).

§ Syntax: BL{cond} label

§ BL: Without a condition code, the branch is unconditional.

§ BL{cond} : With a condition code, the branch occurs only if the condition is met.

Operation:

§ The current value of the program counter (PC) plus 4 (address of the next instruction) is saved in the link

register (LR)

§ The program counter is then updated to the address specified by the label, effectively jumping to the

subroutine
133
Branch instructions

BL (Branch with Link) Instruction:

§ At the end of the subroutine , the instruction MOV PC , LR should be given to load PC with the address

from which the execution in the main program should continue

§ Example: BL func – Unconditionally branches to the function func and saves the return address in LR.

BLNE func – Branches to func only if the Zero flag is not set, and saves the return address in LR.

134
Branch instructions

BLX (Branch with Link and Exchange) Instruction:

§ Purpose: The BLX instruction is used to branch to a subroutine while also potentially switching the

instruction set (between ARM and Thumb). It saves the return address in the link register (LR).

§ Syntax: BLX label or BLX register

§ BLX with a label (unconditional): The branch is unconditional and switches the instruction set based on

the target address's least significant bit

§ BLX with a register (unconditional): The branch is unconditional, and the instruction set is switched

based on the value of the least significant bit of the register

135
Branch instructions

BLX (Branch with Link and Exchange) Instruction:

Operation:

§ The current PC + 4 is saved in the link register (LR).

§ The program counter is then updated to the target address (label or register value).

§ If the least significant bit of the target address is 1, the processor switches to Thumb state; if it is 0, it

remains in ARM state.

Example:

§ BLX R0 – Unconditionally branches to the address in R0 and potentially switches the instruction set.

136
Branch instructions

137
Branch instructions

138
Branch instructions

139
Branch instructions

140
Binary encoding of data processing instructions

141
Binary encoding of data processing instructions

142
Binary encoding of data processing instructions

Hex value of binary encoding : 0X02510002

143
Binary encoding of data processing instructions

Hex value of binary encoding : 0X02510002

144
Binary encoding of data processing instructions

Hex value of binary encoding

: 0XE0810102

145
Binary encoding of data processing instructions

Hex value of binary

encoding : 0XE0810312

146
Introduction to LPC 2148

147
Introduction to LPC 2148

LPC 2148 is a ARM 7 based microcontroller from NXP

Features of LPC 2148 :

§ 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package

§ 40 kB of on-chip static RAM and 512 kB of on-chip flash memory

§ In-System Programming/In-Application Programming (ISP/IAP) via on-chip bootloader software

§ USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM

§ Two 10-bit ADCs (AD0,AD1) provide a total of 14 analog inputs (8+6)

§ Single 10-bit DAC provides variable analog output

§ Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM
unit (six outputs) and watchdog

§ Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input

§ 2 parallel ports (port 0 and port 1) (29+16) = 45 GPIO

148
Introduction to LPC 2148

Features of LPC 2148 :

§ Multiple serial interfaces including two UARTs, two Fast I2C-bus (400 kbit/s), SPI and SSP with buffering

and variable data length capabilities

§ Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses

§ 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 𝜇𝑆

§ On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz

§ Power saving modes include Idle and Power-down

§ Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power

optimization

§ CPU operating voltage range of 3.0 V to 3.6 V (3.3 V ±10%) with 5 V tolerant I/O pads

149
Introduction to LPC 2148

Types of buses:

In LPC2148 three types of busses are used to connect the core with other peripherals on chip.

§ Local Bus to connect the on chip memory controllers and fast GPIO’s

§ Advance High Performance Bus (AHB) for interrupt controller

§ VLSI Peripheral Bus (VPB) for other on chip peripherals

§ AHB acts as a bridge for VPB

§ VPB is mainly meant for connecting slower peripherals with processor

150
Introduction to LPC 2148

AHB :

§ The ARM7 core is connected to the Advanced High

Performance Bus (AHB)

§ This is the second fastest bus in ARM7 core

§ Connected to the AHB is the vector interrupt

controller and a bridge to a second bus called the

VLSI peripheral bus (VPB)

§ Since the interrupt vector controller is responsible

Bus architecture
for managing all the device interrupt sources, it is

connected to the ARM7 core by the second fastest

bus
151
Introduction to LPC 2148

VPB :

§ All the user peripherals are connected to the VPB

§ The VPB bridge contains a clock divider, so the VPB

bus can be run at a slower speed than the ARM7

core and the AHB

Why VPB is operated at lower speeds ?

§ First, the user peripherals can run at a slower clock

rate than the main processor to conserve power

Bus architecture
§ Second, it gives Philips the option of adding a

slower peripheral to the LPC2000 family without it

becoming a bottleneck on the AHB bus

152
Introduction to LPC 2148

Optimum speed of VPB :

§ Currently all the on-chip peripherals are capable of

running at 60MHz so the VPB bus can be set to the

same speed as the AHB bus

§ It is important to note that after reset the VPB

divider is set to divide down the AHB clock by four,

so all the on-chip peripherals will be running at 1⁄4

the CPU clock frequency

Bus architecture

153
Introduction to LPC 2148

Local bus:

§ ARM7 bus is the fastest bus

§ The ARM7 local bus directly connects the ARM7

core to the on-chip flash memory and SRAM

§ This direct connection ensures that the ARM7 core

can fetch instructions and data with minimal

latency, which is crucial for high-performance

operation.
§ The direct access path allows the ARM7 core to
Bus architecture
read from and write to these memories very

quickly, making the on-chip SRAM an ideal place

for storing variables and frequently accessed data

154
Introduction to LPC 2148

System functions:

§ This block is used to handle the clock input given to the microcontroller

§ Crystal oscillator is used for generating accurate clock for microprocessor / microcontroller

§ Crystal oscillator will be connected across XTAL1 and XTAL2 (ref. architecture fig.)

§ From the microcontroller, a small frequency clock will be given to the crystal via. XTAL2

§ When the crystal gets a small frequency signal , it will start vibrating in the desired frequency and

generate a clock signal at this desired frequency (say 12 MHz for example)

§ This desired frequency clock signal will be fed to the microcontroller through XTAL1

§ PLL0 is used for multiplying or dividing the clock given by XTAL1. The output of the PLL0 (system

clock) is connected to all the peripherals and processor

§ PLL1 is used for generating the USB clock

155
ARM 7 TDMI – S explanation

ARM 7 TDMI – S :

§ ARM : ARM stands for Advanced RISC Machine. ARM is a family of RISC architectures for computer

processors. RISC architectures are designed to perform a smaller number of types of computer
instructions so that they can operate at a higher speed (perform more millions of instructions per

second, or MIPS)
§ 7: The number 7 indicates the version of the ARM architecture. ARM7 is the seventh generation in the

ARM family, known for its balance between performance, power consumption, and cost, making it

suitable for embedded systems and low-power applications.

§ T : T stands for Thumb. Thumb is an instruction set introduced by ARM that provides 16-bit

compressed instructions rather than the standard 32-bit instructions of the ARM instruction set. The

Thumb instruction set reduces code size and, in some cases, can improve performance due to more

efficient use of memory and the processor's instruction cache..

156
ARM 7 TDMI – S explanation

ARM 7 TDMI – S :

§ D: D stands for Debug. The ARM7TDMI includes a debugging feature that allows developers to debug

their programs directly on the processor. This is done through the EmbeddedICE logic, a set of

debugging hardware that allows the setting of breakpoints, watchpoints, and single-step execution.

§ M: M stands for Multiplier. The ARM7TDMI features a hardware 32-bit multiplier which enhances its

ability to perform arithmetic operations, especially useful in signal processing and other

computational tasks requiring fast multiplication.

§ I: I stands for ICE (In-Circuit Emulation). This is related to the debugging capabilities mentioned

earlier. In-circuit emulation allows developers to test and debug code on the physical hardware,

observing the processor's behavior in real-time as the code runs.

157
ARM 7 TDMI – S explanation

ARM 7 TDMI – S :

§ S: S stands for Synthesizable Core. This means the ARM7TDMI-S core can be synthesized into a

silicon chip using a hardware description language like VHDL or Verilog. This makes it highly

flexible for integration into various types of embedded systems, allowing manufacturers to include

the ARM7TDMI-S core in custom silicon designs.

158