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Dvlsi Unit-2 Notes

The document outlines important coding practices for writing synthesizable Verilog for sequential hardware, emphasizing the use of edge-triggered clocks and non-blocking assignments. It includes tasks such as writing Verilog descriptions for various circuits, state machines, and flip-flops, as well as implementing conditional statements and loops. Additionally, it covers the design of specific digital components like counters and shift registers.

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Sasi Bhushan
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14 views

Dvlsi Unit-2 Notes

The document outlines important coding practices for writing synthesizable Verilog for sequential hardware, emphasizing the use of edge-triggered clocks and non-blocking assignments. It includes tasks such as writing Verilog descriptions for various circuits, state machines, and flip-flops, as well as implementing conditional statements and loops. Additionally, it covers the design of specific digital components like counters and shift registers.

Uploaded by

Sasi Bhushan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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LAKIREDDY BALI REDDY COLLEGE OF ENGINEERING (AUTONOMOUS)

L.B.Reddy Nagar :: Mylavaram – 521 230 :: Krishna Dist.:: A.P.


20VE01 DIGITAL VLSI SYSTEM DESIGN

UNIT- 2
INTRODUCTION TO VERILOG

1 List out the important coding practices while writing synthesizable Verilog for sequential hardware.
Ans (a) Use an edge-triggered clock in the sensitivity list using the posedge or negedge keywords.
(b) Use non-blocking assignments—that is, “<=” inside always blocks although it is possible to get
sequential hardware by certain uses of the blocking “=” operator.
(c) Do not mix blocking and non-blocking statements in an always block.
(d) Do not make assignments to the same variable from more than one always block. This is not a
compile-time error and hence may go unnoticed.
(e) Avoid unwanted latches by assigning a value to combinational output signals in every possible
execution path in the always block. This can be done by
i. including else clauses for if statements,
ii. specifying all cases for case statements or have a default clause at the end, or
iii. Unconditionally assigning default values to all combinational output signals at the beginning of the
always block.
2 Write a Verilog description of the following combinational circuit using concurrent statements. Each gate
has a 5-ns delay, excluding the inverter, which has a 2-ns delay.

Ans

3 Develop behavioral model of the Mealy state machine for BCD to Excess-3 Code Converter based on its
state table. The state change occurs on the rising edge of the clock. The output is computed by a
conditional assignment statement whenever State or Z changes.
Ans
4 Write Verilog code for the following circuit using concurrent statements and always block with sequential
statements. No latches should be generated. Assume that the gate delays are negligible.

Ans
5 Write a Verilog description of the Synchronous (4-bit) up/down decade counter with output Q works as
follows: All state changes occur on the rising edge of the CLK input, except the asynchronous clear
(CLR). When CLR = 0, the counter is reset regardless of the values of the other inputs. If the LOAD input
is 0, the data input D is loaded into the counter. If LOAD = ENT = ENP = UP = 1, the counter is
incremented. If LOAD = ENT = ENP = 1 and UP = 0, the counter is decremented. If ENT = UP = 1, the carry
output (CO) = 1 when the counter is in state 9. If ENT = 1 and UP = 0, the carry output (CO) = 1 when the
counter is in state 0.
Ans

6 Write a Verilog description of an S-R latch using an always block.


Ans
7 A is an array of 20 4-bit registers. Using ‘for loop’ and ‘while loop’ write Verilog code that finds the largest
register in the array,
Ans

8 An M-N flip-flop responds to the falling clock edge as follows:


If M = N = 0, the flip-flop changes state ; If M = 0 and N = 1, the flip-flop output is set to 1; If M = 1 and N =
0, the flip-flop output is set to 0; If M = N = 1, no change of flip-flop state occurs; The flip-flop is cleared
asynchronously if CLRn = 0. Write a complete Verilog module that implements an M-N flip-flop.
Ans

9 Write a Verilog module that describes a 16-bit serial-in, serial-out shift register with inputs SI (serial
input), EN (enable), CK (clock, shifts on rising edge), and a serial output (SO).
Ans
10 Write a ‘conditional signal assignment’ statement, ‘if-else statement’ and ‘case statement’ to represent the
4-to-1 MUX shown subsequently. Assume that there is an inherent delay in the MUX that causes the
change in output to occur 10 ns after a change in input.

Ans

11 Write a Verilog description of an SR latch.


(a) Use a conditional assignment statement (i.e., a behavioral description).
(b) Use the characteristic equation in the Verilog description.
(c) Use the logic gate level structure of an SR latch in the model.
Ans

12 Write at least two different Verilog modules that are equivalent to the following pseudo code: A = B1 when
C = 1 else B2 when C = 2 else B3 when C = 3 else 0; Draw a circuit to implement the statement
Ans

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