1.

(a) Simplify the Boolean function by using K-map: F = ∏M(2, 8, 9, 10, 11, 12, 14) and
implement the real minimal expression in universal logic.
(b) Expand A' + B' to minterms and maxterms.
8 + 4 =12

2. (a) Simplify the following function in SOP form using Quine MC-Cluskey method:
F(A, B, C, D)=∑m(0,1,4,7,9,11,13,15) + ∑d(3,5)

(b) Define the Prime Implicants and Essential Prime Implicants in the Tabular method
with an Example.
8 + 4 =12

3. (a) What is the difference between Decoder and Demultiplexer?

(b) Form a multiplexer tree to give 4X1 MUX from two 2X1 MUX.
(c) Design a combinational circuit, which converts Excess-3 number to its corresponding BCD
number.

(d) Write a short note on odd Parity Generator.

2 + 3 + 4 + 3 = 12

4. (a) Realize the X-OR function using (a) AOI logic, (b) NAND logic.
(b) Add 25+13 in the 8421 BCD code.
(c) Convert the binary 1001 to the Gray code.
(d) Realize the following expression F=A XOR B XOR C using NAND logic.
4 + 2 + 2 + 4 = 12
5. (a) Simplify the Boolean function by using K-map: F=Σm(0, 1, 2, 3, 5, 7, 8, 9, 10, 12, 13)
and implement the real minimal expression in universal logic.
(b) Subtract (-9) from (+12) in 2’s complement system.
8 + 4 =12
6. (a) Implement the following Boolean functions using only NAND or NOR gates.
(i) F(A, B, C) = AB + AC’(B+C)
(ii) F(A, B, C) =(A+B) +(A+C’)(B+C)
(b) Simplify the following Boolean functions using Quine-MacCluskey method:
F (A, B, C, D) = ∑m(1,2,5,7,11,12,13,14,15)

(2 + 2) + 8 =12

7. Convert the given number to the following bases.

(i) (87.5)110=( )2
(ii) (87.5)110=( )8
(iii) (87.5)110=( )16
(iv) (20)12= ( )6
(3 + 3 + 3 + 3) = 12

8. (a) Simplify the following Boolean functions using K-Map:

(i) F(A, B, C)= ∑m(1,2,5,7)
(ii) F(A, B, C)= ∑m(1,2,5,7) + ∑d(0,4)
(b) Add 41+44 in the 8421 BCD code.
(5 + 5) + 2 = 12
9. (a) Find the simplest form of the following Boolean expressions:
(i) F(A, B, C) = AB + AC’(B+C) +AB’
(ii) F(A, B, C) =(A+B) +(A+C’)(B+C) +BC’.
(b) Convert the Gray code 1001 to its equivalent Binary code.
(5 + 5) + 2 = 12
10. (a) Design and implement a Full Adder circuit using two Half Adders.
(b) With the help of a logic diagram and a truth table, explain an Octal to Binary
encoder.
(c) Design a Half-subtractor using only NAND gates.

4 +4 + 4 = 12

11. (a) Implement the following function using 8:1 MUX: F(A, B, C, D)=∑m(1, 3, 4, 11, 12, 13,
14, 15)
(b) Realize a Full Adder Circuit using 3 to 8 Decoder.

6 +6 + = 12

12. (a) Design a 16:1 multiplexer using 8:1 multiplexers and necessary logic gates.

(b) Design a 4-to-16 Decoder using Two 3-to-8 Decoders.

(c) Implement the following function using 4:1 MUX: F(A, B, C)=∑m(1, 3, 5, 6)

4 + 4 + 4 = 12

13. (a) What is the difference between Decoder and Demultiplexer?

(b) Form a multiplexer tree to give 4X1 MUX from two 2X1 MUX.
(c) Design a combinational circuit, which converts Excess-3 number to its corresponding BCD
number.

(d) Write a short note on odd Parity Generator.

2 + 3 + 4 + 3 = 12
14. (a) Draw the gate level circuit diagram of a positive edge-triggered JK flip-flop and
explain its operation with the help of a truth table. How is the race around condition
eliminated?
(b) What is a shift register? Distinguish between a shift register and a counter.

(c) Design a 4-bit ring counter using J-K flip-flops.

(4+2) + 3 + 3 = 12

15. (a) Design a Synchronous 3 bit Up Counter using J-K Flip-Flops.

(b) Convert S-R flip-flop to J-K flip-flop.

7 + 5 = 12
16. (a) With neat diagrams explain the working of the following types of shift registers.
(i) serial-in parallel-out (ii) parallel-in serial-out (iii) parallel-in parallel-out (iv)
serial-in serial-out
(b) Convert J-K flip-flop to D flip-flop.
8 + 4 = 12

17. (a) Draw the circuit diagram of a master-slave JK flip-flop using all NAND gates and
explain the circuit operation.
(b) Draw a neat diagram of a 4-bit Bi-directional shift register using mode control (M).
When M is logic zero then left shift and right shift for M is logic one.
6 + 6 = 12

18. (a) What do you mean by Race-around condition of a flip-flop? How can it be overcome?

(b) What is the main difference between a latch and a flip-flop?

(c) Convert D flip-flop to S-R flip-flop.

3 + 3 + 6 = 12

19. (a) What is the difference between synchronous counter and asynchronous counter?
(b) Draw a timing diagram of a 3- bit Ring counter.
(c) Design a MOD -10 synchronous binary UP counter using J-K flip-flop and necessary
logic gates.
3 + 4 + 5 = 12

20. (a) Design a MOD-6 ripple counter.

(b) What is the lock-out condition of a counter?
(c) Convert J-K flip-flop to S-R flip-flop.

6 + 3 + 3 = 12

21. (a) Design a counter with the following sequence 3 2 7 5 6. Show a detailed
state diagram, state table and design procedure. Draw the logic diagram. Use J-K
flip-flops and other necessary logic gates for designing.

12

22. (a) Design a Synchronous BCD counter Using J-K Flip-Flop.

12

23. (a) What is a Finite State Machine?

(b) What do you mean by the term ‘State Table’? Compare the state diagram and the
state table?
(c) Describe the operation of a serial binary adder.
2 + (2+3) + 5 = 12

24. (a) Distinguish between synchronous and asynchronous latches.

(b) What are Preset and Clear inputs?
(c) Define the following terms as applicable to flip-flops. (i) Set-up time, (ii) Hold time,
(iii) Maximum Clock frequency, (iv) Propagation delay time, (v) Power Dissipation.

(d) What is a data lock-out flip-flop?

3 + 2 + 5 + 2 = 12

25. (a) Distinguish between synchronous and asynchronous counters.

(b) What is the difference between a ring counter and a ripple counter?
(c) Design a mod-7 asynchronous counter using J-K flip-flops.

3 + 3 + 6 = 12

26. (a) Design a 2-input NAND gate using a CMOS inverter.

(b) Design a basic 2 input TTL NAND gate and explain.
(c) Implement the function Y= (A+B)’ using CMOS logic circuit.
4 + 4 + 4 = 12

27. (a) What are ROM and RAM? What are the basic differences between EPROM and
EEROM?
(b) Draw a NOR Gate using RTL logic circuit.
(c) Design a 2-input NOR gate using a CMOS inverter.
4 + 4 + 4 = 12

28. (a) Write short notes on the following :

(i) Tri-state gates in the TTL family.
(ii) EPROM
(iii) TTL NAND GATE
(iv) PLA
(3+3+3+3) = 12

29. (a) Design a basic 2 input TTL NOR gate and explain.
(b) Write short notes on the following :
(i) PLD
(ii) ECL logic family
(iii) Tri State logic
30. (a) Design the circuits for the given Boolean functions using CMOS logic family.
(i) F1=A’+B’+C’
(ii) F2=A’.B’.C’
(b) Draw a dynamic RAM cell and explain its operation.
(4+4)+4=12

31. (a) Design a 3-input NOR gate using RTL logic family.
(b) Draw a static RAM cell and explain its operation.
(c) Explain the differences between PAL & PLA with a basic example.
4+4+4=12

32. (a) Design a 3-input NAND gate using RTL logic family.
(b) Explain the concepts of fan-in and fan-out for logic families.
(c) Explain the operation of a programmable switch used in EEPROM.
4+4+4=12
33. (a) What is a Finite State Machine?
(b) What do you mean by the term ‘State Table’? Compare the state diagram and the
state table?
(c) Describe the operation of a serial binary adder.
2 + (2+3) + 5 = 12

34. (a) Distinguish between synchronous and asynchronous latches.

(b) What are Preset and Clear inputs?
(c) Define the following terms as applicable to flip-flops. (i) Set-up time, (ii) Hold time,
(iii) Maximum Clock frequency, (iv) Propagation delay time, (v) Power Dissipation.
(d) What is a data lock-out flip-flop?

3 + 2 + 5 + 2 = 12

35. (a) Distinguish between synchronous and asynchronous counters.

(b) What is the difference between a ring counter and a ripple counter?

(c) Design a mod-7 asynchronous counter using J-K flip-flops.

3 + 3 + 6 = 12
36. (a) Explain the operation of a 4-bit binary ripple carry adder circuit with block
schematic.

(b) Design a 3-bit binary to Gray code converter circuit.

6 + 6 = 12

37. (a) Realize 3-input XOR gate with 4:1 Multiplexer.

(b) Design 1-bit magnitude comparator circuit using basic logic gates.
(c) Realize the following Boolean function using 3 to 8 line Decoder: F(A, B,
C)=∑m(3,5,6,7)

4 + 4 + 4 = 12

38. (a) Design and implement a full adder circuit using basic logic gates.
(b) Design a 4:1 MUX using basic logic gates.

(c) Explain tree multiplexers. Design a 16:1 MUX using only multiplexers.
4 + 3 + (1 + 4) = 12

39. (a) Design and implement a full sub tractor circuit using basic logic gates.
(b) Explain the role of De-MUX. Implement the given Boolean function using a suitable
Multiplexer.
F(A, B, C) =(A+B’)+(A+C’)(B+C)
(c) Design and implement a Binary-to-Octal decoder circuit using necessary logic gates.
4 + (1 + 4) + 3 = 12