Laboratory Manual

VLSI Design Laboratory

EEE/ECE 412 (V1, V2)
EEE/ECE 411L (V3)

Department of Electrical & Electronic Engineering (EEE)

School of Engineering (SoE)
Brac University

Revision: July 2022

A. Course Objectives:
The objectives of this course are to
a. Introduce the fundamentals, implementation and applications of VLSI.
b. Provide students with sound understanding of fabrication technology and layout design of VLSI chips.
c. Introduce designing and using different systems including clocked sequential circuits, PLAs and memory
systems.

B. Course Outcomes, CO-PO-Taxonomy Domain & Level- Delivery-Assessment Tool:

Sl. CO Description POs Bloom’s Delivery Assessment
taxonomy methods and tools
domain/level activities
EEE 411 VLSI Design
Apply the knowledge of CMOS circuits
CO1 a Cognitive/ Apply Lecture, Notes Quiz, Exam
in delay and capacitance calculation
Analyze different combinational and
Assignment,
CO2 sequential circuits, systems and a Cognitive/ Analyze Lecture, Notes
Exam
memory cells
Design basic arithmetic and logical unit Assignment,
CO3 c Cognitive/ Create Lecture, Notes
and simple finite state machines Project
EEE 411L VLSI Design Laboratory
Use VLSI and VHDL tools to
Cognitive/ Apply
implement schematics and layout level Lab Class, Lab Work, Lab
CO4 e Psychomotor/
and Finite State Machines for Tutorial Exam, Project
Manipulation
combinational and sequential circuits
Function effectively in a group
Affective/ Lab Class,
CO5 environment to complete a design i Project
Characterization Tutorial
project
Communicate findings of VLSI work Lab Class, Lab Report,
CO6 j Affective/ Valuing
through reports and assignments Lecture Project Report

C. Mark Distribution
Assessment Tools Weightage (%)
Attendance (Class Performance) 10
Lab Report 30
Project (Presentation & Viva + Report) 30 (10+20)
Simulation Question1 (Transient or DC analysis) 15
Simulation Question2 (Verilog using nclaunch) 15
Total 100

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D. References
Sl. Title Author(s) Publication Edition Publisher ISBN
01 CMOS Digital Integrated Sung-Mo (Steve) 2014 4th McGraw- 13:
Circuits Analysis & Design Kang, Yusuf Leblebici, Hill 978-007338
Chul Woo Kim Education 0629
02 CMOS VLSI DESIGN A Neil H. E. Weste; Dave 2010 4th Pearson 13:
CIRCUITS AND SYSTEMS Harris 978-032154
PERSPECTIVE 7743
03 Basic VLSI Design Douglas A. Pucknell 1994 3rd Prentice 0-13-07915
and Kamran Hall 3-9
Eshraghian
04 Design of VLSI Systems: A Linda E. M. 1987 1st Scholium 13:
Practical Introduction Brackenbury Int 978-033340
8216

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Lab Safety and Security Issues

1. Laboratory Safety Rules (General Guidelines):

The Department of EEE maintains general safety rules for laboratories. The guideline is attached in front of
the door in each of the laboratories. The written rules are as follows.

1. Always check if the power switch is off before plugging into the outlet. Also, turn the instrument or
equipment OFF before unplugging from the outlet.
2. Students must be familiar with the locations and operations of safety and emergency equipment
like Emergency power off, Fire alarm switches, and so on.
3. Eating, drinking, chewing gum inside electrical laboratories are strictly prohibited.
4. Do not use damaged cords or cords that become too hot or cords with exposed wiring and if
something like that is found, inform the teacher/LTO right away.
5. No laboratory equipment can be removed from their fixed places without the teacher/LTO’s
authorization.

2. Electrical Safety:
To prevent electrical hazards, there are symbols in front of the Electrical Distribution Board, High voltage
three-phase lines in the lab, Backup generator, and substation. Symbols related to Arc Flash and Shock
Hazard, Danger: High Voltage, Authorized personnel Only, no smoking, etc. are posted in required places.
Only authorized personnel are allowed to open the distribution boxes.

3. Electrical Fire:
If an electrical fire occurs, try to disconnect the electrical power source, if possible. If the fire is small, you
are not in immediate danger, use any type of fire extinguisher except water to extinguish the fire. When in
doubt, push the Emergency Power Off button.

4. IMPORTANT:
Do not use water on an electrical fire.

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● Laboratory Plan
Class Topic Page Is this experiment used
Week for any CO assessment?

1. Introductory Session 5-6

2. Expt1: Familiarization with remote access technique to 7-13

Cadence server, Linux OS and Linux commands

3. Expt2: Design of CMOS Inverter Circuit and Performing 14-3 CO4

Transient Analysis 4

4. Expt3: Performing DC and Parametric analysis of a CMOS 35-6 CO4

Inverter and Symbolic Representation of CMOS Circuits 0
and Delay Calculation

5. Expt4: Introduction to Verilog HDL and familiarization with 61-6

Altera Quartus as simulation tool for Verilog HDL codes. 6

6. Expt5: Familiarization with Multiplexer-Demultiplexer, 67-7

Encoder-Decoder and Different Types of Counters using 1
Blocking and Non-blocking statements.

7. Software Test 1 CO4

8. Expt6: Introduction to Testbench for Design Verification 72-8

Using Cadence. 3

9. Expt7: Implementing Finite State Machines using Verilog 84-9 CO4

HDL. 1

10. Expt8: RTL Synthesis of a Digital Subsystem using 92-

Cadence Genus

11. Expt9: Physical Design from Verilog HDL using Innovus

12. Software Test 2 CO4

13. Project Work

14. Project Report Submission and Project Presentation CO5, CO6

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Updated by:
Md. Mahmudul Islam & Ehsanul Karim

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Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 0

○ Introductory Session

■ Objective:
i) Know about Laboratory Course Outline and Assessment Plan.
ii) Know about relevant Laboratory COs.
iii)Brief overview of each experiment.
iv) Getting an idea about required software for this lab.
v) Discussion on Project.
vi) Group Formation for lab work.

■ Detailed Instructions:
● General Instructions:
The soft copy version of the lab manual will be provided to the students so that they get a clear
picture about the skills they are going to have upon completion of this lab. Detailed lecture plan
will be shared and a brief overview will be given for each experiment. Besides, a small
introduction on Outcome Based Education (OBE) will be shared, followed by course outcomes of
this lab and how each of them is going to be assessed.
● Assessments:
All the assessment plan for this lab will be discussed properly and Marks distribution will be
shared as mentioned in Page No 1 (C). How each assessment will be conducted and COs will be
assessed will be explained properly.
● Group Formation:
Students will work in groups for their lab reports and project so they need to form groups.
a) Each group can have a maximum of three members.

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b) A google sheet will be provided where students will share their details regarding the
group formation.
c) Group should be formed within the first week.

● Lab Report submission guideline:

a. There will be only one hard copy report from each group.
b. The hard copy of the report should be submitted before the starting of next week’s lab
session (a soft copy should also be submitted on the online platform, if necessary).
c. All group members should contribute equally. If any group member is found to be
uncooperative, it should be informed to the instructor immediately for taking action. To
inform the instructor for such case an email can be sent to all the instructors of that lab
section keeping all the members of that particular group in the CC of that email.
d. No late submission will be entertained.
e. There will be Zero Tolerance for Plagiarism.
f. Report’s standard should be maintained (e.g., proper formatting, nice presentation).
g. A cover page should be added with the report. (Template- https://tinyurl.com/labtempbu)

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Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 1

○ Familiarization with remote access technique to

Cadence server, Linux OS and Linux commands

■ Objective:
i) To know about remote access technique to cadence server using Putty.
ii) To know about Linux OS and Linux commands.

■ Software requirements:
i) Xming
ii) Putty

■ Tasks:
● Starting with Putty:
1. Before starting Putty make sure you have turned on Xming and from the taskbar make sure that
Xming is running in the background.

2. Run Putty software and input IP address: 115.127.80.32 (Local - 172.16.0.102) in “Host Name (or
IP address)” and input Port: 5859 (Local - 22) (1 in fig)

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3. Click on SSH then click on X11 and put a check mark on Enable X11 forwarding. (3.1, 3.2 and
3.3 in fig)

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4. Click on Session, now give a name in the “Saved Sessions” field say vlsi_lab and save it. (2 in
fig)

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5. Click on Session then click on the name saved in step 3 say vlsi_lab then click on the load button
and finally click on open(4.0, 4.1, 4.2 and 4.3 in fig).

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6. In the popped-up command window enter the Login ID and Password as given by your
instructor. (Password won’t be visible don’t worry)

7. After successful login type nautilus command in the command window.

● Starting with Linux:

Linux Commands:
1. Go to home-
cd /home
2. Go to a specific directory-
cd directory_name
3. Go to the back in one directory-
cd ..

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4. Two directories back-
cd ../..
5. Go to root-
cd /
6. To see the current directory (present working directory)-
pwd
7. To see the list of files under a directory-
ls
8. Making directory-
mkdir directory_name
9. Removing file from a directory-
rm file_name
10. Removing a directory-
rm –rf directory_name/
11. Making file-
touch file_name.ext ext(.v etc)

● Starting with Cadence:

1. In your desktop window right-click anywhere and select Open in Terminal

2. Type pwd you should get /home/login_id/Desktop (login_id is given by your instructor)
3. Type cd .. to go to previous directory
4. Type pwd your present working directory should be /home/login_id (login_id is given by your
instructor)

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5. Type mkdir vlsi_yourID for example mkdir vlsi_25121001 to create a folder. [Note: For all labs,
you will use the same folder]
6. Type cd vlsi_25121001 to go to that directory
7. Type cp -rf /home/brac/cshrc . to copy cshrc file from the server. Here .(dot) at the end is
representing the present working directory. It will be copied from the source to present working
directory.
8. Type cp -rf /home/brac/cds.lib . to copy cds.lib file from server Here .(dot) at the end is
representing the present working directory. It will be copied from the source to present working
directory.
9. Type ls to see those files in the present working directory
10. Type csh
11. Type source cshrc
12. Type virtuoso
Finally, the Cadence window will pop up. Now you can start working with cadence.

-The End-

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Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 2

○ Design of CMOS Inverter Circuit and Performing

Transient Analysis

■ Objective:
i) Draw schematic of basic CMOS Inverter Circuit.
ii) Perform transient analysis of the CMOS Inverter.
iii) Observe the effect of load capacitance.
■ Theoretical Background:
Complementary metal–oxide–semiconductor (CMOS), also known as complementary-symmetry
metal–oxide–semiconductor (COS-MOS), is a type of MOSFET (metal–oxide–semiconductor
field-effect transistor) fabrication process that uses complementary and symmetrical pairs of p-type and
n-type MOSFETs for logic functions. A CMOS circuit consists of two types of networks which are as
follows,
i) Pull-up Network: The network or combination of PMOS that is responsible for pulling the output
up to logic state 1 or HIGH is called the pull-up network.
ii) Pull-down Network: The network or combination of NMOS that is responsible for pulling the
output down to logic state 0 or LOW is called the pull-up network.

Basic Inverter Circuit:

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Figure 1: Circuit Diagram of an Inverter using CMOS
In an inverter circuit (Figure 1), the output is of the opposite logic state than the input. Here if the input A is
HIGH, it turns the NMOS on and PMOS off. Thus, the pull-down network becomes active and output is
LOW. Again, turning the input LOW turns on the PMOS and turns off the NMOS and thus the pull-up
network is active and output is HIGH.
■ Software requirements:
i) Cadence
■ Tasks:
● Adding Library:
1. Click on File>New>Library

2. Give a name for example vlsi_lab then click on Attach to an existing technology library then click
OK.

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3. The following window will pop up. Select gpdk045 (45 referring as 45nm process) then click OK.

4. Verify your vlsi_lab library by clicking on Tools>Library Manager

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5. In the following popped-up window, you will see the library name (vlsi_lab ) at the left-most
column.

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● Creating Inverter Schematic in Virtuoso:
1. Click on File>New>Cellview

2. The following window will pop up. Set up the New File form as follows
Library: vlsi_lab
Cell: my_inverter
View: schematic

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3. To add an Instance, press i (shortcut key) from the keyboard. The following window will pop up.
Select library, cell and view (always symbol) as per the following table, and paste the component
on the schematic window.

Cell Library Parameters

nmos1v gpdk045 Width=120n

pmos1v gpdk045 Width=120n

vdd,gnd analogLib

vpulse analogLib Voltage1=0V, Voltage2=1.2V, period=100ns, delay time=5ns, rise

time=1ns, fall time=1ns pulse width=50ns

vdc analogLib DC voltage=1.2V

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4. To edit the properties of a component, press q (shortcut key) from the keyboard. The following
window will pop up. Select the parameters as given in the following window and keep the rest in
default mode then click OK.

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5. Connect the components as shown by pressing w (shortcut key) to draw wire.

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6. To add pins to a component, press p (shortcut key) from the keyboard. The following window will
pop up. Write Pin Names and select the Direction of the pin and paste the pin on the schematic
window.

Input Pin: Output Pin:

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7. Connect the pins as shown.

8. Click on Check and Save to look for errors.

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● Transient Simulation and use of ADE (Analog Design Environment):
1. Click on Launch>ADE L

2. Click on Setup>Design

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3. Choose your Design Click OK

4. Click on Setup>Simulator/Directory/Host

5. Click OK

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6. Click on Setup>Model Libraries

7. Select the following parameters

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8. Click on Analyses>Choose

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9. Configure the parameters as follows and click OK.

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10. Click on Outputs>To Be Plotted>Select On Design

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11. Click on Vin and Vout wire one by one and you will see Vin and Vout as shown.

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12. Click on Simulation>Netlist and Run

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13. You will get the following graph.

14. To split the graphs

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15. Graphs will split like the following

■ Report Task:
i) Design a 3 input NOR Gate. Show the Circuit Diagram & Transient Response
ii) Design a 3 input NAND Gate. Show Circuit Diagram & Transient Response
iii) Connect a load capacitor at the output node of the circuit designed in (ii) and observe the effect of
load capacitance in the output waveform (100 fF, 1pF, 10pF)
iv) Plot the output waveform of (ii) & (iii) one after another and justify how they are different and why?

■ Comments/Discussion:
● Comment on the obtained results and discrepancies (if any).

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Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 3

○ Performing DC and Parametric analysis of a CMOS

Inverter and Symbolic Representation of CMOS Circuits and
Delay Calculation
■ Objective:
i) Perform DC analysis of a CMOS Inverter.
ii) Perform parametric analysis of a CMOS Inverter circuit (varying the width of the NMOS Transistor).
iii) Create symbol of an Inverter from schematic
iv) Perform simulation using the Inverter symbol.
v) Calculate delay of the Inverter using Calculator tools of cadence
■ Theoretical Background:
We can analyze DC Characteristics of CMOS Gates by studying an Inverter.

Figure 1: Circuit Diagram of an Inverter

In the DC analysis our objective is to obtain the Transfer Characteristic (TC) Curve which is a plot of
Vout as a function of Vin. In order to obtain the TC curve, the input voltage Vin applied at the gate
terminal is varied from 0 to VDD and value of Vout is found for each value of Vin.
Effect of Transistor Size on TC:
Transistor size can modify the TC curve. The Vinv point (where Vout=Vin) can be shifted towards left or
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right by changing the size of any transistor.
Recall β𝑛 = µ𝑛 𝐶𝑜𝑥 (𝑊/𝐿)𝑛 and β𝑝 = µ𝑝 𝐶𝑜𝑥 (𝑊/𝐿)𝑝

If (β𝑛/β𝑝) = 1 TC curve will look like Fig.2 where Vinv=VDD/2 and for different ratios the graph will

shift as shown in Fig.3

Figure 2: TC curve of a CMOS inverter

Figure 3: TC curve of a CMOS inverter for different (β𝑛/β𝑝) ratio

To observe the effect of transistor size on the TC curve, width of NMOS (Wn) can be varied
to vary the (β𝑛/β𝑝) ratio. Thus, we will be able to see the effect from the output plot.

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■ Software requirements:
i) Cadence

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■ Tasks:
● Open the CMOS Inverter Circuit for the analysis:
1. Before starting you have to first open the Inverter Schematic that you created last time. To open,
Click on File>Open

2. From the popped-up window, select Library as vlsi_lab, and from Cells at the right select
my_inverter and click OK. Your inverter schematic will open.

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● Simultaneously Perform DC and Transient analysis using ADE (Analog Design
Environment):
1. Click on Launch>ADE L

2. Click on Setup>Design

3. Choose your Design Click OK

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4. Click on Setup>Simulator/Directory/Host

5. Click OK

6. Click on Setup>Model Libraries

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7. Select the following parameters
Model Libraries: /home/cadence/tech/gpdk045_v_5_0/models/spectre/gpdk045_mos.scs

8. Click on Analyses>Choose

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9. Select dc, check Save DC Operating Point, check Component Parameter

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10. Click Select Component then go to the schematic window and select your vpulse source. The
following window will appear and you have to select DC voltage from the Select Component
Parameter window and click OK.

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11. In the Choosing Analysis window give start and stop voltage 0 and 2 V. Click OK.

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12. In the ADE L window, you will see dc analysis is ready for the simulation.

13. You can also run the transient analysis along with DC analysis. Click on Analyses> Choose> tran
and give 500ns as stop time.

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14. Click on Outputs>To Be Plotted>Select On Design

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15. Select Vin and Vout by clicking on Vin and Vout wire one by one and you will see Vin and Vout as
shown in the following figure.

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16. Click on Simulation>Netlist and Run and You will get the following graph

● Perform Parametric Analysis by varying width of NMOS:

1. To set Design Variables, select the NMOS in the schematic and open object properties (Press Q)
in Total Width Write variable Wn and click OK.
***Don't forget to press check and save your schematic.

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2. Go to the ADE L window click on Variables>Edit

3. In the following window, click on Copy From

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4. All the design variables will be shown on the right.

5. Select Wn and give an arbitrary value as 120n then Click OK

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6. Design Variables Wn will be shown at the left-most column. Click on Tools>Parametric Analysis

7. Double click on Add Variable

8. Select Wn

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9. Configure the parameters as follows.

10. Click on Analyses>Start Selected

11. You will get the following graph.

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● Symbolic Representation of CMOS Circuits:
1. Create a CMOS Inverter schematic as shown, where A is Input pin, Y is output pin and VDD &
VSS are InputOutput pin.

2. After creating the schematic go to the following setting and then click ok,

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3. In the Symbol Generation Options do the modifications and click ok.

4. A window will pop up as shown below,

5. Delete the entire green rectangle by selecting it and pressing the delete button, then your shape
will look like the following,

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6. Then go to Create>Shape>Line/Circle and draw something similar to the figure shown below

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7. Go to File>New>Cellview then create a cell with inverter_test name.

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8. Draw the following schematic by inserting inverter symbol from your library (vlsi_lab). Here A is
input and Y is output pin. Component parameters are listed below,

Library Name Cell Name Properties

vlsi_lab inverter_cc
t

analogLib vdc DC voltage = 1.2V

analogLib gnd

analogLib vpulse Voltage1 = 0V, Voltage 2 = 1.2V, Delay time = 3ns, Rise time = 3ns,
Fall time = 3ns, Period = 50ns, Pulse width = 25ns

analogLib cap Capacitance = 0.1pF

9. After that Launch>ADE L and follow all the steps shown in 4.3 of Expt2. Finally observe the
output wave shape.

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● Delay Calculation of CMOS Circuits:
1. From ADE L go to Tools>Calculator.

10. Click on Vt and then select A and Y pin from the schematic and you will observe similar thing as
shown.

11. In the Function Panel search for delay and hit enter.

12. Do the following setting and click ok.

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13. Click on Tools>Plot and observe the output in the console.

■ Report Task:
i)Design a 2 input XNOR Gate and create a symbol. Show Circuit Diagram, Symbol & Transient
Response.
v) Connect a load capacitor at the output node of the circuit designed in (i) and calculate the delay for
different load capacitance (100 fF, 1pF)
vi) Vary the width of the PMOS Transistor of an Inverter and perform the parametric analysis.
■ Comments/Discussion:
Comment on the obtained results and discrepancies (if any).

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Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 4

○ Introduction to Verilog HDL and familiarization with

Altera Quartus as simulation tool for Verilog HDL codes.

■ Objective:
i) Get familiarized with Verilog HDL and Altera Quartus.

■ Theoretical Background:
Verilog was originally intended for simulation and verification of digital circuits. Subsequently, with the
addition of synthesis capability, Verilog has also become popular for use in design entry in CAD
systems. The CAD tools are used to synthesize the Verilog code into a hardware implementation of the
described circuit.
Verilog allows the designer to represent circuits in two fundamentally different ways. One possibility is
to use Verilog constructs that represent simple circuit elements such as logic gates or even transistors.
A larger circuit is defined by writing code that connects such elements together. This is referred to as
the structural representation of logic circuits. The second possibility is to describe a circuit by using
logic expressions and programming constructs that define the behavior of the circuit but not its actual
structure in terms of gates. This is called the behavioral representation.

■ Software requirements:
i) Altera Quartus

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■ Tasks:
● Construct the following circuit using Verilog HDL and verify the output through timing
diagram:

Figure 1: Circuit Diagram 1

Table 1: Truth table of the circuit shown in Figure 1

x3 x2 x1 f

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1

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Now, the Verilog code for the circuit shown in Figure 1 can be written as,

Structural Representation:

module Exp4(x1,x2,x3,f);
input wire x1,x2,x3;
output wire f;

and(z1,x1,x2);
not(z2,x2);
and(z3,z2,x3);
or(f,z1,z3);

endmodule

Data Flow Representation:

1 module expt1(f,x1,x2,x3);
2 input x1,x2,x3;
3 output f;
4
5 assign f=(x1 & x2) | (~x2 & x3);
6 endmodule

Behavioral Representation:

1 module expt1 (f, x1, x2, x3);

2 input x1, x2, x3;
3 output f;
4 reg f;
5
6 always @(x1 or x2 or x3)
7 if (x2 == 1)
8 f = x1;
9 else

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10 f = x3;
11 endmodule

Construct the following circuit using Verilog HDL and verify the output through timing diagram:

Figure 2: Circuit Diagram 2

Table 2: Truth table of the circuit shown in Figure 2

x4 x3 x2 x1 f

0 0 0 0 1

0 0 0 1 1

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

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1 0 0 1 1

1 0 1 0 1

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

Now, the Verilog code for the circuit shown in Figure 2 can be written as,
Structural Representation:

3
module expt2(f,x1,x2,x3,x4);
input x1,x2,x3,x4;
4
output f;
and (w1,x1,x3);
5
and (w2,x2,x4);
or (g,w1,w2);
6
or (w3,x1,~x3);
or (w4,x4,~x2);
7
and (h,w3,w4);
or (f, g, h);
8
endmodule
9
1
0
1
1
Data Flow Representation:

1 module expt2(f,x1,x2,x3,x4);

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2 input x1,x2,x3,x4;
3 output f;
4 assign f= ((x1 & x3) | (x2 & x4)) | ((x1 | ~x3) & (~x2 |
x4));
5 endmodule

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● Design a 1-bit full adder and using the 1-bit full adder modules, design a 4-bit full adder
using Verilog HDL.

The Verilog code is as follows,

Structural Modelling:

module fulladd4(S0,S1,S2,S3,Cout, A0, A1, A2, A3, B0, B1, B2,

1 B3, Cin);
input A0, A1, A2, A3, B0, B1, B2, B3, Cin;
output S0,S1,S2,S3,Cout;
2 fulladd stage0 (S0,Cout0,A0,B0,Cin);
fulladd stage1 (S1,Cout1,A1,B1,Cout0);
3 fulladd stage2 (S2,Cout2,A2,B2,Cout1);
fulladd stage3 (S3,Cout,A3,B3,Cout2);
4 endmodule

5 module fulladd(S,Cout,A,B,Cin);
input A, B, Cin;
6 output S, Cout;
assign S = A ^ B ^ Cin;
7 assign Cout = (A & B) | (Cin & (A ^ B));
endmodule
8
Structural Modelling 2:
9
1
module Exp4 (carryin, X, Y, S, carryout);
0
input carryin;
1
input[3:0] X, Y;
1
output[3:0] S;
1
output carryout;
2
wire[3:1] C;
1
fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);
3
fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
1
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
4
fulladd stage3 (C[3], X[3], Y[3], S[3], carryout);
1
endmodule
5
module fulladd(Cin, A, B, S, Cout);
input A, B, Cin;
output S, Cout;
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (Cin & (A ^ B));
endmodule

Page | 69
Structural Modelling 3:

module Exp4(X,Y,carryin,carryout,sum);

parameter n=4;
input wire [n-1:0] X,Y;
input wire carryin;
output wire [n-1:0] sum;
wire [n:0] c;
output wire carryout;
genvar k;

assign c[0]=carryin;

generate

for (k=0;k<n;k=k+1)
begin: addbit
fulladd stage(c[k], X[k], Y[k], sum[k], c[k+1]);
// the instances of but fulladd would be addbit[k].stage
end

endgenerate

assign carryout=c[n];
endmodule

module fulladd(Cin, A, B, S, Cout);

input A, B, Cin;
output S, Cout;
assign S = A ^ B ^ Cin;
assign Cout = (A & B) | (Cin & (A ^ B));
endmodule

Behavioral Modelling:

module Exp4(X,Y,carryin,carryout,sum);

parameter n=2;
input wire [n-1:0] X,Y;
input wire carryin;

Page | 70
output reg [n-1:0] sum;
reg [n:0] c;
integer k;
output reg carryout;

always @(X,Y,carryin)
begin

c[0]=carryin;

for (k=0;k<n;k=k+1)
begin
sum[k]=X[k]^Y[k]^c[k];
c[k+1]=(X[k]&Y[k])|(X[k]&c[k])|(c[k]&Y[k]);
end
carryout=c[n];
end

endmodule

Behavioral Modelling2:
module Exp4 (S, A, B, Cin,Cout);
input Cin;
input [3:0] A,B;
output [3:0] S;
output Cout;
assign {Cout,S} = A+B+Cin;

endmodule

■ Report Task:
1. Design a 4 to 1 MUX using Verilog HDL and verify using timing diagram.
2. Design a priority encoder (3>1>0>2) using Verilog HDL and verify using timing diagram.
3. Design a 3 to 8 Decoder using Verilog HDL and verify using timing diagram.
4. Design a 4-bit adder-subtractor (single circuit which will perform both operations as selected by
the user) using Verilog HDL and verify using a timing diagram.

Page | 71
■ Comments/Discussion:
● Comment on the obtained results and discrepancies (if any).

Page | 72
Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 5

○ Familiarization with Multiplexer-Demultiplexer,

Encoder-Decoder and Different Types of Counters using
Blocking and Non-blocking statements.

■ Objective:
This part is intended to build different logic circuits using Verilog HDL and get familiarized with Blocking
and Non-blocking statements.

■ Theoretical Background:
The "<=" operator in Verilog is another aspect of its being a hardware description language as opposed
to a normal procedural language. This is known as a non-blocking assignment. Its action does not
register until after the always block has executed. This means that the order of the assignments is
irrelevant and will produce the same result.
The other assignment operator, "=", is referred to as a blocking assignment. When "=" assignment is
used, for the purposes of logic, the target variable is updated immediately.

■ Software requirements:
i) Altera Quartus

Page | 73
■ Examples:
● Construct a 2 to 1 Mux using if-else conditions in Verilog HDL and verify the output using
the truth table:

Figure 1: Circuit Diagram of a 2 to 1 MUX

Table 1: Truth table of a 2 to 1 MUX

x3 x2 x1 f

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 1

Now, the Verilog code for the circuit shown in Figure 1 can be written as,

module mux2_1(w,s,f);

Page | 74
input [0:1]w;
input s;
output f;
reg f;
always @(w or s)
if (s==0)
f=w[0];
else if (s==1)
f=w[1];
endmodule

We can also use conditional assignment (ternary

operator) to define a 2 to 1 mux

module mux2_1(w,s,f);
input [1:0]w;
input s;
output f;

assign f=(s)?w[1]:w[0];
endmodule

● Construct a 4 to 1 Mux using case statement in Verilog HDL and verify the output from the
timing diagram:
The Verilog code for this can be written as,

module mux4_1(w,s,f);
input [0:3]w;

Page | 75
input [0:1]s;
output reg f;

always @(w,s)
case(s)
0: f=w[0];
1: f=w[1];
2: f=w[2];
3: f=w[3];
default: f=1'bx;
endcase
endmodule

● Write down the behavioral representation of Verilog HDL code for a priority encoder with
default priority (3>2>1>0):
The Verilog code for this can be written as,

module encoder4_2(w,y);

input [3:0]w;
output reg[1:0]y;

always @(w)
casex (w)
4'b1xxx: y=3;
4'b01xx: y=2;
4'b001x: y=1;
4'b0001: y=0;
endcase

Page | 76
endmodule

Page | 77
Blocking versus nonblocking assignment:

always@(*)
begin
p = a ^ b; // blocking
g = a & b; // blocking
s = p ^ cin;
cout = g | (p & cin);
end

Consider the following case

● all the values are initially 0
● at some time a changes from 0 to 1

The following operations occur in the sequence given in the always block

always_comb
begin
p <= a ^ b; // nonblocking
g <= a & b; // nonblocking
s <= p ^ cin;
cout <= g | (p & cin);
end

Page | 78
module example (D, Clock, Q1, Q2);
input D, Clock;
output reg Q1, Q2;
always@(posedge Clock)
begin
Q1=D;
Q2 = Q1;
end
endmodule

module example(D, Clock, Q1, Q2);

input D, Clock;
output reg Q1, Q2;
always@(posedge Clock)
begin
Q1 < = D;
Q2 < = Q1;
end
endmodule

Page | 79
● Write down a Verilog HDL code for an up counter with reset operation:
The Verilog code for this can be written as,

module upcounter(rst,clk,q);
input rst,clk;
output reg[3:0]q;
always @(posedge clk, posedge rst)
begin
if (rst)
q<=0;
else
q<=q+1;
end
endmodule

● Write down a Verilog HDL code for a 4 bit end around shift register with load operation:
The Verilog code for this can be written as,

module shiftreg(d,load,clk,q);
input [3:0]d;
input load,clk;
output reg[3:0]q;

always @(posedge clk)

if (load)

Page | 80
q<=d;
else
//q[3:0]<={q[0],q[3:1]};
begin
q[3]<=q[0];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule

■ Lab Work:
1. Design an 8 to 1 MUX using case statement in Verilog HDL.
2. Write down a Verilog HDL code for a priority encoder for the priority 2>1>3>0.
3. Write down a Verilog HDL code for a 10 to 2 down counter with reset operation.

■ Simulation Results:
● Take screenshot of the outputs.
■ Report Task:
Write down the behavioral representation of Verilog HDL code for the following:
1. Up-Down Counter
2. Ring Counter
3. Johnson Counter

■ Comments/Discussion:
● Comment on the obtained results and discrepancies (if any).

Page | 81
Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 6

○ Introduction to Testbench for Design Verification Using

Cadence.

■ Objective:
i) Writing testbench to test circuits written in Verilog.

■ Theoretical Background:
Verification is necessary to assure the reliable functionality of the design or designed system.
Test-bench is used for functional verification of a design where stimulus patterns are applied to monitor
the behavioral simulation of the design. Following is a pictorial representation of a testbench. Here
andgate (small rectangle) is the andgate module written in verilog code and testbench of andgate
(large rectangle) is the testbench to test the andgate circuit. Besides, using p,q the stimulus patterns
are being applied to this andgate module and the output y of the andgate is observed using r.

Figure1: Testbench for an andgate circuit

Page | 82
Test-bench Template:
1 module testbench_design_name;
2 reg // declaration of input
3 wire // declaration of output
4 //dut- design under test instantiation
5 dut_name instance_name (input/output ports of the dut)
6 //dut- design under test
7 //test vector generation
8 initial
9 begin
10 //multiple statements
11 end
12 //monitoring the inputs and outputs
13 endmodule

Test vector generation:

Statements written inside the initial block are simulated only once at the beginning of the simulation.
Monitoring the inputs and outputs:
To monitor the inputs and outputs $monitor() and $display() are used.
$shm_open(): Opens a waveform database
$shm_probe("AS"): Saves all signals to database
$shm_close(): Closes the waveform database

Other useful commands:

$finish: It exits the simulation whenever executed.
#: It indicates delay. For example, #5 means 5 units of delay. If timescale is defined in ns then it will be
5ns delay.
■ Software requirements:
i) Cadence

Page | 83
■ Examples:
● Construct a 2 input AND gate using Verilog and verify the output by writing a testbench:

1. Log in to your Cadence ID as shown in Expt1. Write the command nautilus. Go to the directory
where the cds.lib and cshrc files are copied. Then create two new documents and2.v and
test_mode.v
2. Right click the and2.v file and select open with gedit. This will open a Verilog file named and2.v
where you need to write your design code.
Verilog Code:
1 module andgate(a,b,y);
2 input a,b;
3 output y;
4
5 assign y = a&&b;
6
7 endmodule

3. Now exit the gedit window and again open the test_mod.v file using gedit as for the previous case.
which will give you a Verilog file to write your testbench code.

module stimulus;

reg a,b;

wire y;

andgate dut(a,b,y);

initial

begin

$shm_open("shm.db",1); // Opens a waveform database

Page | 84
$shm_probe("AS"); // Saves all signals to database

#50 $finish;

#100 $shm_close(); // Closes the waveform database

end

// Stimulate the Input Signals

initial

begin

a=0;b=0;#10;

a=1;b=0;#10;

a=1;b=1;#10;

a=0;b=1;#10;

end

endmodule // stimulus

4. Now open a terminal from this folder and write the commands csh and source cshrc as in
previous experiments. Now write the nclaunch command. A window like this will appear. Right click
on your library name and select set as work library as shown in the figure.

Page | 85
5. Click on your design file and click on the Verilog compiler icon to compile the code.

6. Now select the testbench file and compile that.

Page | 86
7. Now select the test bench module name from your library folder and elaborate it as shown in the
figure.

8. Now select the file vlsi_lab.stimulus from the snapshot folder and launch the simulator as shown
in the figure.

9. This will invoke the Simvision tool. From the design browser window select your testbench module
name and click on the button marked in black to send the signals to the plotting window.

Page | 87
10. Now a plotting window will arrive and click on the play button and observe the waveforms.

Page | 88
Testbench Code examples:
i) Another approach of the testbench shown earlier.

module stimulus;
reg a,b;
wire y;

andgate dut(a,b,y);
integer i;

initial
begin
$shm_open("shm.db",1); // Opens a waveform database
$shm_probe("AS"); // Saves all signals to database
#50 $finish;
#100 $shm_close(); // Closes the waveform database
end

initial
begin
a = 0;
b = 0;

for (i=0;i<4;i=i+1)
begin
{a,b}=i;
#10;
end
end
endmodule

Page | 89
● Construct a 2 to 1 Mux and verify the output:

Verilog Code:
module mux2(a,b,s,y);

input wire a,b,s;

output reg y;

always @(a,b,s)
if(s)
y=b;
else
y=a;
endmodule

Testbench Code:
module stimulus;
reg a,b,s;
wire y;

mux2 dut(a,b,s,y);

initial
begin
$shm_open("shm.db",1); // Opens a waveform database
$shm_probe("AS"); // Saves all signals to database
#50 $finish;
#100 $shm_close(); // Closes the waveform database
end

initial
begin
Page | 90
a = $random;
b = $random;
s=0;
#10;
s=1;
#10;
end
endmodule

● Construct a D Flip flop with asynchronous Reset and verify the output:
Verilog Code:
module dff(clk,d,q,reset);

input wire clk,d,reset;

output reg q;

always @(posedge clk)

if(reset)
q<=0;
else
q<=d;
endmodule

Testbench Code:
i) Clock pulse as input data (D)

module dff_tb;
reg d,clk,rst;
wire q;
dff dut(clk,d,q,rst);

// Generate clock pulse

initial
Page | 91
forever #10 d = ~d;
initial
forever #5 clk = ~clk;

initial
begin
$shm_open("shm.db",1); // Opens a waveform database
$shm_probe("AS"); // Saves all signals to database
#80 $finish;
#100 $shm_close(); // Closes the waveform database
end

// Test vector
initial
begin
clk = 0;
d = 0;
rst = 1;
#10 rst=0;
#45 rst=1;
#5 rst=0;
end
endmodule

ii) Random value as input data (D)

module dff_tb;
reg d,clk,rst;
wire q;
dff dut(clk,d,q,reset);

// Generate clock pulse

initial
forever #10 d = $random;
initial
forever #5 clk = ~clk;

initial
begin
$shm_open("shm.db",1); // Opens a waveform database
$shm_probe("AS"); // Saves all signals to database
Page | 92
#50 $finish;
#100 $shm_close(); // Closes the waveform database
end

// Test vector
initial
begin
clk = 0;
d = 0;
rst = 1;
#10 rst=0;
#45 rst=1;
#5 rst=0;
end
endmodule

■ Simulation Results:
● Take screenshot of the outputs.
■ Report Task:
Design the following circuits using Verilog HDL and verify:
1. 4 to 1 MUX having each input as 2-bit binary number
2. 1 to 4 Demultiplexer having input as 2-bit binary number
3. 3 to 8 Decoder
■ Comments/Discussion:
● Comment on the obtained results and discrepancies (if any).

Page | 93
Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 7

○ Implementing Finite State Machines using Verilog HDL

■ Objective:
● This part is intended to get familiarized with finite state machines and implementing and verifying
them using Verilog in Cadence software.

■ Theoretical Background:
A finite state machine is a computation model that can be implemented with hardware or software and can
be used to simulate sequential logic. A system where particular inputs cause particular changes in state
can be represented using finite state machines.
There can be two types of Finite State Machines (FSM) based on the dependence of output on input:
i. Moore Type Machines: The sequential circuits whose outputs depend only on the states of
the circuit are of Moore type. It has been named after Edward Moore.
Example: Suppose that we wish to design a circuit that meets the following specification:
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of a clock signal.
3. The output z is equal to 1 if during two immediately preceding clock cycles the input w
was equal to 1. Otherwise, the value of z is equal to 0.

Page | 94
Thus, the system follows the following input output combination.

Clock 1 2 3 4 5 6 7 8 9 10
Cycle

w 0 1 0 1 1 0 1 1 1 0

z 0 0 0 0 0 1 0 0 1 1
We can see that in 6th clock cycle, input is 0 and output is 1, again in clock cycle 9, input is 1 and output is
also 1. Thus, the output is not depending on present input, rather they are depending on the past two
states. This type of machine is Moore Type Machine.
ii. Mealy Type Machines: The sequential circuits whose outputs depend on both the state and
the present primary inputs are of Mealy type. It has been named after George Mealy.
Example:
We can modify the example of Moore Machine in the following way:
We wish to design a circuit that meets the following specification:
1. The circuit has one input, w, and one output, z.
2. All changes in the circuit occur on the positive edge of a clock signal.
3. The output z is equal to 1 if during two immediate clock cycles the input w is equal to 1.
Otherwise, the value of z is equal to 0.
Thus, the system follows the following input output combination.

Clock 1 2 3 4 5 6 7 8 9 10
Cycle

w 0 1 0 1 1 0 1 1 1 0

z 0 0 0 0 1 0 0 1 1 0
We can see that for the output to be 1, the input must be 1 and the previous state must also be 1. Thus, it is
a Mealy machine.

■ Software requirements:
i) Cadence

Page | 95
■ Examples:
● Implement the Moore type machine of the example and verify:
The Moore type machine of the example can be represented by the following state diagram:

Figure 1: State Diagram of the above Moore type Machine

The initial state is S0. When the input is 0, the system remains in state S0 and output is 0. When
input is 1, at the next clock cycle, system moves to state S1 but the output still remains 0. If at the
next clock cycle, input is still 1, the system moves to state S2 and at the next clock cycle, output
turns 1. If the input is 0, the system returns to state S0. At state S2, the system remains in state S2
if input is 1 and the output continues to be 1. But if input is 0, system moves back to state S0 and
output turns 0 at next clock cycle.
Now, the Verilog code for this can be written as,

Page | 96
module moore(Clock, Resetn, w, z);

input Clock, Resetn, w;

output reg z;

reg [1:0] y;

parameter [1:0] S0 = 0, S1 = 1, S2 = 2;

always @(posedge Clock, negedge Resetn)

begin

if (Resetn == 0) y <= S0;

else

begin

z <= (y == S2);

case (y)

S0: if (w) y<= S1;

else y<= S0;

S1: if (w) y<= S2;

else y<= S0;

S2: if (w) y<= S2;

else y<= S0;

default: y<= 2'bxx;

Page | 97
endcase

end

end

//assign z = (y == S2);

endmodule

Check your designed FSM using a testbench in Cadence as explained in

experiment 6.

module moore_tb;
reg Clock, Resetn, w;
wire z;
moore dut(Clock, Resetn, w, z);
// Generate clock pulse
initial begin
Clock=0;
forever #5 Clock = ~Clock;
end

initial
begin
$shm_open("shm.db",1); // Opens a waveform
database
$shm_probe("AS"); // Saves all signals to database
#100 $finish;
#150 $shm_close(); // Closes the waveform database

Page | 98
end
// Test vector
initial
begin
w=0;Resetn=0; #17;
w=1; Resetn=1;#50;
w=0; #20;
end
endmodule

Implement the Mealy type machine of the example and verify:

The Mealy type machine of the example can be represented by the following state diagram:

Figure 2: State Diagram of the above Mealy type Machine

Initially the system is at state S0 and remains at S0 as long as input is 0. When input is 1, state
changes to S1 at next clock cycle. When at S1, if input is 1, output turns 1 at next clock cycle and
the system still remains in S1. If input is 0, the output turns 0 and state moves to S0 at next clock.
The Verilog code for this can be written as,

module mealy(z,w,clk,rst);
input clk, rst, w;
output reg z;
reg y;
parameter S0=0, S1=1;

Page | 99
always @(posedge clk, posedge rst)
if (rst==0) y<=S0;
else
case(y)
S0: if (w)
begin
z<=0;
y<=S1;
end
else
begin
z<=0;
y<=S0;
end
S1: if (w)
begin
z<=1;
y<=S1;
end
else
begin
z<=0;
y<=S0;
end
endcase
endmodule

Page | 100
Use the following testbench for functional verification of you
designed FSM
module mealy_tb;
reg Clock, Resetn, w;
wire z;
mealy dut(z,w,Clock,Resetn);

// Generate clock pulse

initial begin
Clock=0;
forever #5 Clock = ~Clock;
end

initial
begin
$shm_open("shm.db",1); // Opens a waveform
database
$shm_probe("AS"); // Saves all signals to database
#100 $finish;
#150 $shm_close(); // Closes the waveform
database
end

// Test vector
initial
begin
w=0;Resetn=0; #17;
w=1; Resetn=1;#50;
w=0; #20;

Page | 101
end
endmodule

● Implement the following finite state machine and verify:

Derive the state diagram for an FSM that has an input w and an output z. The machine has to generate
z = 1 when the previous four values of w were 1001 or 1111; otherwise, z = 0. Overlapping input
patterns are allowed. An example of the desired behavior is,

w: 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1
z: 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1

State Diagram:

Figure 3: State Diagram of the above Machine

Page | 102
The Verilog code for this can be written as,

module example1 (Clock, Resetn, w, z);

input Clock, Resetn, w;
output z;
reg [2:0] y;
parameter [2:0] S0 = 0, S1 = 1, S2 = 2, S3=3, S4=4, S5=5, S6=6, S7=7;
always @(posedge Clock, negedge Resetn)
begin
if (Resetn == 0) y <= S0;
else
begin
case (y)
S0: if (w) y<=S1;
else y<=S0;
S1: if (w) y<=S2;
else y<=S5;
S2: if (w) y<=S3;
else y<=S5;
S3: if (w) y<=S4;
else y<=S5;
S4: if (w) y<=S4;
else y<=S5;
S5: if (w) y<=S1;
else y<=S6;
S6: if (w) y<=S7;
else y<=S0;
S7: if (w) y<=S2;

Page | 103
else y<=S5;
endcase
end
end
assign z=(y==S4)|(y==S7);
endmodule

module example_tb;
reg Clock, Resetn, w;
wire z;
example1 dut(Clock,Resetn,w,z);

// Generate clock pulse

initial begin
Clock=0;
forever #5 Clock = ~Clock;
end

initial
begin
$shm_open("shm.db",1); // Opens a waveform database
$shm_probe("AS"); // Saves all signals to database
#100 $finish;
#150 $shm_close(); // Closes the waveform database
end

// Test vector
initial
begin

Page | 104
//0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1
w=0;Resetn=0; #7;
w=1; Resetn=1;#10;
w=0; #10;
w=1; #40;
w=0; #20;
w=1; #20;
w=0; #20;
w=1; #50;

end
endmodule

■ Simulation Results:
● Take screenshot of the outputs.
■ Report Task:
1. Derive a state diagram for an FSM that has an input w and an output z. The machine has to
generate z = 1 when the previous four values of w were 1010 or 1011; otherwise, z = 0.
Overlapping input patterns are allowed.
a. Show the state diagram.
b. Implement the FSM using verilog HDL.
c. Verify your design using testbench (Hint: Select your input patterns in such a way so
that it covers both sequences. You can refer to page 95 to get an idea on selecting the
input patterns to cover both sequences)
2. A sequential circuit has two inputs, w1 and w2, and an output, z. Its function is to compare the
input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles, the
circuit produces z = 1; otherwise, z = 0. For example
w1: 0110111000110
w2: 1110101000111
z: 0000100001110
3. An FSM is defined by the state-assigned table in Figure:

Page | 105
Present State Next State Output
(z)
Input (w=0) Input (w=1)

S0 S2 S3 0

S1 S1 S0 0

S2 S3 S0 0

S3 S1 S1 1

Draw the state diagram and implement the system using Verilog code.

■ Comments/Discussion:
● Comment on the obtained results and discrepancies (if any).

Page | 106
Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 8

○ RTL Synthesis of a Digital Subsystem using Cadence

Genus.

■ Objective:
i) Performing RTL synthesis of the designed FSM using the Cadence Genus (TM) Synthesis Solution
tool.

■ Theoretical Background:
In digital circuit design, Register-Transfer Level (RTL) is a design abstraction which models a synchronous
digital circuit in terms of the flow of digital signals (data) between hardware registers, and the logical
operations performed on those signals. RTL Logic synthesis is a process by which an abstract form of
desired circuit behavior, typically at Register Transfer Level (RTL), is turned into a design implementation in
terms of logic gates, typically by a computer program called a synthesis tool.
Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by
the designer. In simple language, Synthesis is a process that converts the abstract form of design to a
properly implemented chip in terms of logic gates.
Synthesis takes place in multiple steps:
● Converting RTL into simple logic gates.
● Mapping those gates to actual technology-dependent logic gates available in the technology
libraries.
● Optimizing the mapped netlist keeping the constraints set by the designer intact.

Common Terminologies:
● TCL script: Automates the synthesis process
● Liberty Files: Liberty File are IEEE standard for defining PVT Characterization, Relating
Input and Output Characteristics, Timing, Power, Noise

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● Constraint file: Indicates different constraints like clock skew, off-chip delays under which the
system is to be tested.
● DFT: Design for Testability. Checks whether the chip designed according the constraints

■ Software requirements:
i) Cadence

■ Examples:
1. Right click on your working directory and open the terminal. First, we need to make a few
directories and sub-directories using the mkdir command. Make a folder named exp7. Inside this
folder make sub-folders named rtl, synthesis, simulation, constraint and lib.

2. Now copy and paste your Verilog file you used in experiment 6 for counter to the rtl directory.

module counter(rst,clk,q);
input rst,clk;
output reg[3:0]q;
always @(posedge clk, posedge rst)
begin
if (rst)
q<=0;
else
q<=q+1;
end
endmodule
3. Copy the fast.lib and slow.lib files using the following commands to lib directory

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4. Copy the rc_script.tcl file from the source using the following commands to the synthesis folder

5. Copy the constraint file from the source using the following commands to the constraint folder

6. Now go to the synthesis folder and open the tcl file. Change the file names accordingly in lines
4,8,9. In lines 1,2 and 6 specify the locations of library, Verilog file and constraint file respectively.

7. Now open the constraint file and add the information about the input output and clock ports. If there
is no clock (e.g. a combinational circuit) keep the clock ports as it is.

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8. Now write the following commands as we have done previously. Before that move to the synthesis
folder where the tcl file is stored.

9. A netlist file and sdc will be generated in the synthesis folder. We will use these during layout
design.
10. Now write the command gui_show which will invoke a window.
11. Right click on the file name and select schematic view > Main

12. You will see the schematic view of your design

13. Click on Power>report>Detailed report

14. Now click on DFT -> Violations to observe whether the timing requirements have been met

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15. Explore other reports generated by the Cadence Genus
16. Repeat the same process for the slow.lib and observe the power and violations report.

■ Simulation Results:
● Take screenshot of the outputs.

■ Report Task:
Text:
1. Text
■ Comments/Discussion:
Comment on the obtained results and discrepancies (if any).

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Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Experiment No. 9

○ Physical Design from HDL using Cadence Innovus

■ Objective:
i) Familiarize the students with physical layout design from HDL in Cadence.

■ Theoretical Background:
In integrated circuit design, physical design is a step in the standard design cycle which follows after
the circuit design. At this step, circuit representations of the components (devices and interconnects) of
the design are converted into geometric representations of shapes which, when manufactured in the
corresponding layers of materials, will ensure the required functioning of the components. This
geometric representation is called integrated circuit layout. This step is usually split into several
sub-steps, which include both design and verification and validation of the layout.
Modern day Integrated Circuit (IC) design is split up into Front-end design using HDLs, functional
Verification, and Back-end Design or Physical Design and verification. The next step after Physical
Design is the Manufacturing process or Fabrication Process that is done in the Wafer Fabrication
Houses. Fab-houses fabricate designs onto silicon dies which are then packaged into ICs
Each of the phases mentioned above has Design Flows associated with them. These Design Flows lay
down the process and guide-lines/framework for that phase. Physical Design flow uses the technology
libraries that are provided by the fabrication houses. These technology files provide information
regarding the type of Silicon wafer used, the standard-cells used, the layout rules (like DRC in VLSI),
etc. In the two previous experiment we have designed the logic of an Accumulator, we have done its
functional simulation and synthesized the netlist. All of these are related to Front-end design. In this
experiment we are going to start Physical design (Back-end) of our synthesized accumulator netlist

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step-by-step as mentioned in the above flow diagram. Cadence Innovus Implementation System will be
used for that purpose.
■ Software requirements:
i) Cadence
■ Examples:

● Procedure:
1. Create a new folder named exp 8 and copy the netlist file, fast.lib, slow.lib, sdc
file and tech45.lef file to the folder.
2. Create a new file named Default.view and paste the code provided at the
appendix section of the lab manual. Add the name of your sdc file as shown
below

3. Now open a terminal from the folder exp8 and write the following commands.

4. A window will pop up. Click on File → import design.

5. In the import design window click on the following browsing button

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Then a new window will pop up. Click on the following setting to expand the window.

Now browse to the netlist filed that you had just copied, then click on ADD and Close

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6. Now check the following settings and browse to specify the lef file.

Now select the desired lef file as we had done for the netlist file and press close button.

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7. Now name the power and ground nets to VDD and VSS respectively and click on
Create analysis configuration and a window will appear.
8. Now click on the browsing window in MMMC view definition file and select the file
you have created.

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Please note that there is a mismatch between the netlist file names in
different figures. You need to select the name you have used.
Now press Save and Ok.
You can construct your own custom view file following the steps in 9-16.
9. Right click on library sets and click new.

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A new window will appear and select the location of the slow.lib liberty file as we had done for
the netlist and the lef file.

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now press close.
In the add library set window press apply and the ok to add the slow.lib as your first PVT
condition.

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10. Now do the same to add the fast.lib as the second PVT condition under the name
of min_timing.

Now your MMMC window will look like the following

11. Now right click on the delay corners tab and click on new. in the new window
make the following changes and click ok.

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12. Do the same for the min_delay case

Now the MMMC window should look like this

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13. Now right click on the constraints mode tab and select new. Under the name
top browse for you sdc file.
14. Right click on analysis views, select new and make the following changes

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repeat the same for the following

15. Now right click on hold time analysis and make the following changes

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16. For setup time analysis choose setup as the analysis view. Finally your MMMC
window will look like the following.

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Now press save & close.
17. After again pressing ok you will see a window like the following

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the one with the polygon is the VDD
row and the other is the VSS line.

18. Floorplanning: Floorplanning is the area budgeting of the chip. We can specify
floorplan in two ways
a) By specifying Aspect ratio and core utilization ratio
b) By explicitly specifying the width and height of the die/core
In this step we will specify floorplan information and add IO ports.
Go to Floorplan → specify floorplan and a window will pop up. Make the following
changes and press ok.

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Your design window will look like the following. Keep in mind that the distances
here are in microns

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19. Now save your design by selecting Save design and make the following changes

20. Power Mesh: Go to power→ power planning → add ring and make the following
changes and press update.

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Then press apply and ok.
Here H and V means horizontal and vertical lines
Now the design window will look like this

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21. Now go to power→ power planning → add stripes

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Similarly you can add vertical stripes as well.

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The design window should look like this

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22. Go to route → special route. In the window make the following changes

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This will add the metal layers by via .
The design window will look like this

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23. Placement: Go to Place → Place standard cells and make the following changes

in the physical view you can observe the following view

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24. Now go to timing → report timing and the following window will appear

Press ok and you can see the timing report in the terminal. If any violations exist,
use optimization to remove them.

For that go to ECO → Optimize design and the following window will appear.
Press ok
Similarly the hold time violations can be checked as well.

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25. Now go to Route → Nanoroute → route and click ok on the default settings. You
can find the DRC violations (if any) in the terminal window.

26. Now go to verify → Verify connectivity and click ok. Any violations can be looked
up on the terminal. If everything is fine you will get a message like this

27. Now go to verify → verify geometry and click ok.

28. if you see any violations you can see those in the tools → violation browser.
Good luck with debugging those !!

Congratulations!! You have successfully finished your VLSI sessional. Now you can now design
your own chips through Verilog HDL and your layout design can be fabricated in foundries.

Best of luck with the project.

■ Simulation Results:
● Take screenshot of the outputs.
■ Report Task:
Text:
1. Text
■ Comments/Discussion:
● Comment on the obtained results and discrepancies (if any).

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Brac University
Department of Electrical & Electronic Engineering (EEE)
EEE/ECE 412 (V1, V2) / EEE/ECE 411L (V3)
VLSI Design Laboratory

● Sample Project

○ Title: Design of a Digital Alarm Clock

■ Project Description:
The clock should show the hours, minutes and seconds and update them according to the timestep in a
practical clock. Apart from that, the clock should have the following features:
● Reset: The clock should take a reset bit and reset_min and reset_hour as input. When the
clock receives a high pulse in the reset bit, the time output of the clock should be
a) Second output=0
b) Minute Output=reset_min
c) Hour Output=reset_hour
● Alarm: The clock takes as input alarm_min and alarm_hour. If the output minute and hour
of the clock are equal to the inputs alarm_min and alarm_hour respectively the output flag
‘alarm’ should be set to 1 for 1 minute. After that, the minute output is no longer equal to
the alarm_min and the alarm flag should be set to zero.

■ Tasks:
For completing your project, you need to do the following tasks-
a) Write the Verilog code of your designed alarm clock
b) Observe the output waveform of the clock using testbench in Cadence software
c) Do RTL synthesis in Cadence
d) Design the layout of the clock in Cadence

Deliverables:

1. Detailed Project Report

2. Project Presentation Slide

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Project Report:

Report must contain the following:

1. Cover Page (sample at page 6)

2. Objective (You should write Problem Statement here)

3. Introduction (You should define the basic terminologies related to your project etc.)

4. Software Requirements

5. Working Procedure (How you went through with the design)

6. Verilog Code, Testbench

7. Timing Diagram

RTL synthesis and reports of RTL synthesis

8. Result and Observation (Here you will validate your works by explaining the timing diagram. The
timing diagram should contain all the requirements)

9. Discussion (Any issues with your design or what you’ve learnt doing the project)

Grading Criteria:

1. Completion of all Specifications

2. Efficiency of Code

3. Quality of Report

4. Quality of Presentation

5. Peer Evaluation (How your own groupmates rate your contribution) (out of 5)

6. Viva

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● Appendix:
Working with Altera Quartus:
1. Open Quartus.
2. Click File->New Project Wizard->Next
3. Fill out the following:
What is the working directory for this project? – Browse->Create a folder in desktop->Select the folder
What is the name of the project->Type a name and remember it (Say “expt1”). Same name is going to
be copied to the next box automatically.
Press next.
4. Press next
5. Select Device Family: FLEX10KE and press next.
6. Fill out the following in all three pair of boxes:
Tool name: Custom
Format: Verilog HDL
Press Next->Finish
7. File->New->Verilog HDL File->OK
8. Write the code and save it with the same name as that given in expt1 3 with extension of .v
(Example: expt1.v)
9. File->New->Vector Waveform File
10. Right click on Name->Insert->Insert Node or BUS
11. Click Node Finder.
Filter: Pins: all
Look in: Filename (Example expt1.v)
Click list->Click “>>” -> OK -> OK
12. Right click on each input->Value->Clock and set up the clocks.
13. Save with the same filename as the .v file (Example: expt1.vwf)
14. Assignment->Settings->Simulator Settings
Simulation Mode: Functional
Click OK.
15. Processing-> Generate Functional Simulation Netlist
16. Processing-> Start Simulation

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Lef File
https://drive.google.com/file/d/1kR7NgR18Fw3_yHbUf4Cc1o_cTKZzlM_X/view?usp=sharing

Default.view

# Version:1.0 MMMC View Definition File

# Do Not Remove Above Line
create_library_set -name max_timing -timing {slow.lib}
create_library_set -name min_timing -timing {fast.lib}
create_constraint_mode -name top -sdc_files {Alarm_C_sdc.sdc}
create_delay_corner -name max_delay -library_set {max_timing}
create_delay_corner -name min_delay -library_set {min_timing}
create_analysis_view -name setup -constraint_mode {top} -delay_corner {max_delay}
create_analysis_view -name hold -constraint_mode {top} -delay_corner {min_delay}
set_analysis_view -setup {setup} -hold {hold}

counter_netlist.v

// Generated by Cadence Genus(TM) Synthesis Solution 17.14-s037_1

// Generated on: Nov 29 2022 11:54:10 BDT (Nov 29 2022 05:54:10 UTC)

// Verification Directory fv/upcounter

module upcounter(rst, clk, q);

input rst, clk;
output [3:0] q;
wire rst, clk;
wire [3:0] q;
wire n_0, n_1, n_2, n_3, n_4, n_5;
SDFFRHQX1 \q_reg[3] (.RN (n_5), .CK (clk), .D (n_1), .SI (q[3]), .SE
(n_4), .Q (q[3]));
SDFFRHQX1 \q_reg[2] (.RN (n_5), .CK (clk), .D (n_0), .SI (q[2]), .SE
(n_3), .Q (q[2]));
SDFFRHQX1 \q_reg[1] (.RN (n_5), .CK (clk), .D (q[0]), .SI (n_2), .SE
(q[1]), .Q (q[1]));
NAND2BX1 g67(.AN (n_3), .B (q[2]), .Y (n_4));
DFFRHQX1 \q_reg[0] (.RN (n_5), .CK (clk), .D (n_2), .Q (q[0]));
NAND2X1 g69(.A (q[0]), .B (q[1]), .Y (n_3));
INVXL g72(.A (q[3]), .Y (n_1));
INVXL g71(.A (q[0]), .Y (n_2));
INVXL g70(.A (q[2]), .Y (n_0));
INVXL g73(.A (rst), .Y (n_5));
endmodule

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