slg59h1013v Datasheet
slg59h1013v Datasheet
SLG59H1013V
copper pillar interconnects, the SLG59H1013V package also GND 3 14 SEL
exhibits a low thermal resistance for high-current operation.
VIN 4 13 VOUT
Designed to operate over a -40 °C to 125 °C range, the
SLG59H1013V is available in a low thermal resistance, VIN 5 12 VOUT
RoHS-compliant, 1.6 x 3.0 mm STQFN package. VIN 6 11 VOUT
CIN= C1 + C2 + C3 C5 C6
47 µF 22 µF
C1 C2 C3 Charge
47 µF 22 µF 0.1 µF Pump 3 V FS - Connect
IOUT to System ADC
CAP Linear Ramp Control
RIOUT CIOUT
CSLEW
RSET 84.5 kΩ 180 pF
10 nF
VLOGIC RSET
State Machine VLOGIC
30.1 kΩ
RPU (CL/SC Detection and
10 kΩ SEL Over Temperature RPU
27 V OVLO Protection) 100 kΩ
24 V VIN 20.5 V UVLO
Lockout Selected Connect to
ON ON
CMOS Input
FAULT System GPI
Discharge
OFF
GND
Pin Description
Pin # Pin Name Type Pin Description
A low-to-high transition on this pin initiates the operation of the SLG59H1013V’s state machine.
ON is an asserted HIGH, level-sensitive CMOS input with ON_VIL < 0.3 V and ON_VIH > 0.9 V. As
1 ON Input the ON pin input circuit does not have an internal pull-down resistor, connect this pin to a
general-purpose output (GPO) of a microcontroller, an application processor, or a system controller,
do not allow this pin to be open-circuited.
2 GND GND Pin 2 is a low-current GND terminal for the SLG59H1013V. Connect directly to Pin 3.
Pin 3 is the main ground connection for the SLG59H1013V’s internal charge pump, its gate driver
3 GND GND and current-limit circuits as well as its internal state machine. Therefore, use a short, stout
connection from Pin 3 to the system’s analog or power plane.
VIN supplies the power for the operation of the SLG59H1013V, its internal control circuitry, and the
drain terminal of the nFET load switch. With 5 pins fused together at VIN, connect a 47 μF (or
4-8 VIN MOSFET
larger) low-ESR capacitor from this pin to ground. Capacitors used at VIN should be rated at 50 V
or higher.
Source terminal of n-channel MOSFET (5 pins fused for VOUT). Connect a 47 μF (or larger)
9-13 VOUT MOSFET low-ESR capacitor from this pin to ground. Capacitors used at VOUT should be rated at 50 V or
higher.
As a low logic-level CMOS input with SEL_VIL < 0.3 V and SEL_VIH > 1.65 V, SEL selects one of
two undervoltage/overvoltage lockout windows. When SEL = LOW, the VIN
14 SEL Input undervoltage/overvoltage lockout window is set for 12 V ±10% applications. When SEL = HIGH,
the VIN undervoltage/overvoltage lockout window is set for 24 V ± 5% applications. See the
Electrical Characteristics table for additional information.
An open drain output, FAULT is asserted within TFAULTLOW when a VIN undervoltage, VIN
overvoltage, a current-limit, or an over-temperature condition is detected. FAULT is deasserted
15 FAULT Output
within TFAULTHIGH when the fault condition is removed. Connect an 100 kΩ external resistor from
the FAULT pin to local system logic supply.
A low-ESR, stable dielectric, ceramic surface-mount capacitor connected from CAP pin to GND
sets the VOUT slew rate and overall turn-on time of the SLG59H1013V. For best performance, the
16 CAP Output range for CSLEW values are 10 nF ≤ CSLEW ≤ 20 nF – please see typical characteristics for additional
information. Capacitors used at the CAP pin should be rated at 10 V or higher. Please consult
Applications Section on how to select CSLEW based on VOUT slew rate and loading conditions.
IOUT is the SLG59H1013V’s power MOSFET load current monitor output. As an analog current
output, this signal when applied to a ground-reference resistor generates a voltage proportional to
the current through the n-channel MOSFET. The IOUT transfer characteristic is typically 10 μA/A
17 IOUT Output
with a voltage compliance range of 0.5 V ≤ VIOUT ≤ 4 V. Optimal IOUT linearity is exhibited for
0.5 A ≤ IDS ≤ 3.5 A. In addition, it is recommended to bypass the IOUT pin to GND with a 0.18 nF
capacitor.
A 1%-tolerance, metal-film resistor between 23.7 kΩ and 91 kΩ sets the SLG59H1013V’s active
18 RSET Input current limit. A 91 kΩ resistor sets the SLG59H1013V’s active current limit to 1 A and a 23.7 kΩ
resistor sets the active current limit to 4 A.
Ordering Information
Part Number Type Production Flow
SLG59H1013V STQFN 18L FC Industrial, -40 °C to 125 °C
SLG59H1013VTR STQFN 18L FC (Tape and Reel) Industrial, -40 °C to 125 °C
Electrical Characteristics
12 V ≤ VIN ≤ 24 V; CIN = 47 µF, TA = -40 °C to 125 °C, unless otherwise noted. Typical values are at TA = 25 °C
ON*
50% ON 50% ON
TOFF_Delay
VOUT TON_Delay
TTotal_ON
HIGH
VIN
LOW
Time
ON
TRISE
HIGH 90%
TON_Delay
VOUT
10%
Abnormal Step Load
Current Event
IACL IACL
HIGH
VIN
LOW
Time
IDS
ISCL ISCL
Timing Diagram - Basic Operation including Active Current + Internal FET SOA Protection
HIGH
VIN
LOW
Time
ON
10%
Abnormal Step Load Active Current Limit
Operation
Current Event
IACL IACL
SOA
Protection
IDS
ISCL ISCL
0.2s
Figure 2. Typical Turn ON operation waveform for VIN = 12 V, CSLEW = 10 nF, CLOAD = 10 μF, RLOAD = 100 Ω
Figure 3. Typical Turn ON operation waveform for VIN = 12 V, CSLEW = 18 nF, CLOAD = 10 μF, RLOAD = 100 Ω
Figure 4. Typical Turn ON operation waveform for VIN = 24 V, CSLEW = 10 nF, CLOAD = 10 μF, RLOAD = 100 Ω
Figure 5. Typical Turn ON operation waveform for VIN = 24 V, CSLEW = 18 nF, CLOAD = 10 μF, RLOAD = 100 Ω
Figure 6. Typical Turn OFF operation waveform for VIN = 12 V, CSLEW = 10 nF, no CLOAD , RLOAD = 100 Ω
Figure 7. Typical Turn OFF operation waveform for VIN = 12V, CSLEW = 10 nF, CLOAD = 10 μF, RLOAD = 100 Ω
Figure 8. Typical Turn OFF operation waveform for VIN = 24 V, CSLEW = 10 nF, no CLOAD , RLOAD = 100 Ω
Figure 9. Typical Turn OFF operation waveform for VIN = 24 V, CSLEW = 10 nF, CLOAD = 10 μF, RLOAD = 100 Ω
Figure 10. Typical ACL operation waveform for VIN = 12 V, CLOAD = 10 μF, IACL = 1 A, RSET = 91 kΩ
Figure 11. Thermally induced SOA shutdown for VIN = 24 V, CLOAD = 10 μF, IACL = 1 A, RSET = 91 kΩ
Figure 12. Typical FAULT assertion waveform for VIN = 24 V, CLOAD = 10 μF, IACL = 1 A, RSET = 91 kΩ, switch on 18.5 Ω load
Figure 13. Typical FAULT de-assertion waveform for VIN = 24 V, CLOAD = 10 μF, IACL = 1 A,
RSET = 91 kΩ, switch out 18.5 Ω load
Applications Information
Renesas’s High Voltage GreenFET load switches incorporate a number of internal protection features that prevents them from
damaging themselves or any other circuit or subcircuit downstream of them. One particular protection feature is their Safe
Operation Area (SOA) protection. SOA protection is automatically activated under overpower and, in some cases, under
overcurrent conditions. Overpower SOA is activated if package power dissipation exceeds an internal 5 W threshold longer than
2.5 ms. High Voltage GreenFET devices will quickly switch off (open circuit) upon overpower detection and automatically resume
(close) nominal operation once overpower condition no longer exists.
One possible way to have an overpower condition trigger SOA protection is when High Voltage GreenFET products are enabled
into heavy output resistive loads and/or into large load capacitors. It is under these conditions to follow carefully the “Safe Start-up
Loading” guidance in the Applications section of the datasheet. During an overcurrent condition, High Voltage GreenFET devices
will try to limit the output current to the level set by the external RSET resistor. Limiting the output current, however, causes an
increased voltage drop across the FET’s channel because the FET’s RDSON increased as well. Since the FET’s RDSON is larger,
package power dissipation also increases. If the resultant increase in package power dissipation is higher/equal than 5 W for
longer than 2.5 ms, internal SOA protection will be triggered and the FET will open circuit (switch off). Every time SOA protection
is triggered, all High Voltage GreenFET devices will automatically attempt to resume nominal operation after 160 ms.
SLG59H1013V has built-in protection to prevent over-heating during start-up into a heavy load. Overloading the VOUT pin with
a capacitor and a resistor may result in non-monotonic VOUT ramping. In general, under light loading on VOUT, VOUT ramping
can be controlled with CSLEW value. The following equation serves as a guide:
TRISE 20
CSLEW = x 4.9 µA x
VIN 3
where
TRISE = Total rise time from 10% VOUT to 90% VOUT
VIN = Input Voltage
CSLEW = Capacitor value for CAP pin
When capacitor and resistor loading on VOUT during start up, the following tables will ensure VOUT ramping is monotonic without
triggering internal protection:
Note 3: Active Current Limit accuracy is ±15% over voltage range and over temperature range.
To configure the SLG59H1013V for conditioned 12 V ±10% VIN applications is simply a matter of connecting the SEL pin to GND
as shown in Figure A. For other VIN lockout window applications, please consult Renesas for additional information.
Figure A.
12 V ±10%
3A VOUT CLOAD= C5 + C6
VIN
CIN= C1 + C2 + C3 C5 C6
47µF 22µF
C1 C2 C3 Charge
47 µF 22µF 0.1 µF
Pump 3 V FS - Connect
IOUT to System ADC
CAP Linear Ramp Control
RIOUT CIOUT
CSLEW 180 pF
RSET 84.5 kΩ
10 nF
RSET
State Machine VLOGIC
30.1 kΩ
(CL/SC Detection and
SEL
Over Temperature RPU
13.7V OVLO Protection) 100 kΩ
12 V VIN 10.2V UVLO
Lockout Selected
ON ON Connect to
CMOS Input Discharge FAULT System GPI
OFF
GND
Shown in Figure B and Figure C are the two sets of VIN overvoltage/undervoltage lockout windows – one for conditioned
24 V ±5% VIN systems and the second for conditioned 12 V ±10% VIN systems. To avoid lockout threshold collision with nominal
operation, the SLG59H1013V’s VIN(OVLO) min and VIN(UVLO) max thresholds were set 0.1 V correspondingly higher than the
system’s nominal VIN max or lower than the system’s VIN min range.
Figure B.
Figure C.
Power Dissipation
The junction temperature of the SLG59H1013V depends on different factors such as board layout, ambient temperature, and
other environmental factors. The primary contributor to the increase in the junction temperature of the SLG59H1013V is the power
dissipation of its power MOSFET. Its power dissipation and the junction temperature in nominal operating mode can be calculated
using the following equations:
PD = RDSON x IDS2
where:
TJ = PD x θJA + TA
where:
TJ = Junction temperature, in Celsius degrees (°C)
θJA = Package thermal resistance, in Celsius degrees per Watt (°C/W)
TA = Ambient temperature, in Celsius degrees (°C)
PD = (VIN-VOUT) x IACL or
PD = (VIN – (RLOAD x IACL)) x IACL
where:
PD = Power dissipation, in Watts (W)
VIN = Input Voltage, in Volts (V)
RLOAD = Load Resistance, in Ohms (Ω)
IACL = Output limited current, in Amps (A)
VOUT = RLOAD x IACL
Layout Guidelines:
1. Since the VIN and VOUT pins dissipate most of the heat generated during high-load current operation, it is highly recommended
to make power traces as short, direct, and wide as possible. A good practice is to make power traces with absolute minimum
widths of 15 mils (0.381 mm) per Ampere. A representative layout, shown in Figure 14, illustrates proper techniques for heat
to transfer as efficiently as possible out of the device;
2. To minimize the effects of parasitic trace inductance on normal operation, it is recommended to connect input CIN and output
CLOAD low-ESR capacitors as close as possible to the SLG59H1013V's VIN and VOUT pins;
3. The GND pin should be connected to system analog or power ground plane.
А High Voltage GreenFET Evaluation Board for SLG59H1013V is designed according to the statements above and is illustrated
on Figure 14. Please note that evaluation board has D_Sense and S_Sense pads. They cannot carry high currents and dedicated
only for RDSON evaluation.
ON SEL0 SEL1
GND GND GND
R6
1
2
3
1
2
3
1
2
3
1
5V1
VLOGIC IOUT/POUT PDS/CAP FAULT#
1
R5
10k
R3 C4 R4 R2 R1 C3
VLOGIC circuit 30.1k 10nF N.P. 100k 84.5k 180pF
U1
18
RSET 17
1 IOUT 16
2 ON CAP 15
3 GND FAULT 14
4 GND SEL 13
5 VIN VOUT 12 CAP Array
6 VIN VOUT 11
C1 C5 VIN VOUT
C2 C6 1 2
47uF 22u F 7 10 4 7uF 22uF
8 VIN VOUT 9 3 4
VIN VOUT 5 6
7 8
9 10
1
1
2
3
4
1
2
3
4
1
2
3
4
5 6
7 8
GND D/VIN GND S/VOUT 9 10
EVB Configuration
Pin 1 Identifier
ARR Assembly + Rev. Code
Note 1: Each character in code field can be alphanumeric A-Z and 0-9
Note 2: Character in code field can be alphabetic A-Z
Nominal Max Units Reel & Leader (min) Trailer (min) Tape Part
Package # of
Package Size Hub Size Length Length Width Pitch
Type Pins per Reel per Box Pockets Pockets
[mm] [mm] [mm] [mm] [mm] [mm]
STQFN
18L
1.6x3mm 18 1.6 x 3 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4
0.4P FC
Green
Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.64 mm3 (nominal). More
information can be found at www.jedec.org.
Revision History
Date Version Change
Updated Company name and logo
2/2/2022 1.04 Added SOA Protection Threshold to Features
Fixed typos
Updated EC Table
7/22/2021 1.03
Updated EVB figure
Updated style and formatting
Updated Charts
12/12/2018 1.02 Updated Scopeshots
Added Layout Guidelines
Fixed typos
Updated VIN Max and VIN(OVLO) Min
11/2/2017 1.01
Fixed typos and formatting
5/13/2016 1.00 Production Release
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