COURSE INSTRUCTORS ABOUT

A SHORT COURSE
IIT BHUBANESWAR
STEVE HOOVER
CANTIC
ON
Next-Generation
YOGA
Steve Hoover is the founder of Redwood
EDA, a Massachusetts startup specializing
in emerging digital logic modeling tools
and methodology. He brings with him into
Studio
Semiconductors: RISC-V, AI,
and TL-Verilog
this role a deep understanding of the
complexities of high-performance IC
Certified Yoga Workout Class
design, having contributed to multiple MOE&Scheme
Indoor Outdoor on
Studio
generations of Alpha microprocessors at
DEC and Compaq as well as Itanium and Global Initiative on Academic Network
Xeon server projects and Omni-Path HPC
network switch microarchitecture for Intel.

DR. SRINIVAS BOPPU

Dr. Srinivas Boppu is an Assistant Professor in the School of Indian Institute of Technology Bhubaneswar is established by
Electrical and Computer Sciences, IIT Bhubaneswar. His the Government of India in 2008 under The Institutes of
research interests include high-level synthesis, design of Technology Act 1961 with amendments up to 2012. IIT 09-DEC-2024 to 20-DEC-2024
programmable hardware accelerators, and design automation Bhubaneswar became an institute of national importance
for integrated circuits. from 29th June 2012 with notification of amendment in the
Institutes of Technology Act, 1961, by the Ministry of
Education, (Department of Higher Education) Government of
India published in the Gazette of India dated 2nd July 2012.

With a vision to attain global recognition through exceptional

graduates and innovative research, IIT Bhubaneswar fosters
a learning community that promotes interdisciplinary
collaboration and encourages creativity, cognitive thinking,
and entrepreneurship. The mission of the Institute includes
DR. AYAN PALCHAUDHURI nurturing a learning community based on mutual respect,
interdisciplinary collaboration, innovation, flexible curricula,
Dr. Ayan Palchaudhuri is an Assistant Professor in the School and strong industry-academia partnerships.
of Electrical and Computer Sciences at IIT Bhubaneswar. His SPONSORS
research interests include VLSI architecture design for high
performance computer arithmetic applications.
CONTACT
0091-674-7135752
Design Integrate Fabricate Test
[email protected] / [email protected]

School of Electrical and Computer Sciences,

IIT Bhubaneswar, Odisha, India- 752050
OVERVIEW COURSE DETAILS REGISTRATION DETAILS
This course provides hands-on experience with next- Module 1, Days 1-2: Digital Logic and CPUs REGISTRATION FEE
CATEGORY
CANTIC
generation design methodology and tools, RISC-V CPU design, Introduction to Digital Logic (including GST)
and the semiconductor fabrication process. By participating, Topics: Digital logic; sequential logic; pipelined logic; Tiny
you will learn how large design teams work together to Next-Generation1180
Research Scholars/ PG / UG (3rd year
accomplish one of mankind's most remarkable
tapeout; FPGAs; TL-Verilog
Online tools: Nand Game; Wokwi; Makerchip IDE;
onwards) Students YOGA
accomplishments—turning sand into microchips with billions
of transistors and teraflops of computing power. You will learn
Compiler Explorer Semiconductors: RISC-V,
Faculty/Researchers from
Academic/ Research Institutions
1180 AI,
Labs: logic gates; counter circuit; Fibonacci series circuit;
to use advanced design tools and methodologies powered by
the open-source community before they are broadly adopted calculator circuit andandTL-Verilog
Engineers from Industry R&D 2360
by the industry. You will learn RISC-V by building your own CPUs Organizations
RISC-V CPU core! Topics: compilers; assembly language
After learning these skills and technologies, including Online tools: Compiler Explorer You can pay directly to the following account or use a QR code
Transaction-Level Verilog, the Makerchip IDE, and the Open Labs: compilation; CPU operation for UPI payments. Once paid, please register yourself using the
Lane flow, you will be able to use them in an open-ended final Module 2 (Days 3-5): Building a RISC-V CPU following link.
project. Winning projects will be fabricated on the Skywater Digital Logic
130 nm process using Tiny Tapeout on Efabless's Chip Ignite https://forms.gle/9zyBNMPo6EPtWsnS8
Topics: Review of Module 1, Logic retiming, validity and
multi-project wafer shuttle!
clock gating
To suit participants from different backgrounds, the course is
Online tools: Makerchip IDE Account Holder Name CEP, IIT BHUBANESWAR
delivered in four modules, and participants may register for CANTIC
Labs: combinational circuit, pipeline, calculator with
any or all modules based on interest and experience. See YOGA
memory for Tiny Tapeout Account No 24282010001960
details on the registration page. Next-Generation
RISC-V Semiconductors: RISC-V, AI,
Studio
Canara Bank,
WHO CAN ATTEND ? Topics: RISC-V ISA, application binary interface (ABI), Bank & Branch
and TL-Verilog
IIT Bhubaneswar,Argul Branch
CPUs
This course can be attended by both UG, PG students and
Online tools: Compiler Explorer, WARP-V IFSC Code CNRB0017282
research scholars who want to explore hardware design
irrespective of their stream. It will also be helpful for faculty Labs: assembling/disassembling;
programming/compilation, CPU simulation MICR Code 752015014
from academia and professionals from industry and R&D
organizations. For outside participants, accomodation is Building a Single-Cycle RISC-V CPU
available on payment basis. Topics: caches and memories, CPU components SCAN ME
Labs: next PC logic, fetch logic, decode logic, register
PREREQUISITES read/ write, ALU
Pipelining the CPU
We welcome participants with diverse backgrounds, as no
prior experience with hardware is necessary to excel in this Topics: waterfall diagrams, hazards
course. All lab exercises use online tools. Participants MUST Labs: simple pipelined CPU, register file bypass, branch
bring their own laptops every day. redirect
Completing the CPU
TINY TAPEOUT Labs: all instructions, loads/stores, jumps
Module 3 (Day 6): Semiconductor Industry Design Practices
Design Team Roles
Topics: Roles, pre-silicon verification, post-silicon
verification
EDA Tools
Topics: Open Lane flow, logic synthesis, place &route, etc.
Future Methodologies ACCOMODATION
Topics: hardware description languages, transaction-level
Outstation participants can stay in our campus hostels on
design/verification, AI in EDA
payment basis. If you need an accommodation, please fill
Module 4 (Days 7-10): Open Projects
out the form given in the link below.
Selected projects will be
DATE OF EXAM: DEC 20, 2024 fabricated using Tiny Tapeout https://forms.gle/fJAYA1syYmDpaBFn9