Architectural Features of

16F873 PIC Microcontroller

Chapter - II

ARCHITECTURAL FEATURES OF 16F873 PIC

MICRO CONTROLLER

2.1 INTRODUCTION

New science called for new scientists. White collars took the place of blue
collars and there came the people who could "understand the electronics". And
while the world stared in awe, the conspirators split up in two factions: those
who specialized in software and those who specialized in hardware. Younger
and more enthusiastic than their teachers, both groups carried on their efforts,
but following the different paths. While the first advanced steadily to this day,
those dedicated to hardware got carried away by their success and eventually
discovered a transistor.

Up to that crucial moment, the situation could have been controlled to a

certain extent - but the public underestimated the importance of this
breakthrough and made a grave mistake! In a naive attempt to slow down the
technological revolution, world market opened itself for a flood of electronic
products, thus closing the circle. Market value of components rapidly decreased,
electronics making its way to the younger populace. Discovery of the integrated
circuits and the processors only sped up the things, making the computers as
available as ever. Computers started to upgrade themselves. The resulting
deflation brought electronics new wave of devotees, making it omnipresent
nowadays. Computers fell into the hands of the masses and their rule supreme
had begun...

While this drama took place, nameless hobbyists and professionals across
the world kept working on their projects, although still divided into two large
factions. And then somebody came up with another great idea: why not create an
all-purpose component? A cheap and universal integrated circuit that could be

16
programmed and used in any device, anywhere. Technology was up to the task;
there was an interested market... why not? Soul and body were united into one
powerful MICROCONTROLLER.

A Microcomputer designed on a single board typically includes a

Microprocessor, RAM, ROM, Clock generator, Timer/Counter and some Serial
& Parallel I/O lines. The complete microcomputer on a single chip is known as a
Microcontroller.Some of the microcontroller have on-chip A/D converter and
pulse width modulated output signal.

The Microcontroller has innumerable applications in every field. It plays

a significant role in the daily functioning of all industrialized societies. No field
can ignore the applications of microcontroller. They are primarily used for

control applications [10] such as Traffic lights, Washing machines, Video

recorders, Calculators.... etc. Now they are extensively used in sophisticated
Real-time demanding applications like industrial control (machine control), Data
processing (plotters, tape drivers, Winchester disc drivers), Telecommunications
(modems, intelligent line card control), Instrumentation computer peripherals.

The uses of Microcontrollers reduce the hardware as well as complexity

as they have on-chip all essential components of a microcomputer. This finds
applications in portable and low cost instruments and dedicated applications.

In the present study the Microcontroller PIC 16F873 is used which is an 8-

bit CMOS FLASH Microcontroller.

2.2 ARCHITECTURE OF PIC 16F873 MICROCONTROLLER

The internal logic design of a device is called its architecture. The

Microcontroller architecture [11] determines how and what various operations

17
are performed. The architecture of the PIC 16F873 Microcontroller is shown in
Figure 2.1.

RAQAMO
RA1<AN1
RiCAtCVRS*.
RA3AIJ3-VHE--*-
RA+TOCKI
RA5'AM4)S5

RBOiNF
RBI
RB2
R83PGM
RB4
RB5
RflftPSC
RSTiPGD
RCOTIOSOfTICKi
HCVT10SKCP2
RCS’CCPt
RC3SCK/SCL
RC*SO>SDA
RCS'SOS
ReerocK
RC'PXCT

Figure 2.1 Block Diagram of PIC 16F873 Microcontroller

The architectural features of PIC 16F873 Microcontroller are given below

!8
Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn
• All single cycle instructions except for program branches, which
are two cycle
• Operating speed: DC - 20 MHz clock input DC - 200 ns
instruction cycle
• Up to 8K x 14 words of FLASH Program Memory, Up to 368 x 8
bytes of Data Memory (RAM), Up to 256 x 8 bytes of EEPROM
data memory
• Pinout compatible to the PIC 16C73B/74B/76/77
• Interrupt capability (up'to 14 sources)
• Eight level deep hardware stack
• Direct, indirect and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC oscillator for
reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS FLASH/EEPROM technology
• Fully static design
• In-Circuit Serial Programming a (ICSP) via two pins
• Single 5V In-Circuit Serial Programming capability
• In-Circuit Debugging via two pins
• Processor read/write access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Commercial and Industrial temperature ranges
• Low-power consumption:

19
- < 2 mA typical @ 5V, 4 MHz
- 20 mA typical @ 3V, 32 kHz
-< 1 mA typical standby current

❖ Peripheral Features

• TimerO: 8-bit timer/counter with 8-bit prescaler

• Timer 1: 16-bit timer/counter with prescaler can be incremented
during sleep Via external crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler
and postscaler
• Two Capture, Compare, PWM modules
- Capture is 16-bit, max. Resolution is 12.5 ns
- Compare is 16-bit, max. Resolution is 200 ns
- PWM max. Resolution is 10-bit
• 10-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPIa (Master Mode) and I2Ca
(Master/Slave)
• Universal Synchronous Asynchronous Receiver Transmitter
(USART/SCI) with 9-bit address detection
• Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and
CS controls

❖ PIC 16F873 Microcontroller Pin Configuration

The PIC 16F873 Microcontroller is a 28 pin DIP. The Pin diagram [12]
contains the abbreviated names of the signals for each pin. It is important to note
that many of the pins are used for more than one function. Programming
functions or physical pin connections determine the use of any multifunction
pins. The system designer decides which of these functions is to be used and
designs the hardware and software affecting that pin accordingly.

20
The Pm diagram of PIC 16F873 Microcontroller is shown m Figure 2.2.
The pinout description of PIC 16F873 Microcontroller is given in table 2.1.

! - i n::
-E 3 — R67-GC
raCD?Vp=;THV-

q> rj
3 REt.'-GC

j
RAD'ANO * -t:

o> r

fj (j
RA1AN1 •> -E 3 *— RK

P IC 1 6 F 8 7 6 /8 7 3
*«•

tj fr»j oi
* -t 3 —* =.E4

a> c*
■E 3 — *.E»'-Gf,'

o ou •*fj ifj,j u>

i^TDCK - -C 33 — RE:

I
RAS/AM®* -t RBI
*-*•

co
Vss- •E 3 —~ REC.IKT
C'SCTwLK'M- -E «—Vcc

o »
OSC2.CLKOiT • -E 3 .»_Vss

n>
3 —* RC7-RXO-
RCaTtOSOTlCK - •C to rS
3 —*■ RC6'TX.'CK
RCinos.'CC?2",-*C 3 RCS'SOO
RC1'CC=1—*-E

o oi
RCS'SCK'SCl *— C 3 — RC4:SD1,'£3A
^ j

Figure 2.2 Pin Diagram of PIC 16F873 Microcontroller I

21
Pin out Description

DIP SOIC VOIP Buffer

Pin Name Description
Pin# Pin# Type. Type
OSCI'CLK.N S' V i ST C'.103(S; Oscillator crystal inpui'etfemal clock source input.
OSC2CUXUT 1C 10 0 Cscfilato' cysts; cutout Connects tc crysta • ot resonator >n crystal
oscillator mode n PC mode the 0SC2 pin cutouts CLKOo"
which has **4 ire Kcueney of 03C1. and denotes the instruct on
cycle r3te.
MCLRV=f.'--V 1 !-’P ST Master c ear ■;«&$«:) nput or programrt ng voltage input or high
voltage test ncce control. T*i$ pin is an active low reset to the
device.
®ORTA is a bi-d -soonaf l.’O son.
RA&AND 2 2 i«‘0 Tl RAG can also be analog inputD
RA?;AN1 5- 3 i<*0 ~TL RA1 can also be analog input 1
RA2;AN2-Vfef- 4 4 i*0 "TL RA2 can also r-e analog inpu:2 or negative ana og reference
voltage
RA2.‘Ai\3V«EF+ 5 K. If'O Tl RA3 can also be ana og inp-'S c*- positive analog reference
voltage
RA4T0CKI 5 z [■'0 ST RA4 can also be the clock input to the TinerO module. Outc-1
s open drain type.
RAE.'SSlAN4 [f'O "TL RA5 can also be analog nput4 or toe slave seectforthe
7 synchronous serial por.
-CRT3 is a bn; regional L’O port. POR"S can be software
r^ogranmed for interna! weak pull-up on ail inpcts.
RBC.1NT 21 21 I'O RBO can also be the e»:temal interrupt p^.
R3- 22 22 i-0 "TL
RSi 23 23 ■'0 "TL
R32.'PGM 2* 24 !-0 "TL RB3 C-3” also be the low vc tage programming tout
R34 25 •oo "TL interrupt ■:** change pin
a:
cn

2e 28 u'0 TL interrupt o" change pin

R35/PGC -17 -IT uQ interrupt >:•* change pin or n-Circ-it Debugger r- n. Ser3
prograrvivng c ock.
RB7;PGD 21 28 i:° T-_STa:. interrupt change pin or n-C'fc-it Debugger z n. Sera
©npgranhvng data.
RORTC ts 3 Si-directsc-al l>G pen
RCO.TtOSO>T1C<l 11 11 VC ST RCDcan also be toe Tiererl oscillator cvlput or Timerl clock
nput
RC1T103i’CCP2 12 12 \;q ST RC1 can also be toe" *ner1 oscillator input or C apt-rs2 input'
Compared output'FWM2 output.
RC2CCP1 13 13 VO 3T RC2 can also be the Capture 1 inp-t'Ccmpare- outout'PVVMI
o-tput.
RC3'SCKSCL Id 14 HQ ST RC3 can a so re toe synchronous serial clock mput'eutput for
both 3P anc l:C modes.
RC4.SDI.3DA 1c 15 VO 3T RC4 can also c* the SPI Data to i$Pl mode) or
ca:a vO itoC nosel
RCd-SDC ie 16 I'D 3T RC5 can also be the SPI Data OutiSR mode}.
RC6.TX.'C-< 17 17 I/O ST RC5 san also b« fe JSAR” Asynchronous Transn; or
Synchronous Clock
RC7’RX/DT 18 18 i*0 ST RC" can also be toe uSAR" Asynchronous Receive or
Synchronous Data
V;; 8 1i 5. 19 - - Si'ound tefere-ce for ogic and i‘C pins.
Voc 2€ 20 = __ Positive supply "V ogic and i.'O p ns.
Legend i - npu: 0 = OUtS A , s nc.vowtCv? P * bower
- s \jC- -sec TT;. ~ T"L inp.t ST * Schn tt Trigger input
Note 1: "ns buffer r 3 3chrr;tt Trigg*' np wne- con {.red a- the e eternal mterrwpi
2: s buffer is 3 Schtrnr,Trigg**.up*: wher used to sera programs ing ncc*.
3: "* s -buffer ts a Schirrtc Trigg*’ input when oonfg^-M * RC csa atcrrrvde a-da CMOS input otherwise.

Table 2.1 Pinout Description

22
2.3 MEMORY ORGANIZATION

There are three memory blocks in PIC 16F873 Microcontroller [13]. The
Program Memory and Data Memory have separate buses so that concurrent

access can occur.

2.3.1 Program Memory Organization

The PIC16F87X devices have a 13-bit program counter capable of

addressing an 8K x 14 program memory space. The PIC 16F873 device has 4K x
14 words of FLASH program memory. Accessing a location above the
physically implemented address will cause a wraparound. The reset vector is at
OOOOh and the interrupt vector is at 0004h.

The PIC 16F873 Program memory Map and stack is shown in Figure 2.3.

Figure 2.3 PIC16F873 Program Memory Map And Stack

23
2.3.2 Data Memory Organization

The data memory is partitioned into multiple banks, which contain the
General Purpose Registers and the Special Function Registers. Bits RP1
(STATUS<6>) and RPO (STATUS<5>) are the bank select bits. These bits are
represented in the Table 2.2.

RP1:RP0 Bank
CO 0
01 1
10 2
11 3

Table 2.2 Bank Select Bits

Each bank extends up to 7Fh (128 bytes). The lower locations of each
bank are reserved for the Special Function Registers. Above the Special
Function Registers are General Purpose Registers, implemented as Static RAM.
All implemented banks contain Special Function Registers. Some “high use”
Special Function Registers from one bank may be mirrored in another.

2.3.3 Special Function Registers

Special Function Registers [14] are special elements of RAM, their

purpose predefined by the manufacturer. Each of these registers is named and
controls a certain subsystem of MCU. For example: by writing zeros and ones to
the SFR register which controls an I/O port, each of these pins can be designated
as input or output (each register bit corresponds to one of the port pins).

The Special Function Registers are registers used by the CPU and
peripheral modules for controlling the desired operation of the device. These
registers are implemented as static RAM. The Special Function Registers can be
classified into two sets; core (CPU) and peripheral.

24
Status Register

The STATUS register contains the arithmetic status of the ALU, the
RESET status and the bank select bits for data memory. The STATUS register
can be the destination for any instruction, as with any other register. If the
STATUS register is the destination for an instruction that affects the Z, DC or C
bits, then the write to these three bits is disabled. These bits are set or cleared
according to the device logic. Furthermore, the TO and PD bits are not writable,
therefore, the result of an instruction with the STATUS register as destination
may be different than intended. It is recommended, that only BCF, BSF, SWAPF
and MOVWF instructions are used to alter the STATUS register, because these
instructions do not affect the Z, C or DC bits from the STATUS register.

❖ OptionReg Register

The OPTION_REG Register is a readable and writable register, which

contains various control bits to configure the TMRO presealer/WDT postscaler
(single assignable register known also as the prescaler), the External INT
Interrupt, TMRO and the weak pull-ups on PORTB.

❖ PIE1 Register

The PIE1 register contains the individual enable bits for the peripheral
interrupts.

❖ PIR1 Register

The PIR1 register contains the individual flag bits for the peripheral
interrupts.

❖ PIE2 Register

25
The PIE2 register contains the individual enable bits for the CCP2
peripheral interrupt, the SSP bus collision interrupt, and the EEPROM write
operation interrupt.

❖ PIR2 Register

The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP
bus collision interrupt and the EEPROM write operation interrupt.

❖ PCON Register

The Power Control (PCON) Register contains flag bits to allow

differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a
Watch-dog Reset (WDT) and an external MCLR Reset.

2.4 I/O PORTS

Some pins for these I/O ports are multiplexed with an alternate function
for the peripheral features on the device. In general, when a peripheral is
enabled, that pin may not be used as a general purpose I/O pin.

There are three ports in PIC 16F873 [14] Microcontroller. They are
Port A, Port B and Port C.

□ PORTA and the TRISA Register

PORTA is a 6-bit wide bi-directional port. The corresponding data

direction register is TRISA. Setting a TRISA bit (=1) will make the
corresponding PORTA pin an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will make the corresponding
PORTA pin an output.

26
□ PORTB and the TRISB Register

PORTB is an 8-bit wide, bi-directional port. The corresponding data

direction register is TRISB. Setting a TRISB bit (=1) will make the
corresponding PORTB pin an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding
PORTB pin an output.

□ PORTC and the TRISC Register

r

PORTC is an 8-bit wide, bi-directional port. The corresponding data direction

register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin
an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a
TRISC bit (=0) will make the corresponding PORTC pin an output. PORTC pins have
Schmitt Trigger input buffers.

2.5 TIMERS

Majority of programs utilizes these miniature electronic "stopwatches".

Commonly, timers are 8 or 16-bit registers whose value automatically increases
upon an impulse. If timer is stimulated by an internal MCU oscillator, it can be
used for measuring time between two occurrences (register value at the start of
measuring = Tl, register value at the end of measuring = T2, elapsed time = T2-
Tl). If timer is triggered by impulses from an external source, instrument
behaves like a counter. In both cases, filling the register resets the counter and
the occurrence is recorded in a particular bit of SFR register (Overflow flag).
This makes possible to measure longer time periods. Also, if enabled, this flag
can cause an interrupt for breaking the program and carrying out a designated
routine.

2.5.1 Timer 0 Module

The TimerO module timer/counter has the following features:

27
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to OOh
• Edge select for external clock

Timer mode is selected by clearing bit TOCS (OPTION REG<5>). In

timer mode, the TimerO module will increment every instruction cycle (without
prescaler). If the TMRO register is written, the increment is inhibited for the
following two instruction cycles. The user can work around this by writing an
adjusted value to the TMRO register. Counter mode is selected by setting bit
TOCS (OPTION REG<5>). In counter mode, TimerO will increment either on
every rising or falling edge of pin RA4/T0CKI. The incrementing edge is
determined by the TimerO Source Edge Select bit TOSE (OPTION_REG<4>).
Clearing bit TOSE selects the rising edge. The prescaler is mutually exclusively
shared between the TimerO module and the watchdog timer. The prescaler is not
readable or writable

2.5.2 Timer1 Module

The Timerl module is a 16-bit timer/counter consisting of two 8-bit

registers (TMR1H and TMR1L), which are readable and writable. The TMR1
Register pair (TMR1H:TMR1L) increments from OOOOh to FFFFh and rolls over
to OOOOh. The TMR1 Interrupt, if enabled, is generated on overflow, which is
latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE
(PIE1<0>). Timerl can operate in one of two modes:

• As a timer
* As a counter

28
The operating mode is determined by the clock select bit, TMR1CS
(T1C0N<1>). In timer mode, Timer 1 increments every instruction cycle. In
counter mode, it increments on every rising edge of the external clock input.
Timer 1 can be enabled/disabled by setting/clearing control bit TMRION
(T1CON<0>). Timer 1 also has an internal “reset input”. This reset can be
generated by either of the two CCP modules counter mode is selected by setting
bit TMR1CS. In this mode, the timer increments on every rising edge of clock
input on pin RC1/T10SI/CCP2, when bit T10SCEN is set, or on pin
RCO/TIOSO/TICKI, when bit T10SCEN is cleared. Timerl may operate in
asynchronous or synchronous mode depending on the setting of the TMR1CS
bit.

2.6 ADDRESSABLE UNIVERSAL SYNCHRONOUS

ASYNCHRONOUS RECEIVER TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver Transmitter

(USART) module is one of the two serial I/O modules. (USART is also known
as a Serial Communications Interface or SCI). The USART [15] can be
configured as a full duplex asynchronous system that can communicate with
peripheral devices such as CRT terminals and personal computers, or it can be
configured as a half duplex synchronous system that can communicate with
peripheral devices such as A/D or D/A integrated circuits, serial EEPROMs etc.

The USART can be configured in the following modes:

• Asynchronous (full duplex)

• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)

Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to

configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter. The USART module also has a multi­
processor communication capability using 9-bit address detection.

29
O USART Asynchronous Mode

In this mode, the USART uses standard non-retum-tozero (NRZ) format

(one start bit, eight or nine data bits, and one stop bit). The most common data
format is 8 bits. An on-chip, dedicated, 8-bit baud rate generator can be used to
derive standard baud rate frequencies from the oscillator. The USART transmits
and receives the LSB first. The USART’s transmitter and receiver are
functionally independent, but use the same data format and baud rate. The baud
rate generator produces a clock either xl6 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be
implemented in software (and stored as the ninth data bit). Asynchronous mode
is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).

The USART Asynchronous module consists of the following important

elements:
• Baud Rate Generator
• Sampling Circuit
• Asynchronous Transmitter
• Asynchronous Receiver

O USART ASYNCHRONOUS TRANSMITTER

The USART transmitter block diagram is shown in Figure 2.4. The heart
of the transmitter is to transmit (serial) shift register (TSR). The shift register
obtains its data from the read/write transmit buffer, TXREG. The TXREG
register is loaded with data in software. The TSR register is not loaded until the
STOP bit has been transmitted from the previous load. As soon as the STOP bit
is transmitted, the TSR is loaded with new data from the TXREG register (if
available). Once the TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>)
is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE

30
and cannot be cleared in software. It will reset only when new data is loaded into
the TXREG register. While flag bit TXIF indicates the status of the TXREG
register, another bit TRMT (TXSTA<1>) shows the status of the TSR register.
Status bit TRMT is a read only bit, which is set when the TSR register is empty.
No interrupt logic is tied to this bit, so the user has to poll this bit in order to
determine if the TSR register is empty. Transmission is enabled by setting
enable bit TXEN (TXSTA<5>).

Figure 2-4 USART Transmit Block Diagram

Steps to follow when setting up an Asynchronous Transmission:

• Initialize the SPBRG register for the appropriate baud rate. If a high
speed baud rate is desired, set bit BRGH.
• Enable the asynchronous serial port by clearing bit SYNC and setting bit
SPEN.
• If interrupts are desired, then get enable bit TXIE.
• If 9-bit transmission is desired, then set transmit bit TX9.
• Enable the transmission by setting bit TXEN, which will also set bit
TXIF.
• If 9-bit transmission is selected, the ninth bit should be loaded in bit
TX9D.
• Load data to the TXREG register (starts transmission).

31
O USART ASYNCHRONOUS RECEIVER

The receiver block diagram is shown in Figure 2.5.The data is received on

the RC7/RX/DT pin and drives the data recovery block. The data recovery block
is actually a high speed shifter operating at xl6 times the baud rate, whereas the
main receive serial shifter operates at the bit rate or at FOSC.Once asynchronous
mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The
heart of the receiver is to receive (serial) shift register (RSR). After sampling the
STOP bit, the received data in the RSR is transferred to the RCREG register (if it
is empty). If the transfer is complete, flag bit RCIF (PIR1<5>) is set. The actual
interrupt can be enabled/disabled by setting/clearing enable bit RCIE
(PIEl<5>).Flag bit RCIF is a read only bit which is cleared by the hardware. It is
cleared when the RCREG register has been read and is empty. The RCREG is a
double buffered register (i.e. it is a two deep FIFO). It is possible for two bytes
of data to be received and transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of the STOP bit of the third
byte, if the RCREG register is still full, the overrun error bit OERR
(RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register
can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to
be cleared in software. This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from the RSR register to the
RCREG register are inhibited, so it is essential to clear error bit OERR if it is set.
Framing error bit FERR (RCSTA<2>) is set if a stop bit is detected as clear. Bit
FERR and the 9th receive bit are buffered the same way as the receive data.
Reading the RCREG will load bits RX9D and FERR with new values, therefore
it is essential for the user to read the RCSTA register before reading RCREG
register in order not to lose the old FERR and RX9D information.

32
;<34 Baud Rate C_K
CREN
SP3RG 1
50'*
Baud Rate Generate' n •

»ie
RC7.-RX.-DT

SPEM

Interrupt

Figure 2-5 USART Receiver Block Diagram

Steps to follow when setting up an Asynchronous Reception:

• Initialize the SPBRG register for the appropriate baud rate. If a high­

speed baud rate is desired, set bit BRGH.

• Enable the asynchronous serial port by clearing bit SYNC and setting bit

SPEN.

• If interrupts are desired, then set enable bit RCIE.

• If 9-bit reception is desired, then set bit RX9.

• Enable the reception by setting bit CREN.

• Flag bit RCIF will be set when reception is complete and an interrupt

will be generated if enable bit RCIE is set.

• Read the RCSTA register to get the ninth bit (if enabled) and determine

if any error occurred during reception.

• Read the 8-bit received data by reading the RCREG register.

• If any error occurred, clear the error by clearing enable bit CREN.

2.7 ANALOG TO DIGITAL CONVERTER

The Analog-to-Digital (A/D) Converter module [14] has five inputs for
the 28-pin devices and eight for the other devices. The analog input charges a

sample and hold capacitor. The output of the sample and hold capacitor is the

input into the converter. The converter then generates a digital result of this

33
analog level via successive approximation. The A/D conversion of the analog
input signal results in a corresponding 10-bit digital number. The A/D module
has high and low voltage reference input that is software selectable to some
combination of VDD, VSS, RA2 or RA3.The A/D converter has a unique
feature of being able to operate while the device is in SLEEP mode. To operate
in sleep, the A/D clock must be derived from the A/D’s internal RC oscillator.

The A/D module has four registers. These registers are;

• A/D Result High Register (ADRESH)
• A/D Result Low Register (ADRESL)
• A/D Control RegisterO (ADCONO)
• A/D Control Registerl (ADCON1)

The ADCONO register controls the operation of the A/D module. The
ADCON1 register configures the functions of the port pins. The port pins can be
configured as analog inputs (RA3 can also be the voltage reference) or as digital
I/O.The ADRESH: ADRESL registers contain the 10-bit result of the A/D
conversion. When the A/D conversion is complete, the result is loaded into this
A/D result register pair, the GO/DONE bit (ADCONO<2>) is cleared and the
A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is
shown in Figure 2.6.After the A/D module has been configured as desired, the
selected channel must be acquired before the conversion is started. The analog
input channels must have their corresponding TRIS bits selected as inputs.

The following steps should be followed for doing an A/D conversion:

> Configure the A/D module:

• Configure analog pins / voltage reference /and digital I/O
(ADCON1)
• Select A/D input channel (ADCONO)
• Select A/D conversion clock (ADCONO)
• Turn on A/D module (ADCONO)

34
> Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
> Wait the required acquisition time.
> Start conversion:
• Set GO/DONE bit (ADCONO)
> Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
> Read A/D Result register pair (ADRESH: ADRESL), clear bit
ADIF if required.
> For next conversion, go to step 1 or step 2 as required. The A/D
conversion time per bit is defined as TAD. A minimum wait of
2TAD is required before next acquisition starts.

35
CH$2:ChSC

Figure 2-6 A/D Block Diagram

2.8. WATCH DOG TIMER

The Watchdog Timer [16] is as a free running on-chip RC oscillator

which does not require any external components. This RC oscillator is separate
from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the
device has been stopped. The block diagram is shown in Figure 2.7.

During normal operation, a WDT time-out generates a device RESET

(Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out
causes the device to wake-up and continue with normal operation (Watchdog

36
Timer Wake-up). The TO bit in the STATUS register will be cleared upon a
Watchdog Timer time-out. The WDT can be permanently disabled by clearing
configuration bit WDTE. Values for the WDT prescaler may be assigned using
the OPTION REG register.

From TMRC Clock Source

; Fig .ire 5-11

«"*— P32P3C

To TMRC (Figure M)

PSA

WOT
Tire-ou?

Figure 2.7 WATCHDOG TIMER BLOCK DIAGRAM

2.9 ADDRESSING MODES

Data is stored at a source address and moved to a destination address. The

ways by which these addresses are specified are called the addressing modes.

In PIC 16F873 microcontroller there are two important addressing modes

[12] which are used to access data. They are
• Direct Addressing
• Indirect Addressing
RAM memory locations can be accessed directly or indirectly.

• Direct Addressing Mode

Direct addressing is done through a 9-bit address. This address is obtained

by connecting 7th bit of direct address of an instruction with two bits (RP1, RPO)

37
from STATUS register .Any access to SFR registers can be an example of direct
addressing.
• Indirect Addressing Mode

Indirect addressing mode does not take an address from an instruction but
makes it with the help of IRP bit of STATUS and FSR registers. Addressed
location is accessed via INDF register which infact holds the address indicated
by a FSR.

For example, one general purpose register at address OFh contains a value
of 20.By writing a value of OFh in FSR register we will get a register indicator at
address OFh and by reading from INDF register, we will get a value of 20, which
means that we have read from the first register its value without accessing it
directly.

2.10 INSTRUCTION SET

Each instruction in PIC 16F873 is a 14-bit word divided into an opcode,

which specifies the instruction type and one or more operands, which further
specify the operation of the instruction.

The instruction set is highly orthogonal [17] and is grouped into three
basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a
conditional test is true or the program counter is changed as a result of an
instruction. In this case, the execution takes two instruction cycles with the
second cycle executed as a NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction

38
execution time is 1 ms. If a conditional test is true or the program counter is
changed as a result of an instruction, the instruction execution time is 2 ms.

• Byte-oriented operations

For byte-oriented instructions, T represents a file register designator and

’d’ represents a destination designator. The file register designator specifies
which file register is to be used by the instruction. The destination designator
specifies where the result of the operation is to be placed. If ’d’ is zero, the result
is placed in the W register. If ’d’ is one, the result is placed in the file register
specified in the instruction.

The Format of this is

oyte-oreoted register operations

13. are c
OPCODE f ("he #;■
d = 0 for destination V¥
d = ' for destir 3tior f
f = 7-bi: He reg ster address

• Bit-oriented operations

For bit-oriented instructions, ’b’ represents a bit field designator

which selects the number of the bit affected by the operation, while T
represents the number of the file in which the bit is located.

The Format of this is

3>t-c dented fderegster operations

13 -3 & 76
OPCODE b (SlT #) f (FILE 0}

b = 3-bit bit aacress

f = 7-bi: file reg ster address

• Literal and control operations

For literal and control operations, ’k’ represents an eight or eleven bit
constant or literal value.

39
Jiersi and centra ape-atons

Gere-a
IS 8 C
OPCODE h (kerall

k » 5-bit immediate value

2AL_ and GOTO instructions only

13 11 10
OPCODE k (literal)

k = 11-bi: imTed ate value

The PIC 16F873 Microcontroller instruction set [18] is shown in Table 2.3

Mremenlc, Description Cycles H-Sit Opcode Status Notes

Operates MSb -Sb Affected

■3vTE-OR)ENTEO FLE REG 3 *ER OPERA-IO

ADOWF f d Add W and f OO 0111 dfff ffff C..QCfZ 1.2
ANBWF * d AND ‘A* with f 00 0101 dfff ffff •7 1.2
CLRF t Clea* ? o-:> 0001 lfff ffff Z •>
CLRW Otar y< 00 0001 oxxx 7XXX
z
COMF * d ComplementJ 00 1001 dfff ffff z t,2
OECF ?. d Decrement f 00 oon if f £ ffff 1.2
DECFSZ f. d Decrement f. Skip* f3 I\2\
z
00 1011 dfff ffff 1,2.3
SNCF f d Increment f 00 1010 iff f ffff 2 1,2
*NCFSZ ?. d Increment ?, Skip r C !t2) 00 1111 dfff ffff 1 2.3
sORWF * d inclusive OR W with f ! GO 0100 dfff ffff z 1,2
MOV'F * d Move f 00 1000 dfff ffff ? 1,2
MOVWF t Wove A to f oo 00 00 lfff ffff
NOP - No Operation oo oooo oxxo OOOO
RLF 1 d Rotate Left f through Carry 00 1101 dfff ffff r- 1.2
RRF ?. d Rctaie Right * th-cjgh Ca-ry oo 1100 dfff ffff C 1,2
SUBWF f. d Subt'act W from 1 oo 0010 dfff ffff C.OC.Z 1,2
SWAPF f. d Swap n-boles in f oo 1110 dfff ffff 1.2
XORWF f. d Exclusive OR W wth f t 00 0110 dfff ffff z 1,2
• •
BIT-ORIENTED FK.E REOIS- ER OPERATION s •
BCF f. b Bs Clear f ' 01 OOfcb bfff ffff 1.2
BSF * b Si Set f 01 oifcb bfff ffff 1,2
6TF3C f b Bt Test f, Skip \r Dear 1 i2) 01 lObb bfff ffff 3
BTFSS < b Bfest f. Skip if Set 1 (2) 01 ilbb bfff ffff 3
LATERAL AND CONTROL OPERATIONS
ADDLW k Add iteral and A 11 1 llx kkkk kkkk C.OC.Z
ANOLW k AND literal With VV 11 looi kkkk kkkk z
CALL k Ca l subroutine 2 10 Okkk kkkk kkkk
CLRWDT - Clea' Watchdog Tme- 00 0000 ono 0100 TO,PD
GOTO K Go to address 2 10 lkkk kkkk kkkk
lORtW k Inclusive CR literal with W 11 1000 kkkk kkkk 2
MOVV/v k Move literal to W 11 OOxx kkkk kkkk
RETFIE - Return *fcm interrupt 2 00 oooo OOOO 1001
RETIW k Return with Utera- n W •*? 11 Olxx kkkk kkkk
RETURN - Retjrr frsrr Subroutine -> 00 oooo OOOO 1000
$L£EP - Go into siordoy mode oo oooo 0110 0011 WPS
SU3C.V h Sjbfaot W from I’te'ai 11 110X kkkk kkkk C.DCZ
XCR-W k Exclusive OR literal with W 11 1010 kkkk kkkk z

Table 2.3 PIC16F873 INSTRUCTION SET

Some of the important instructions used in the present study are explained
below in detail.

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Instruction Descriptions

■ ADDLW Add Literal and W

Syntax: [label] ADDLW k

Operands: 0 £ k £ 255
Operation: (W) + k ® (W)
Status Affected: C, DC, Z
Description: The contents of the W register are added to the eight-bit
literal ’k’ and the result is placed in the W register.

- BCF Bit Clear f

Syntax: [label] BCF f, b

Operands: 0£f£ 1270£b£7
Operation: 0 ® (f<b>)
Status Affected: None
Description: Bit *b* in register 'f is cleared. ,,

- CALL Call Subroutine " 1

Syntax: [label] CALL k

Operands: 0 £ k £ 2047
Operation: (PC)+ 1® TOS,k ® PC<10:0>,(PCLATH<4:3>)® PC<12:11>
Status Affected: None
Description: Call Subroutine. First, return address (PC+1) is pushed onto
the stack. The eleven bit immediate address is loaded into PC bits <10:0>.
The upper bits of the PC are loaded from PCLATH. CALL is a two cycle
instruction.

■ CLRF Clear f

Syntax: [label] CLRF f

Operands: 0 £ f £ 127
Operation: OOh ® (f)l ® Z
Status Affected: Z
Description: The contents of register ’f are cleared and the Z bit is set.

■ COMF Complement f

Syntax: [label] COMF f,d

Operands: 0£f£ 127dI [0,1]
Operation: (f) ® (destination)
Status Affected: Z
Description: The contents of register T are complemented. If ’d’ is 0, the
result is stored in W. If’d’ is 1, the result is stored back in register ’f.

■ DECF Decrement f

Syntax: [label] DECF f,d

Operands: 0£f£ 127dI [0,1]
Operation: (f) - 1 ® (destination)
Status Affected: Z
Description: Decrement register ’f. If’d’ is O.the result is stored in the W
register. If’d’ is 1, the result is stored back in register T.

■ GOTO Unconditional Branch

Syntax: [label] GOTO k

Operands: 0 £ k £ 2047
Operation: k ® PC<10:0>PCLATH<4:3> ® PC<12:11>
Status Affected: None
Description: GOTO is an unconditional branch. The eleven bit immediate
value is loaded into PC bits <10:0>. The upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a two-cycle instruction.

■ INCF Increment f

Syntax: [label] INCF f,d

42
Operands: 0£f£127d I [0,1]

Operation: (f) + 1 eg) (destination)

Status Affected: Z
Description: The contents of register ’f are incremented. If’d’ is 0, the
result is placed in the W register. If’d’ is 1, the result is placed back in
register T.

" IORLW Inclusive OR Literal with W

Syntax: [label] IORLW k

Operands: 0 £ k £ 255
Operation: (W) .OR. k ® (W)
Status Affected: Z
Description: The contents of the W register are OR’ed with the eight bit
literal 'k'.The result is placed in the W register.

* NOP No Operation
Syntax: [label] NOP
Operands: None
Operation: No operation
Status Affected: None
Description: No operation.

* RETURN Return from Subroutine

Syntax: [label] RETURN

Operands: None
Operation: TOS ® PC
Status Affected: None
Description: Return from subroutine. The stack is POPed and the top of
the stack (TOS) is loaded into the program counter. This is a two-cycle
instruction.

43