SLITE TECHNOLOGIES

VLSI PROJECTS
Sl.No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. Project Title Spectrally Shaped Generalized MC-DS-CDMA with Dual Band Combining for Increased Diversity Single Chip Encryptor Decryptor Core Implementation of AES Algorithm Serial Search Code Acquisition Using Smart Antennas with Single Correlator or Matched Filter Practical Asynchronous Interconnect Network Design Fast Elliptic Curve Cryptography on FPGA A Novel Approach to Design BCD Adder and Carry Skip BCD Adder A Novel Carry-look ahead approach to an Unified BCD and Binary Adder_Subtractor Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores Cost-Effective Triple-Mode Reconfigurable Pipeline FFT_IFFT_2-D DCT Processor General Design Issues of Sliding-Mode Controllers in DCDC Converters Multilevel Multiphase Space Vector PWM Algorithm A Space Vector PWM Scheme for Multi frequency Output Voltage Generation With Multiphase Voltage-Source Inverters Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors System-Level Specification Testing Of Wireless Transceivers A Power-Efficient and Self-Adaptive Prediction Engine for H.264/AVC Decoding Equalization and Coding for On-Chip Bus Communication A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic Speculative Carry Generation With Prefix Adder A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors Proceedings/Year IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008

TRICHY: 168/ 3, 1st Floor, JJ Tower, Near STAR Theater, Madurai road, Trichy-8 Ph:0431 4011860,61 CHENNAI :No 91,2nd Floor,1st Avenue, Ashok Nagar,Chennai-83 Ph: 044 - 64627827 MOBILE: 9444108716 , 9994603786 , 9894147084

SLITE TECHNOLOGIES
21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. Architectural Modifications to Enhance the Floating-Point Performance of FPGAs System Architecture and Implementation of MIMO Sphere Decoders on FPGA FPGA Implementation(s) of a Scalable Encryption Algorithm Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance Run-Time Management of a MPSoC Containing FPGA Fabric Tiles A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors Reconfigurable Architecture for Network Flow Analysis A JPEG Compression Resistant Steganography Scheme for Raster Graphics Images A Low-Power Multiplier With the Spurious Power Suppression Technique A Novel SPWM Method with Voltage Balancing Capability for Multilevel Rectifier Inverter Systems A Partial Self-Reconfigurable Adaptive Fir Filter System A Performance Comparison of DS-CDMA and MC-CDMA with PerUser MMSE Frequency Domain Equalization A Simple Design Of M-Channel Fir Wavelet-Like Filter Bank An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm Applying CDMA Technique to Network-on-Chip Configurable Adaptive Viterbi Decoder for GPRS , EDGE and Wimax Design and Realization ofNCO of Modulation Based on FPGA Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication Differential Power Analysis for Data Encryption Standard Hirschman Optimal Transform Block LMS Adaptive Filter IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2008 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007

TRICHY: 168/ 3, 1st Floor, JJ Tower, Near STAR Theater, Madurai road, Trichy-8 Ph:0431 4011860,61 CHENNAI :No 91,2nd Floor,1st Avenue, Ashok Nagar,Chennai-83 Ph: 044 - 64627827 MOBILE: 9444108716 , 9994603786 , 9894147084

SLITE TECHNOLOGIES
42. 43. 44. 45. 46. 47. 48. 49. 50. 51. 52. 53. 54. 55. 56. 57. 58. 59. 60. 61. 62. 63. PID Digital Control Using Microcontroller and FPGA Applied to a Single-Phase Three-Level Inverter Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform The low power biotelemetry architecture for implantable applications A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips Design and Optimization of On-Chip Interconnects Using WavePipelined Multiplexed Routing Run-Time Integration of Reconfigurable Video Processing SystemsCode Decompression Unit Design for VLIW Embedded Processors Code Decompression Unit Design for VLIW Embedded Processors A Novel Charge Recycling Design Scheme Based on Adiabatic Charge Pump SIMD Processor-Based Turbo Decoder Supporting Multiple ThirdGeneration Wireless Standards Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits Registers for Phase Difference Based Logic Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform A Flexible Architecture for Precise Gamma Correction A Processor-In-Memory Architecture for Multimedia Compression A Memory Efficient Partially Parallel Decoder Architecture for QuasiCyclic LDPC Codes Power Modeling and Efficient FPGA Implementation of FHT for Signal Processing Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems Architecture and Implementation of an Interpolation Processor for Soft-Decision ReedSolomon Decoding An Energy-Efficient Reconfigurable Baseband Processor for Wireless Communications Design Methodology for Global Resonant H-Tree Clock Distribution Networks IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007

TRICHY: 168/ 3, 1st Floor, JJ Tower, Near STAR Theater, Madurai road, Trichy-8 Ph:0431 4011860,61 CHENNAI :No 91,2nd Floor,1st Avenue, Ashok Nagar,Chennai-83 Ph: 044 - 64627827 MOBILE: 9444108716 , 9994603786 , 9894147084

SLITE TECHNOLOGIES
64. 65. 66. 67. 68. 69. 70. 71. 72. 73. 74. 75. 76. 77. 78. 79. 80. 81. 82. 83. 84. 85. Low-Power Rotary Clock Array Design Two New Techniques Integrated for Energy-Efficient TLB Design SAMBA-Bus: A High Performance Bus Architecture for System-onChips Floating-Point Divider Design for FPGAs VLSI-Efficient Scheme and FPGA Realization for Robotic Mapping in a Dynamic Environment A Methodology for the Evaluation of a GPS Receiver Performance in Telematics Applications Concurrent Error Detection in ReedSolomon Encoders and Decoders Neural Network based Artificial bandwidth expansion of Speech An Energy-Efficient Reconfigurable Base band Processor for Wireless Communications A VLSI Architecture for Image Registration in Real Time Mobile Radio Channel State Prediction for Power Control in WCDMA Mobile Network An Efficient Approach to On-Chip Logic Minimization Low-Power Buffer Management for Streaming Data Discrete wavelet Transform for Image compression Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores A Lossless Data Compression and Decompression Algorithm and Its Hardware Architecture High-Speed Interpolation Architecture for Soft-Decision Decoding of ReedSolomon Codes Fast Decimal Floating-Point Division Minimal Energy Asynchronous Dynamic Adders Retargetable pipeline hazard detection for partially bypassed processors Scenario-oriented design for single-chip heterogeneous multiprocessors IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2007 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006

TRICHY: 168/ 3, 1st Floor, JJ Tower, Near STAR Theater, Madurai road, Trichy-8 Ph:0431 4011860,61 CHENNAI :No 91,2nd Floor,1st Avenue, Ashok Nagar,Chennai-83 Ph: 044 - 64627827 MOBILE: 9444108716 , 9994603786 , 9894147084

SLITE TECHNOLOGIES
86. 87. 88. 89. 90. 91. 92. 93. 94. 95. 96. 97. 98. 99. 100. 101. 102. 103. 104. Low-power high-performance NAND match line content addressable memories Energy efficient watermarking on mobile devices using proxy-based partitioning Design of flexible GF(2/sup m/) elliptic curve cryptography processors A low-power ROM using single charge-sharing capacitor and hierarchical bit line Energy-efficient soft error-tolerant digital signal processing VLSI implementation of low-power high-quality color interpolation processor for CCD camera FPGA based space vector PWM control IC for Three Phase Induction Motor Drive The Implementation Of A High Speed Adaptive FIR Filter On A FPGA Sequential Element Design With Built-In Soft Error Resilience Induction Motor Speed Control using Fuzzy Logic Controller( 2006 WORLD ENFORMATIKA SOCIETY) Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison Space Vector Modulation Applied to Three-Phase Three-Switch TwoLevel Unidirectional PWM Rectifier traction motors A Lossless Data Compression and Decompression Efficient Inner Receiver Design for OFDM-based WLAN Systems Algorithm and Architecture Nonlinear Behaviors of First and Second-Order Complex Digital Filters With Twos Complement Arithmetic
Application of DDR Controller for High-speed Data Acquisition Board Robust UART based RRS filter for better noise performance Shift Register based data transposition for cost effective DCT ( Discrete Cosine Transform) Efficient Space- Time Signal Processing techniques for WCDMA Communication

IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE 2006 IEEE IEEE IEEE IEEE

TRICHY: 168/ 3, 1st Floor, JJ Tower, Near STAR Theater, Madurai road, Trichy-8 Ph:0431 4011860,61 CHENNAI :No 91,2nd Floor,1st Avenue, Ashok Nagar,Chennai-83 Ph: 044 - 64627827 MOBILE: 9444108716 , 9994603786 , 9894147084