5 4 3 2 1

DOTHAN/ALVISO-GM(PM)/ATI M24 BLOCK DIAGRAM

SUB-BOARD CLOCK
CPU FAN & THERMAL
SENSOR
GENERATOR DOTHAN ADT7473
D
ICS954213 PAGE 6
478 uFCPGA D
PAGE 7
INSTANT KEY PAGE 3,4,5
BOARD
CRT CN PAGE 24
FSB
ATI
AUDIO DJ
BOARD
TV OUT PAGE 24 M24-C PCI-E

PAGE 14,15,16,17
ALVISO DDRII SDRAM 400/533MHz
LCD CN & INVERTER PAGE 25 GM(PM)CH
MIC 1257 uFCBGA
BOARD
ONBOARD
PAGE 8,9,10,11,12,13 ONBOARD STANDARD
DDR
DDRII DDRII
64MB PAGE 18,19
DMI 512MB PAGE 20,21 DIMM PAGE 22,23

C PAGE 42 C
RTC CN
SM_BUS
PAGE 42

PAGE 44 POWER UP
DC IN
POWER USB 2.0 ICH6-M RESET
CIRCUIT PAGE 29
609 uFCBGA
PCI BUS 3.3V, 33MHz
CMOS
VCORE MODULE IDE
PAGE 48

PAGE 33
BUS PAGE 20,21,22

CARDBUS LAN MINI-PCI

SYSTEM 3VO/5VO
RICOH R5C841 REALTEK 8101L 802.11 a/b/g
PAGE 49
PAGE 34,35,36 PAGE 38 PAGE 40
BLUETOOTH AZALIA
1.2V/1.5V/1.8V/1.05V MODULE LPC ADI AD1986A
PAGE 50 PAGE 33
33MHz PAGE 30
1394 LAN IO
PAGE 36 PAGE 39

B
1.5VA/0.9VS B
PAGE 51
USB 2.0 * 4 PHONE
PAGE 43
JACK
BATLOW/SD# KEYBOARD FWH PAGE 31 ONE
PAGE 52
CONTROLLER PAGE 44
PCMCIA
MITSUBISHI M38857 SLOT
CHARGE DEBUG PAGE 45
AUDIO PAGE 37
PAGE 53
PORT AMP &
PAGE 5 TPM INT.
BAT CON CARDBUS
PAGE 54 PAGE 44 SPK PAGE 32
POWER
PIC16C54 HDD CN INTERNAL SWITCH
PAGE 55
PAGE 41
KB & TP MIC PRE R5531
PAGE 46
AMP & MIC PAGE 37

LOAD Switch JACK

PAGE 56
PAGE 33
ODD CN 4 IN 1 MEMORY
VGA VCORE PAGE 41 Audio DJ CARD
PAGE 57

A MDC READER A
HEARDER SD/MMC/MS/XD
PAGE 47 PAGE 39 PAGE 37

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan LIBRARY DATE :
2.0 SHEET 1 OF 61 BLOCK DIAGRAM
5 4 3 2 1
A B C D E

PAGE Content PAGE Content

M9V PAGE REF.
1 Block Diagram 53 CHARGE
2 Page Reference 54 BAT CONNECT
1
3 Dothan Main (1) 55 PIC16C54 & PRO_CIR 1
4 Dothan Power & GND (2) 56 LOAD SWITCH
5 Cpu Cap & Debug Card 57 M24-C - VGA VCORE
6 Clock Generator 58 ◆ Power Flowchart
7 Fan & Thermal Sensor 59 Power History
8 Alviso GM(PM)CH - Host (1) 60 Revision History
9 Alviso GM(PM)CH - PCI-E (2)
10 Alviso GM(PM)CH - DDR (3)
11 Alviso GM(PM)CH - Power (4)
12 Alviso GM(PM)CH - GND (5)
13 GM(PM)CH Strapping
14 M24-C - Main (1)
2 15 M24-C - Memory Interface (2) 2

16 M24-C - Power (3)

17 M24-C - Straping (4)
18 M24-C - DDR Memory A
19 M24-C - DDR Memory B
20 DDR2 (1)
21 DDR2 (2)
22 Standard DDR2 SO-DIMM
23 DDR2 Address Termination
24 CRT & TV OUT
25 LCD & Inverter
3
26 ICH6M - LPC & IDE (1) 3
27 ICH6M - USB & PCI-E & PMIO (2)
28 ICH6M - PWR & GND (3)
29 Reset Circuit
30 Azalia AD1986A
31 PHONE JACK
32 Audio AMP & INT SPK
33 MIC PRE-AMP & MIC JACK & ExtCN
34 CardBus RICOH 5C841/PCI_B
35 CardBus RICOH 5C841/PCI_A
36 CardBus RICOH 5C841/PCI_C
37 Cardbus & CardReader & PwrSw
4 38 LAN RealTek-RTL8101L 4

39 LAN IO & MDC

40 MiniPCI
41 HDD CN & CDROM CN
42 SM_BUS & RTC CN
43 4*USB2.0 Conn
44 DCIN JACK & FWH & TPM
45 Keyboard Controller (M3885)
46 LEDs & Internal KB & TP
47 Audio DJ
48 VCORE
5
49 SYSTEM 5
50 2.5V & 1.5V & 1.8V & 1.05V
51 1.5VA & DDR2 & 3VALWAYS_P
52 BATLOW/SD#
REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
ASUS PROJECT: Obi-Wan 2.0 SHEET 2 OF 61 PAGE REFERENCE LIBRARY DATE :

WWW.AliSaler.Com
A B C D E
5 4 3 2 1

+VCCP
H_D#[0:63] 8

1
R623
U49A
8 H_A#[3:16]
U49B 56Ohm H_D#15 C25 Y25 H_D#47
H_A#16 H_D#14 D[15]# D[47]# H_D#46
AA2 A[16]# ADS# N2 H_ADS# 8 E23 D[14]# D[46]# AA26
H_A#15 TP91 H_D#13 H_D#45

2
Y3 A[15]# PRDY# A10 1 B23 D[13]# D[45]# Y23
H_A#14 AA3 B10 1 TP90 H_D#12 C26 V26 H_D#44
H_A#13 A[14]# PREQ# H_D#11 D[12]# D[44]# H_D#43
U1 A[13]# E24 D[11]# D[43]# U25
H_A#12 Y1 L1 H_D#10 D24 V24 H_D#42
A[12]# BNR# H_BNR# 8 D[10]# D[42]#

DATA GROUP 0
H_A#11 H_D#9 H_D#41

2
Y4 J3 H_BPRI# 8 B24 U26

ADDRESS GROUP 0
D H_A#10 A[11]# BPRI# H_D#8 D[9]# D[41]# H_D#40 D
W2 C20 AA23

DATA GROUP
H_A#9 A[10]# H_D#7 D[8]# D[40]# H_D#39
T4 A[9]# B20 D[7]# D[39]# R23
H_A#8 W1 A7 1 TP89 H_D#6 A21 R26 H_D#38
H_A#7 A[8]# DBR# H_D#5 D[6]# D[38]# H_D#37
V2 A[7]# B26 D[5]# D[37]# R24
H_A#6 R3 H_D#4 A24 V23 H_D#36
H_A#5 A[6]# H_D#3 D[4]# D[36]# H_D#35
V3 A[5]# B21 D[3]# D[35]# U23
H_A#4 U4 L4 H_D#2 A22 T25 H_D#34
A[4]# DEFER# H_DEFER# 8 D[2]# D[34]#
H_A#3 P4 H2 H_D#1 A25 AA24 H_D#33
A[3]# DRDY# H_DRDY# 8 D[1]# D[33]#
U3 M2 H_D#0 A19 Y26 H_D#32
8 H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# 8 D[0]# D[32]#
H_REQ#4 T1 D25 T24
REQ[4]# 8 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 8
H_REQ#3 P1 C23 W25
REQ[3]# 8 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 8
H_REQ#2 T2 C22 W24
REQ[2]# +VCCP 8 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 8
H_REQ#1 P3
H_REQ#0 REQ[1]# H_D#31 H_D#63
R2 REQ[0]# K25 D[31]# D[63]# AF26
N4 H_D#30 N25 AF22 H_D#62
H_BREQ#0 8

CONTROL
BR0# H_D#29 D[30]# D[62]# H_D#61
8 H_REQ#[0:4] H26 D[29]# D[61]# AF25
H_D#28 M25 AD21 H_D#60
H_IERR# R616 D[28]# D[60]#
8 H_A#[17:31] IERR# A4 1 2 56Ohm H_D#27 N24 D[27]# D[59]# AE21 H_D#59
H_D#26 L26 AF20 H_D#58

3
D[26]# D[58]#

DATA GROUP 1
H_A#31 AF1 H_D#25 J25 AD24 H_D#57
H_A#30 A[31]# H_D#24 D[25]# D[57]# H_D#56

DATA GROUP
AE1 A[30]# INIT# B5 H_INIT# 26 M23 D[24]# D[56]# AF23
H_A#29 AF3 H_D#23 J23 AE22 H_D#55
H_A#28 A[29]# +VCCP H_D#22 D[23]# D[55]# H_D#54
AD6 G24 AD23
ADDRESS GROUP 1
H_A#27 A[28]# H_D#21 D[22]# D[54]# H_D#53
AE2 A[27]# LOCK# J2 H_LOCK# 8 F25 D[21]# D[53]# AC25
H_A#26 AD5 H_D#20 H24 AC22 H_D#52
H_A#25 A[26]# H_D#19 D[20]# D[52]# H_D#51
AC6 A[25]# M26 D[19]# D[51]# AC20
H_A#24 AB4 H_D#18 L23 AB24 H_D#50
H_A#23 A[24]# R631 1 D[18]# D[50]#
AD2 A[23]# 2 54.9Ohm H_D#17 G25 D[17]# D[49]# AC23 H_D#49
H_A#22 AE4 @ H_D#16 H23 AB25 H_D#48
H_A#21 A[22]# D[16]# D[48]#
AD3 A[21]# RESET# B11 H_CPURST# 8 8 H_DINV#1 J26 DINV[1]# DINV[3]# AD20 H_DINV#3 8
H_A#20 AC3 L2 H_RS#2 K24 AE24
A[20]# RS[2]# 8 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 8
H_A#19 AC7 K1 H_RS#1 L24 AE25
C A[19]# RS[1]# 8 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 8 C
H_A#18 AC4 H1 H_RS#0
H_A#17 A[18]# RS[0]# SOCKET479P
AF4 A[17]# H_RS#[0:2] 8
8 H_ADSTB#1 AE5 ADSTB[1]# TRDY# M3 H_TRDY# 8

HIT# K3 H_HIT# 8
8 H_DPWR# C19 DPWR# HITM# K4 H_HITM# 8
SOCKET479P

U49C
6 CLK_CPU_BCLK B15 BCLK[0]
B14
HOSTCLK

6 CLK_CPU_BCLK# BCLK[1]
R634 1 2 49.9Ohm A16 AB1 H_COMP3 R216 1 2 54.9Ohm R5,R7(COMP3,COMP1) should be placed within 0.5" R170 0Ohm @
R635 1 ITP_CLK[0] COMP[3] H_COMP2
2 49.9Ohm A15 ITP_CLK[1] COMP[2] AB2 R215 1 2 27.4Ohm of processor pin. Traces shold be 55 ohm +/-15%. 1 2 +V1.8S_PROC_VCCA1
P26 H_COMP1 R661 1 2 54.9Ohm
COMP[1]

1
C2 P25 H_COMP0 R660 1 2 27.4Ohm R6,R8(COMP2,COMP0) should be placed within 0.5" C146
26 H_A20M# A20M# COMP[0]
26 H_FERR# D3 FERR# of processor pin. Traces shold be 27.4 ohm +/-15%.
+V1.8S_PROC
LEGACY CPU

A3 1UF/6.3V @
26 H_IGNNE# IGNNE#

2
26 H_DPSLP# B7 DPSLP# BPM[3]# C9
A6 A9 R581 0Ohm @ R222 0Ohm @
8,26 H_CPUSLP# SLP# BPM[2]# +VCCP
26 H_INTR D1 LINT0 BPM[1]# B8 +1.8VS 1 2 1 2 +V1.8S_PROC_VCCA2
5 H_NMI D4 LINT1 BPM[0]# C8

1
B4 C670 C672 C162
26 H_SMI# SMI#
1
R618 1 2 0Ohm C6 R176 0Ohm
26 H_STPCLK# STPCLK#
1 2 0.01UF/10V 10UF/6.3V 1UF/6.3V @
+1.5VS
R665

2
26 H_PWRGD E4 PWRGOOD GTLREF[3] AC1
G1 1KOhm R664 0Ohm @
GTLREF[2] H_DPRSTP# 26
H_VID5 H4 E26 1 2
VID[5] GTLREF[1] +V1.8S_PROC_VCCA3
H_VID4 GT_REF0
2

G4 VID[4] GTLREF[0] AD26

1
H_VID3 G3 C680
VID[3]
1

B H_VID2 F3 B
H_VID1 VID[2] R666 0.1uF/10V @
F2 VID[1]
H_VID0 R617 1 2 1KOhm @ 2KOhm +VCCP +VCCP +VCCP +VCCP

2
E2 VID[0] TEST1 C5
F23 R273 1 2 1KOhm @
TEST2
MISC

+VCCP

1
+V1.8S_PROC_VCCA3
2

AC26 VCCA[3]
+V1.8S_PROC_VCCA2 N1 R251 R640 R620 R223
+V1.8S_PROC_VCCA1 VCCA[2] R630 1
B1 VCCA[1] TCK A13 2 27Ohm
+V1.8S_PROC F26 C12 R624 1 2 150Ohm 200Ohm 56Ohm 56Ohm 56Ohm
VCCA[0] TDI R629 1
TDO A12 2 54.9Ohm @ @ @

2
7 CPU_THERM_DA B18 THERMDA TMS C11 H_TMS 5
A18 B13 H_PWRGD
7 CPU_THERM_DC THERMDC TRST# H_TRST# 5
C17 H_PROCHOT_S#
9,26 PM_THRMTRIP# H_PROCHOT_S# THERMTRIP# H_DPSLP#
B17 PROCHOT#
AE7 R252 1 2 54.9Ohm @ H_DPRSTP#
R218 1 VCCSENSE
48 PM_PSI# 2 0Ohm E1 RSVD5
R636 1 2 0Ohm C16
6 CPU_BSEL0 RSVD4
C3 RSVD3
R632 1 2 0Ohm C14
6 CPU_BSEL1 RSVD2
AF7 RSVD1
B2 AF6 R247 1 2 54.9Ohm @
RSVD0 VSSSENSE
SOCKET479P

H_VID5 RN6A 1 2
0Ohm VR_VID5 48
H_VID4 RN6B 3 4
0Ohm VR_VID4 48
H_VID3 RN6C 5 6
0Ohm VR_VID3 48
H_VID2 RN6D 7 8
0Ohm VR_VID2 48
A H_VID1 R220 1 2 0Ohm A
VR_VID1 48
H_VID0 R219 1 2 0Ohm VR_VID0 48

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan DOTHAN - MAIN (1) LIBRARY DATE :
2.0 SHEET 3 OF 61
5 4 3 2 1
5 4 3 2 1

+VCCP +VCORE

AD25
AD22
AD19
AD17
AD15
AD13
AD11
AE26
AE23
AE20
AE18
AE16
AE14
AE12
AE10
AF24
AF21
AF19
AF17
AF15
AF13
AF11

AD9
AD7
AD4
AD1
AE8
AE6
AE3
AF9
AF5
AF2
U49D U49E
D6 A2 AC24

VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VCC1 VSS1 VSS160
W4 VCCQ[1] VCC2 D8 A5 VSS2 VSS159 AC21
P23 VCCQ[0] VCC3 D18 A8 VSS3 VSS158 AC18
VCC4 D20 A11 VSS4 VSS157 AC16
D D22 A14 AC14 D
VCC5 VSS5 VSS156
VCC6 E5 A17 VSS6 VSS155 AC12
VCC7 E7 A20 VSS7 VSS154 AC10
VCC8 E9 A23 VSS8 VSS153 AC8
D10 VCCP1 VCC9 E17 A26 VSS9 VSS152 AC5
D12 VCCP2 VCC10 E19 B3 VSS10 VSS151 AC2
D14 VCCP3 VCC11 E21 B6 VSS11 VSS150 AB26
D16 VCCP4 VCC12 F6 B9 VSS12 VSS149 AB23
E11 VCCP5 VCC13 F8 B12 VSS13 VSS148 AB21
E13 VCCP6 VCC14 F18 0.745V - 1.356V(+/- 1.5%) B16 VSS14 VSS147 AB19
1.0V - 1.2V(+/- 5%) E15 VCCP7 VCC15 F20 C0: 27 A B19 VSS15 VSS146 AB17
S0-S1M: 2.5 F10 VCCP8 VCC16 F22 B22 VSS16 VSS145 AB15
F12 G5 C3: 7.59A B25 AB13
A(CPU,MCH,ICH) VCCP9 VCC17 VSS17 VSS144
F14 VCCP10 VCC18 G21 C4: 0.9A C1 VSS18 VSS143 AB11
F16 VCCP11 VCC19 H6 C4 VSS19 VSS142 AB9
K6 VCCP12 VCC20 H22 C7 VSS20 VSS141 AB7
L5 J5 C10 AB5
L21
M6
M22
VCCP13
VCCP14
VCCP15
VCCP16
VCC VCC21
VCC22
VCC23
VCC24
J21
K22
U5
C13
C15
C18
VSS21
VSS22
VSS23
VSS24
VSS140
VSS139
VSS138
VSS137
AB3
AA25
AA22
N5 VCCP17 VCC25 V6 C21 VSS25 VSS136 AA20
N21 VCCP18 VCC26 V22 C24 VSS26 VSS135 AA18
P6 W5 D2 AA16
P22
R5
R21
VCCP19
VCCP20
VCCP21
VCCP22
VCC27
VCC28
VCC29
VCC30
W21
Y6
Y22
D5
D7
D9
VSS27
VSS28
VSS29
VSS30
GND VSS134
VSS133
VSS132
VSS131
AA14
AA12
AA10
T6 VCCP23 VCC31 AA5 D11 VSS31 VSS130 AA8
T22 VCCP24 VCC32 AA7 D13 VSS32 VSS129 AA6
U21 VCCP25 VCC33 AA9 D15 VSS33 VSS128 AA4
VCC34 AA11 D17 VSS34 VSS127 AA1
VCC35 AA13 D19 VSS35 VSS126 Y24
VCC36 AA15 D21 VSS36 VSS125 Y21
C C
VCC37 AA17 D23 VSS37 VSS124 Y5
VCC38 AA19 D26 VSS38 VSS123 Y2
VCC39 AA21 E3 VSS39 VSS122 W26
VCC40 AB6 E6 VSS40 VSS121 W23
VCC41 AB8 E8 VSS41 VSS120 W22
VCC42 AB10 E10 VSS42 VSS119 W6
VCC43 AB12 E12 VSS43 VSS118 W3
VCC44 AB14 E14 VSS44 VSS117 V25
VCC45 AB16 E16 VSS45 VSS116 V21
VCC46 AB18 E18 VSS46 VSS115 V5
VCC47 AB20 E20 VSS47 VSS114 V4
VCC48 AB22 E22 VSS48 VSS113 V1
VCC49 AC9 E25 VSS49 VSS112 U24
VCC50 AC11 F1 VSS50 VSS111 U22
VCC51 AC13 F4 VSS51 VSS110 U6
VCC52 AC15 F5 VSS52 VSS109 U2
VCC53 AC17 F7 VSS53 VSS108 T26
VCC54 AC19 F9 VSS54 VSS107 T23
VCC55 AD8 F11 VSS55 VSS106 T21
VCC56 AD10 F13 VSS56 VSS105 T5
VCC57 AD12 F15 VSS57 VSS104 T3
VCC58 AD14 F17 VSS58 VSS103 R25
VCC59 AD16 F19 VSS59 VSS102 R22
AD18 F21 R6
AF18 VCC72
AF16 VCC71
AF14 VCC70
AF12 VCC69
AF10 VCC68
AF8 VCC67
AE19VCC66
AE17VCC65
AE15VCC64
AE13VCC63
AE11VCC62
AE9 VCC61

VCC60 VSS60 VSS101

F24 VSS61 VSS100 R4
G2 VSS62 VSS99 R1
G6 VSS63 VSS98 P24
SOCKET479P G22 P21

VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS64 VSS97

M21
M24
G23
G26

H21
H25

N22
N23
N26
K21
K23
K26
SOCKET479P

L22
L25
J22
J24

M1
M4
M5
H3
H5

N3
N6
K2
K5

P2
P5
L3
L6
J1
J4
J6
B B

+VCCP
+VCCP (CPU) Decoupling Capacitor
(Place near CPU)
1

+
1

CE3 C251 C189 C187 C249 C252 C250 C253 C185 C188 C226 C241 C186
0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U @ @ 0.1U
150U/4.0V X7R X7R X7R X7R X7R X7R X7R X7R X7R 10uF/10V 10uF/10V X7R
2

A A
Not included in the Intel Checklist

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan DOTHAN - POWER&GND (2) LIBRARY DATE :
2.0 SHEET 4 OF 61

WWW.AliSaler.Com 5 4 3 2 1
5 4 3 2 1

H1 H2
HOLE_NPTH HOLE_NPTH

1
+VCORE +VCORE
CPU VCORE Decoupling Capacitor
D D

H7 H10 H5 H12 H17

1
C244 C204 C666 C208 C640 C654 C635 C248 C667 C205 c114d94 c114d94 c114d94 c114d94 c114d94
1

1
+ + +
C230 C214 C235 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V

1
470UF/2.5V 330UF/2V @ 220U/2.5V
2

1
C245 C203 C664 C207 C227 C637 C649 C668 C638 C651

10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V
H20 H21 H23 H6 H9

2
c114d94 c114d94 c114d94 c114d94 c114d94

1
1

1
C209 C652 C243 C242 C653 C206 C228 C636 C665 C246

10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V

2
H18 H22

1
C247 C650 C229 C663 C639 c114d94 c114d94

10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V

1
C C

SR 1.0 -> ER 1.1

ER 1.1 -> PR 2.0

H16 H13 H14 H15 H8 H3

H26 H27 C154D134 C154D134 C154D134 C154D134

1
AM20-30 AM20-30
AM20-30 AM20-30

For MDC
H25 H11 H19
H4 H24 C94D94N C94D94N C94D94N
c114d94 O142X95DO142x95N

1
+5V
10

U33B U68 H28

37 CBDEBUGEN# SCREW_HOLE
12 9 1 24
PR

R423 D Q BEA# Vcc

35,37 CLKRUN#/IOIS16# 2 B0 B9 23
1 2 11 8 +3VALWAYS 3 22
29,34,38,45 PCIRSTNS#_3 CK Q# 6 CLK_DBPCI A0 A9

1
26,44,45 LFRAME# 4 A1 A8 21
0Ohm +3V 7 14 5 20
35,37 CAUDIO/SPKR_IN#/BVD2
CLR

GND VCC B1 B8
1

B 6 19 B
35,37 CPERR#/A14 B2 B7 CBLOCK#/A19 35,37 NMI#/SMI# NMI
C410 RR1 R444 7 18 1 2 1 TP112
26,44,45 LAD0 A2 A7
2 1 1 2 74LV74A 8 17 R876 0Ohm @
26,44,45 LAD1 DIS_SYSBIOS#_FWH 44
13

0Ohm A3 A6
35,37 RFU/D2 9 B3 B6 16 CSERR#/WAIT# 35,37
1UF/10V @ 10KOhm @ 10 15
35,37 RFU/D14 B4 B5 RFU/A18 35,37
2

26,44,45 LAD2 11 A4 A5 14 LAD3 26,44,45

U28 12 13
GND BEB#
35,37 CCD1# 1 A VCC 5

35,37 CSTSCHG/STSCHG#/BVD1 2 B PI5C3384

3 GND 4
2

Y CBDEBUGEN#
R445 NC7SZ00M5

1MOhm
1

+VCCP
R256
H_NMI 3
3 H_TMS 1 2

2
39.2Ohm R253

R257 0Ohm
3 H_TRST# 1 2

1
NMI_ICH 26
680Ohm

A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan LIBRARY DATE :
2.0 SHEET 5 OF 61 CPU CAPS& DEBUG CARD
5 4 3 2 1
5 4 3 2 1

+3VS +3VS_CLK
L39 120Ohm/100Mhz
1 2
BSEL1 BSEL0

1
C273 C290 C270 C287 C288 C717 C714 C720 C722

FSLB FSLC HOST CLOCK 0.1UF 0.1UF 10uF/10V 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

2
D
0 1 100 (DEFAULT) L87 D
1 2
0 0 133 120Ohm/100Mhz

+3VS_CLKVDD1
PLACE termination close to source IC
+VCCP +VCCP

1
C705 C704 C713

2
C703 C712
1

R696 R706 0.1UF 0.1UF 10uF/10V CLK_CPU_BCLK R352 2 1 49.9Ohm

R726 R725 0.1UF 10uF/10V

2
1

1
R353 1KOhm C711 C715 +3VS_CLK U16 2.2OHM 1Ohm CLK_CPU_BCLK# R351 1 2 49.9Ohm

2
1KOhm 1KOhm @ 1 2

VDDPCI

VDDPCI0
MCH_SEL1 9
10uF/10V 0.1UF CLK_MCH_BCLK R350 1 2 49.9Ohm

1
FSLB
2

2
CPU_BSEL1 3
13 CLK_MCH_BCLK# R349 1 2 49.9Ohm
FSLC VDD48
CPU_BSEL0 3 22 VDDSRC1
29 VDDSRC2
1

1 2 33 48 VDD_REF_CR C719 1 2 0.1UF

MCH_SEL0 9 VDDSRC3 VDDREF
R716 R715 X5 R315 DREFCLK R286 1 2 49.9Ohm
R354 1KOhm 1 2 2.2OHM
1KOhm @ 1KOhm 2 1 42 18 R294 1 2 0Ohm DREFCLK# R285 1 2 49.9Ohm
VDDCPU PCI_SRC_STOP# STP_PCI# 26
14.318MHZ 10 R690 1 2 0Ohm
CPU_STOP# STP_CPU# 26,48
1

1
C267 C271 +3VS_CLKA
2

37 VDDA
41 CPU1 1 TP52 CLK_PCIE_ICH R291 2 1 49.9Ohm
33PF/50V 33PF/50V CPUCLKT1 CPU1# TP51
38 GNDA CPUCLKC1 40 1
CLK_PCIE_ICH# R288 1 2 49.9Ohm
2

2
44 CPU0 R335 1 2 33Ohm
XIN_CLKGEN CPUCLKT0 CLK_CPU_BCLK 3
SR 1.0 -> ER 1.1 50 43 CPU0# R334 1 2 33Ohm
X1 CPUCLKC0 CLK_CPU_BCLK# 3
CLK_MCH_3GPLL R348 2 1 49.9Ohm
XOUT_CLKGEN 49
C X2 R333 1 C
CPUCLKT2_ITP/SRCCLKT5 35 2 33Ohm CLK_MCH_BCLK 8
CLK_MCH_3GPLL# R347 1 2 49.9Ohm
R295 1 2 33Ohm 17 34 R332 1 2 33Ohm
14 CLK_ATI27 27MHZ CPUCLKC2_ITP/SRCCLKC5 CLK_MCH_BCLK# 8
R299 1 2 33Ohm 11 32 PCIE5 R331 1 2 33Ohm CLK_PCIE_PEG R929 2 1 49.9Ohm
27 CLK_USB48 48MHz SRCCLKT4 CLK_MCH_3GPLL 9
R692 1 2 1KOhm 31 PCIE#5 R330 1 2 33Ohm
+3VS_CLK 33PCIF5 SRCCLKC4 CLK_MCH_3GPLL# 9
R301 1 2 33Ohm 5 CLK_PCIE_PEG# R930 1 2 49.9Ohm
5 CLK_DBPCI FSLA/PCICLK5
SRCCLKT3_SATA 27
R302 1 2 33Ohm 33PCIF4 4 28
44 CLK_FWHPCI PCICLK4 SRCCLKC3_SATA ER1.1 -> PR2.0 (Obi-Wan)
R303 1 2 33Ohm 33PCIF3 3 25 PCIE3 R290 1 2 33Ohm
45 CLK_KBCPCI PCICLK3 SRCCLKT2 CLK_PCIE_ICH 27
26 PCIE#3 R289 1 2 33Ohm
SRCCLKC2 CLK_PCIE_ICH# 27
R342 1 2 33Ohm 33PCIF2 56
34 CLK_CBPCI PCICLK2
23 PCIE2 R293 1 2 33Ohm
SRCCLKT1 CLK_PCIE_PEG 14
R341 1 2 33Ohm 33PCIF1 55 24 PCIE#2 R292 1 2 33Ohm
40 CLK_MINIPCI PCICLK1 SRCCLKC1 CLK_PCIE_PEG# 14
R340 1 2 33Ohm 33PCIF0 54 20 PCIE1 1 TP48
38 CLK_LANPCI PCICLK0 SRCCLKT0
21 PCIE#1 1 TP47
R300 1 33Ohm 33PCIKF1 SRCCLKC0
27 CLK_ICHPCI 2 9 PCICLK_F1
R691 1 2 10KOhm 8 36
+3VS_CLK ITP_EN/PCICLK_F0 DOC_2
DOC_1 19
SMBCK_3S R336 1 2 33Ohm 46
7,22,42 SMBCK_3S SCLK
SMBDA_3S R337 1 2 33Ohm 47
7,22,42 SMBDA_3S SDATA
14 DOT96 R298 1 2 33Ohm
DOTT_96MHz DREFCLK 9
R919 1 2 33Ohm IREF 39 15 DOT96# R297 1 2 33Ohm
44 CLK_TPMPCI IREF DOTC_96MHz DREFCLK# 9
@
2 16 VTT_PWRGD# R296 1 2 0Ohm @
GND1 VTT_PWRGD#/PD CLK_PWR_GD# 48
2

6 GND2
SR 1.0 -> ER 1.1 R705 12 GND3
C261

C262

C263

C266

C295

C294

C293

C265

C289

C292

475Ohm 30 GND4 REF1/FSLB 52 R338 1 2 680Ohm FSLB

45 53 R339 1 2 33Ohm
GND5 REF0/FSLC CLK_ICH14 26
2

B 51 B
GND6 R710 1 2 680Ohm FSLC
1

ICS954213
10PF

10PF

10PF

10PF

10PF

10PF

10PF

10PF

10PF

10PF
1

ER1.1 -> PR2.0 (Obi-Wan)

+3VS
2

+3VS
R737
10KOhm
2

R743
VTT_PWRGD#
1

1KOhm
3
R746 R742 C
1

1 2 1 2 1 B Q87
9,26,29,48,55 VRM_PWRGD
0Ohm 20KOhm E MMBT3904-7
2

A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan CLOCK GENERATOR LIBRARY DATE :
2.0 SHEET 6 OF 61

WWW.AliSaler.Com 5 4 3 2 1
A B C D E

1 1

FAN +5VS_FAN1

+5VS +5VS Q76 +5VS_FAN1

1
C696 2 1 1000PF SI2305DS
R657 @ @

1
2 3

3 D
10KOhm R694

2
@ +12V TP96
+

G
1
U51 10KOhm C707 D11

11
D41
SR 1.0 -> ER 1.1 3 A+ + VCC 8 @ C164
R700 D40 0.1UF 100UF/6.3V 1N4148W-A2

1
1 2 1
FAN1 1 2 A- - AO @ @ @

2
2 1 2

1
+5VS C697 +5VS R693 1SS355

1
300KOhm RB751V_40@ 5 B+ + 1 2 @

1
TP88 @ C698 BO 7 0.1UF
D42
6 B- - @ 10KOhm

2
1 GND 4
10UF/6.3V R675 1 2 0Ohm OTP# @ 2 1
CN21 @ @ LM358MX

2
5 @ 1SS355
NC1 @
1 1
FAN_SPD 2 2 +5VS
3 3
2 PWM1 4 2
4
NC2 6

2
WtoB_CON_4P R697

10KOhm +3V
@ R702 0Ohm
@ 2

1
1
OTP#
R699 0Ohm @ ER 1.1 -> PR 2.0 WatchDog normal: H during post BIOS set L

2
1 2 3 Q81
45 FAN_DA_PWM D

1
R734 R735
C710

3
0.1UF 11 +VCORE 100KOhm 100KOhm 3 D
@

2
G
S 2
2N7002 @ Q86

1
11

2
+3VS G NDS351N
2 S

3
3
D

2
OTP#_P 11 Q83
29,54 OTP#_P
2

G 2N7002
2 S

1
R698 R712 R711 C716
R704

2
3 10KOhm 10KOhm 10KOhm 0.1uF/10V 3
SR 1.0 -> ER 1.1 1MOhm

2
SR 1.0 -> ER 1.1
1

FAN_SPD

1
U54
1 16 R902 +3V
6,22,42 SMBCK_3S SCL SDA SMBDA_3S 6,22,42 PWM1
2 GND PWM1/XTO 15 2 1
3 VCC Vccp 14 1 2
R707 0Ohm 4 13 R701 0Ohm 0Ohm
TACH3 D1+ CPU_THERM_DA 3

2
1 2 5 12 OTP#_P
26 PM_THRM# PWM2/SMBALERT# D1- CPU_THERM_DC 3

1
Q82 R740

1
6 TACH1 D2+ 11

G
7 TACH2 D2- 10

3
TP97 470KOhm 3

2 S

3
1 8 PWM3 TACH4/GPIO/THERM#/SMBALERT# 9 1 2 2 3 THERM_PRO# 29 D

D
R714 0Ohm Q85
ADT7473ARQZ

1
2N7002
2N7002
45 WATCHDOG 11
C718 G
2 S

1
2 1 C743
TP54

2
2200PF/10V 1 1UF/10V

2
TPC32t

VGA_THERM_DA 14
VGA_THERM_DC 14

4
C721 4
2 1

2200PF/10V ER 1.1 -> PR 2.0

3 Q118
C
1 B

E
2 SMBT3904 @

P/N:07-003000510

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan FAN & THERMAL SENSOR LIBRARY DATE :
2.0 SHEET 7 OF 61
A B C D E
5 4 3 2 1

D D
+VCCP

3 H_D#[0..63]
R611 54.9Ohm H_A#[3..31] 3
1 2 H_XSCOMP U48D
H_D#0 E4 G9 H_A#3
R615 54.9Ohm H_D#1 HD0# HA3# H_A#4
E1 HD1# HA4# C9
1 2 H_YSCOMP H_D#2 F4 E9 H_A#5
H_D#3 HD2# HA5# H_A#6
H7 HD3# HA6# B7
H_D#4 E2 A10 H_A#7
H_D#5 HD4# HA7# H_A#8
F1 HD5# HA8# F9
H_D#6 E3 D8 H_A#9
H_D#7 HD6# HA9# H_A#10
D3 HD7# HA10# B10
H_D#8 K7 E10 H_A#11
H_D#9 HD8# HA11# H_A#12
F2 HD9# HA12# G10
H_D#10 J7 D9 H_A#13
H_D#11 HD10# HA13# H_A#14
J8 HD11# HA14# E11
H_D#12 H6 F10 H_A#15
H_D#13 HD12# HA15# H_A#16
F3 HD13# HA16# G11
H_D#14 K8 G13 H_A#17
H_D#15 HD14# HA17# H_A#18
H5 HD15# HA18# C10
H_D#16 H1 C11 H_A#19
R610 24.9Ohm H_D#17 HD16# HA19# H_A#20
H2 HD17# HA20# D11
1 2 H_XRCOMP H_D#18 K5 C12 H_A#21
H_D#19 HD18# HA21# H_A#22
K6 HD19# HA22# B13
H_D#20 J4 A12 H_A#23
R628 24.9Ohm H_D#21 HD20# HA23# H_A#24
G3 HD21# HA24# F12
1 2 H_YRCOMP H_D#22 H3 G12 H_A#25
H_D#23 HD22# HA25# H_A#26 +VCCP
J1 HD23# HA26# E12
C H_D#24 H_A#27 C
L5 HD24# HA27# C13
H_D#25 K4 B11 H_A#28
H_D#26 HD25# HA28# H_A#29
J5 HD26# HA29# D13

2
H_D#27 P7 A13 H_A#30
H_D#28 HD27# HA30# H_A#31 R246
L7 HD28# HA31# F13
H_D#29 J3
H_D#30 HD29# H_ADS# 100Ohm
P5 HD30# HADS# F8 H_ADS# 3
H_D#31 L3 B9 H_ADSTB#0
HD31# HADSTB0# H_ADSTB#0 3
H_D#32 H_ADSTB#1

1
U7 HD32# HADSTB1# E13 H_ADSTB#1 3
H_D#33 V6 J11 H_VREF 1 TP32
H_D#34 HD33# HVREF H_BNR#
R6 HD34# HBNR# A5 H_BNR# 3
H_D#35 R5 D5 H_BPRI#
HD35# HBPR# H_BPRI# 3

1
+VCCP H_D#36 P3 E7 H_BREQ#0 C179
HD36# HBREQ0# H_BREQ#0 3
H_D#37 T8 H10 H_CPURST# R249
HD37# HCPURST# H_CPURST# 3
H_D#38 0.1UF

HOST
R7 HD38#
2

H_D#39 200Ohm

2
R8 HD39#
R612 H_D#40 U8
H_D#41 HD40#

1
R4 HD41# HCLKINN AB1 CLK_MCH_BCLK# 6
221Ohm H_D#42 T4 AB2
HD42# HCLKINP CLK_MCH_BCLK 6
H_D#43 T5
H_D#44 HD43#
1

R1 HD44# HDBSY# C6 H_DBSY# 3

H_XSWING H_D#45 T3 E6
HD45# HDEFER# H_DINV#0 H_DEFER# 3
H_D#46 V8 H8
HD46# HDINV0# H_DINV#0 3
2

H_D#47 U6 K3 H_DINV#1
HD47# HDINV1# H_DINV#1 3
1

R613 C624 H_D#48 W6 T7 H_DINV#2

HD48# HDINV2# H_DINV#3 H_DINV#2 3
H_D#49 U3 U5
HD49# HDINV3# H_DINV#3 3
100Ohm 0.1UF H_D#50 V5 G6
HD50# HDPWR# H_DPWR# 3
H_D#51
2

W8 HD51# HDRDY# F7 H_DRDY# 3

H_D#52 H_DSTBN#0
1

W7 HD52# HDSTBN0# G4 H_DSTBN#0 3

H_D#53 U2 K1 H_DSTBN#1
HD53# HDSTBN1# H_DSTBN#2 H_DSTBN#1 3
H_D#54 U1 R3
HD54# HDSTBN2# H_DSTBN#3 H_DSTBN#2 3
H_D#55 Y5 V3
B HD55# HDSTBN3# H_DSTBP#0 H_DSTBN#3 3 B
H_D#56 Y2 G5
HD56# HDSTBP0# H_DSTBP#1 H_DSTBP#0 3
H_D#57 V4 K2
HD57# HDSTBP1# H_DSTBP#2 H_DSTBP#1 3
H_D#58 Y7 R2
HD58# HDSTBP2# H_DSTBP#3 H_DSTBP#2 3
H_D#59 W1 W4
HD59# HDSTBP3# TP_H_EDRDY# H_DSTBP#3 3
H_D#60 W3 F6 1 TP28
H_D#61 HD60# HEDRDY#
Y3 HD61# HHIT# D4 H_HIT# 3
H_D#62 Y6 D6
HD62# HHITM# H_HITM# 3
H_D#63 W2 B3
HD63# HLOCK# TP_H_PCREQ# H_LOCK# 3
A11 1 TP26
H_XRCOMP HPCREQ# H_REQ#0
C1 HXRCOMP HREQ0# A7 H_REQ#0 3
+VCCP H_XSCOMP C2 D7 H_REQ#1
H_XSWING HXSCOMP HREQ1# H_REQ#2 H_REQ#1 3
D1 HXSWING HREQ2# B8 H_REQ#2 3
H_YRCOMP T1 C7 H_REQ#3
HYRCOMP HREQ3# H_REQ#3 3
2

H_YSCOMP L1 A8 H_REQ#4
H_YSWING HYSCOMP HREQ4# H_RS#0 H_REQ#4 3
R619 P1 A4
HYSWING HRS0# H_RS#1 H_RS#0 3
HRS1# C5 H_RS#1 3
221Ohm B4 H_RS#2
HRS2# H_RS#2 3
HCPUSLP# G8 1 2 H_CPUSLP# 3,26
R614 0Ohm
1

HTRDY# B5 H_TRDY# 3
H_YSWING
ALVISO_BGA1257
2

R622 C641

100Ohm 0.1UF
2
1

915 PM P/N is 02-010000791HQ

A A
915 GM P/N is 02-010002640

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan Alviso GM(PM)CH - HOST (1) LIBRARY DATE :
2.0 SHEET 8 OF 61

WWW.AliSaler.Com
5 4 3 2 1
5 4 3 2 1

+1.5VS

CFG0 CFG1 CFG2 FSB

2
1 0 0 533MT/S(533MHz) R227

24.9Ohm
+VCCP 1 0 1 400MT/S(400MHz)
U48F

1
MISC
TP33 1 H24 D36
TP31 SDVOCTRL_DATA EXP_COMPI
1 H25 SDVOCTRL_CLK EXP_ICOMPO D34 EXP_RXN[0:15] 14
27 DMI_TXN[0:3] 6 CLK_MCH_3GPLL# AB29 GCLKN
U48A R244 10KOhm AC29 E30 EXP_RXN0
D DMI_TXN0 6 CLK_MCH_3GPLL GCLKP EXP_RXN0 EXP_RXN1 D
AA31 DMIRXN0 CFG0 G16 1 2 EXP_RXN1 F34
DMI_TXN1 AB35 H13 SR 1.0 -> ER 1.1 G30 EXP_RXN2
DMI_TXN2 DMIRXN1 CFG1 MCH_SEL1 6 EXP_RXN2 EXP_RXN3
AC31 G14 R896 1 2 0Ohm @ A15 H34
DMI_TXN3 DMIRXN2 CFG2 MCH_SEL0 6 14,24 TV_DACA_OUT TVDAC_A EXP_RXN3 EXP_RXN4
AD35 F16 R897 1 2 0Ohm @ C16 J30
27 DMI_TXP[0:3] DMIRXN3 CFG3 14,24 TV_DACB_OUT TVDAC_B EXP_RXN4 EXP_RXN5
F15 R898 1 2 0Ohm @ A17 K34
CFG4 14,24 TV_DACC_OUT TVDAC_C EXP_RXN5

TV
DMI_TXP0 Y31 G15 TVREF J18 L30 EXP_RXN6
DMI_TXP1 DMIRXP0 CFG5 CFG5 13 TV_REFSET EXP_RXN6 EXP_RXN7
AA35 DMIRXP1 CFG6 E16 CFG6 13 1 2 B15 TV_IRTNA EXP_RXN7 M34

2
DMI_TXP2 AB31 D17 R231 150Ohm 1% @ B16 N30 EXP_RXN8
DMI_TXP3 DMIRXP2 CFG7 CFG7 13 TV_IRTNB EXP_RXN8 EXP_RXN9
AC35 J16 1 2 R254 B17 P34
27 DMI_RXN[3:0] DMIRXP3 CFG8 CFG8 13 TV_IRTNC EXP_RXN9 EXP_RXN10
D15 R221 150Ohm 1% @ R30
DMI_RXN0 CFG9 CFG9 13 EXP_RXN10 EXP_RXN11
AA33 E15 1 2 4.99KOhm T34
DMI_RXN1 DMITXN0 CFG10 R212 150Ohm 1% @ @ EXP_RXN11 EXP_RXN12

DMI
AB37 DMITXN1 CFG11 D14 EXP_RXN12 U30
DMI_RXN2 EXP_RXN13

1
AC33 DMITXN2 CFG12 E14 CFG12 13 EXP_RXN13 V34
DMI_RXN3 AD37 H12 W30 EXP_RXN14
27 DMI_RXP[0:3] DMITXN3 CFG13 CFG13 13 DDC2BC EXP_RXN14 EXP_RXN15
CFG14 C14 14,24 DDC2BC E24 DDCCLK EXP_RXN15 Y34 EXP_RXP[0:15] 14
DMI_RXP0 Y33 H15 DDC2BD E23
DMITXP0 CFG15 14,24 DDC2BD DDCDATA

VGA
DMI_RXP1 AA37 J15 B SR 1.0 -> ER 1.1 E21 D30 EXP_RXP0
DMI_RXP2 DMITXP1 CFG16 CFG16 13 14,24 B B# BLUE EXP_RXP0 EXP_RXP1
AB33 H14 R192 1 2 R903 1 2 0Ohm @ D21 E34
DMI_RXP3 DMITXP2 CFG17 150Ohm 1% @ G BLUE# EXP_RXP1 EXP_RXP2
AC37 DMITXP3 CFG18 G22 CFG18 13 14,24 G C20 GREEN EXP_RXP2 F30
G# EXP_RXP3

PCI-EXPRESS GRAPHICS
G23 R191 1 2 R904 1 2 0Ohm @ B20 G34
CLK_DCLK0 CFG19 CFG19 13 GREEN# EXP_RXP3
0Ohm 1 2 R276CK_R0AM33 D23 150Ohm 1% @ R A19 H30 EXP_RXP4
22 CLK_DCLK0 CLK_DCLK1 SM_CK0 CFG20 CFG20 13 14,24 R RED EXP_RXP4
0Ohm 1 2 R655CK_R1 AL1 G25 R193 1 2 R905 1 2 0Ohm @ R# B19 J34 EXP_RXP5
22 CLK_DCLK1 CLK_DCLK2 SM_CK1 RSVD21 RED# EXP_RXP5 EXP_RXP6
TP43 1 AE11 G24 150Ohm 1% @ R210 1 2 39Ohm@ H21 K30 PEG_RXN[0..15]
CLK_DCLK3 SM_CK2 RSVD22 14,24 VSYNC VSYNC EXP_RXP6 PEG_RXN[0..15] 14
0Ohm 1 2 R654CK_R3 AJ34 J17 R211 1 2 39Ohm@ G21 L34 EXP_RXP7
20,21 CLK_DCLK3 CLK_DCLK4 SM_CK3 RSVD23 14,24 HSYNC HSYNC EXP_RXP7
0Ohm 1 2 R658CK_R4 AF6 A31 R250 1 2 DAC_REFSET J20 M30 EXP_RXP8
20,21 CLK_DCLK4 CLK_DCLK5 SM_CK4 RSVD24 REFSET EXP_RXP8 EXP_RXP9 PEG_RXP[0..15]
TP39 1 AC10 A30 255Ohm 1% @ N34
SM_CK5 RSVD25 EXP_RXP9 EXP_RXP10 PEG_RXP[0..15] 14
RSVD26 D26 EXP_RXP10 P30
CLK_DCLK0# 0Ohm 1 2 R277CK_R0#AN33 D25 R34 EXP_RXP11
22 CLK_DCLK0# SM_CK0# RSVD27 EXP_RXP11
DDR MUXING
CLK_DCLK1# 0Ohm 1 2 R653CK_R1# AK1 T30 EXP_RXP12
22 CLK_DCLK1# CLK_DCLK2# SM_CK1# EXP_RXP12 EXP_RXP13
TP42 1 AE10 U34
CLK_DCLK3# 0Ohm SM_CK2# EXP_RXP13
20,21 CLK_DCLK3# 1 2 R652CK_R3#AJ33 SM_CK3# 25 LCD_BACK_ADJ
LCD_BACK_ADJ E25 LBKLT_CRTL EXP_RXP14 V30 EXP_RXP14
CLK_DCLK4# 0Ohm 1 2 R659CK_R4# AF5 LCD_ENBACK F25 W34 EXP_RXP15
C 20,21 CLK_DCLK4# CLK_DCLK5# SM_CK4# 14,25 LCD_ENBACK LBKLT_EN EXP_RXP15 C
TP40 1 AD10 C23
SM_CK5# LCTLA_CLK EXP_TXN0 PEG_RXN0
C22 LCTLB_DATA EXP_TXN0 E32 1 2
SM_CKE0 AP21 R892 1 2 0Ohm @ F23 F36 EXP_TXN1 C170 0.1UF 1 2 PEG_RXN1
22,23 SM_CKE0 SM_CKE1 SM_CKE0 14,25 LVDS_DDC2BC LDDC_CLK EXP_TXN1 EXP_TXN2 PEG_RXN2
AM21 R893 1 2 0Ohm @ F22 G32 1 2 C623 0.1UF
22,23 SM_CKE1 SM_CKE2 SM_CKE1 14,25 LVDS_DDC2BD LDDC_DATA EXP_TXN2 EXP_TXN3 C175 PEG_RXN3
AH21 J23 R890 1 2 0Ohm @ F26 H36 0.1UF 1 2
20,23 SM_CKE2 SM_CKE2 BM_BUSY# PM_BMBUSY# 26 14,25 LCD_ENVDD LVDD_EN EXP_TXN3
PM

SM_CKE3 AK21 J21 PM_EXTTS#0 1 LCD_LIBG C33 J32 EXP_TXN4 1 2 C626 0.1UF PEG_RXN4
21,23 SM_CKE3 SM_CKE3 EXT_TS0# LIBG EXP_TXN4

LVDS
H22 PM_EXTTS#1 TP24 1 LCD_LVBG C31 K36 EXP_TXN5 C177 0.1UF 1 2 PEG_RXN5
SM_CS0# EXT_TS1# TP34 LVREFH LVBG EXP_TXN5 EXP_TXN6 PEG_RXN6
22,23 SM_CS0# AN16 SM_CS0# THRMTRIP# F5 PM_THRMTRIP# 3,26 1 F28 LVREFH EXP_TXN6 L32 1 2 C629 0.1UF
SM_CS1# AM14 AD30 TP29 1 LVREFL F27 M36 EXP_TXN7 C180 0.1UF 1 2 PEG_RXN7
22,23 SM_CS1# SM_CS2# SM_CS1# PWROK VRM_PWRGD 6,26,29,48,55 LVREFL EXP_TXN7 EXP_TXN8 PEG_RXN8
AH15 AE29 2 1 TP30 N32 1 2 C631 0.1UF
20,23 SM_CS2# SM_CS3# SM_CS2# RSTIN# PLT_RST#_3 14,24,27,29,41,44,45 L1_TXC- EXP_TXN8 EXP_TXN9 C196 PEG_RXN9
AG16 R271 100Ohm B30 P36 0.1UF 1 2
21,23 SM_CS3# SM_CS3# 25 L1_TXC- LACLKN EXP_TXN9
CLK

A24 L1_TXC+ B29 R32 EXP_TXN10 1 2 C633 0.1UF PEG_RXN10

SM_OCDCOMP0 DREF_CLKN DREFCLK# 6 25 L1_TXC+ LACLKP EXP_TXN10 EXP_TXN11 C210 PEG_RXN11
AF22 A23 C25 T36 0.1UF 1 2
SM_OCDCOMP1 SM_OCDCOMP0 DREF_CLKP DREFCLK 6 LBCLKN EXP_TXN11 EXP_TXN12 1 PEG_RXN12
AF16 SM_OCDCOMP1 DREF_SSCLKN C37 C24 LBCLKP EXP_TXN12 U32 2 C642 0.1UF
D37 V36 EXP_TXN13 C219 0.1UF 1 2 PEG_RXN13
SM_ODT0 AP14 DREF_SSCLKP L1_TX0- EXP_TXN13 EXP_TXN14 1 PEG_RXN14
22,23 SM_ODT0 SM_ODT0 25 L1_TX0- B34 LADATAN0 EXP_TXN14 W32 2 C646 0.1UF
2

SM_ODT1 AL15 AP37 1 TP94 L1_TX1- B33 Y36 EXP_TXN15 C224 0.1UF 1 2 PEG_RXN15
22,23 SM_ODT1 SM_ODT2 AM11 SM_ODT1 NC1 25 L1_TX1- L1_TX2- LADATAN1 EXP_TXN15
R272 R270 AN37 1 TP93 B32 C656 0.1UF
20,23 SM_ODT2 SM_ODT3 AN10 SM_ODT2 NC2 25 L1_TX2- LADATAN2 EXP_TXP0 PEG_RXP0
AP36 1 TP95 D32 1 2
21,23 SM_ODT3 SM_ODT3 NC3 EXP_TXP0 EXP_TXP1 C168 PEG_RXP1
40.2KOhm 40.2KOhm AP2 1 TP45 E36 0.1UF 1 2
NC

M_RCOMPN NC4 TP46 L1_TX0+ EXP_TXP1 EXP_TXP2 PEG_RXP2

AK10 SMRCOMPN NC5 AP1 1 25 L1_TX0+ A34 LADATAP0 EXP_TXP2 F32 1 2 C622 0.1UF
M_RCOMPP TP44 L1_TX1+ EXP_TXP3 C172 0.1UF 1 PEG_RXP3
1

AK11 SMRCOMPP NC6 AN1 1 25 L1_TX1+ A33 LADATAP1 EXP_TXP3 G36 2

SM_VREF_MCH AF37 B1 1 TP27 L1_TX2+ B31 H32 EXP_TXP4 1 2 C625 0.1UF PEG_RXP4
SMVREF0 NC7 25 L1_TX2+ LADATAP2 EXP_TXP4 EXP_TXP5 C176 PEG_RXP5
Route as AD1 A2 1 TP25 J36 0.1UF 1 2
SMVREF1 NC8 EXP_TXP5
1

short as C671 SMXSLEW AE27 B37 1 TP86 K32 EXP_TXP6 1 2 C628 0.1UF PEG_RXP6
SMXSLEWIN NC9 TP87 EXP_TXP6 EXP_TXP7 C178 0.1UF 1 PEG_RXP7
possible AE28 SMXSLEWOUT NC10 A36 1 C29 LBDATAN0 EXP_TXP7 L36 2
0.1UF SMYSLEW AF9 A37 1 TP85 D28 M32 EXP_TXP8 1 2 C630 0.1UF PEG_RXP8
SMYSLEWIN NC11 LBDATAN1 EXP_TXP8 EXP_TXP9 C190 0.1UF 1 PEG_RXP9
2

AF10 SMYSLEWOUT C27 LBDATAN2 EXP_TXP9 N36 2

P32 EXP_TXP10 1 2 C632 0.1UF PEG_RXP10
ALVISO_BGA1257 EXP_TXP10 EXP_TXP11 C198 0.1UF 1 PEG_RXP11
EXP_TXP11 R36 2
C28 T32 EXP_TXP12 1 2 C634 0.1UF PEG_RXP12
LBDATAP0 EXP_TXP12 EXP_TXP13 C215 0.1UF 1 PEG_RXP13
D27 LBDATAP1 EXP_TXP13 U36 2
B +2.5VS C26 V32 EXP_TXP14 1 2 C645 0.1UF PEG_RXP14 B
LBDATAP2 EXP_TXP14 EXP_TXP15 C222 0.1UF 1 PEG_RXP15
EXP_TXP15 W36 2
C648 0.1UF
R241 1 2 10KOhm PM_EXTTS#0 ALVISO_BGA1257

1 2 PM_EXTTS#1
R242 10KOhm

+5V +5VS

2
R625 R626
0Ohm 1 0Ohm @

1
+1.8V +1.8V R228

1
R627 0Ohm C644 1 2 LCD_LIBG
20,21,22 SM_VREF_DDR 1 2
2

0.1UF 1.5KOhm
1

R275 R638

2
1
TP53 R639
U50
80.6Ohm 10KOhm
0Ohm SM_VREF_MCH 1 5
M_RCOMPN @
1

2
M_RCOMPP
2

3 4
2

TLV2471CDBV
R274 R642

80.6Ohm 10KOhm
A A
1

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan Alviso GM(PM)CH - PCI-E (2) LIBRARY DATE :
2.0 SHEET 9 OF 61
5 4 3 2 1
5 4 3 2 1

D D

22 SM_A_DQ[0:63]
U48B 20,21 SM_B_DQ[0:63]
U48C
SM_A_DQ0 AG35 AK15 SM_A_BS#0 SM_B_DQ0 AE31
SM_A_DQ1 SADQ0 SA_BS0# SM_A_BS#1 SM_A_BS#0 22,23 SM_B_DQ1 SBDQ0 SM_B_BS#0
AH35 SADQ1 SA_BS1# AK16 SM_A_BS#1 22,23 AE32 SBDQ1 SB_BS0# AJ15 SM_B_BS#0 20,21,23
SM_A_DQ2 AL35 AL21 SM_A_BS#2 SM_B_DQ2 AG32 AG17 SM_B_BS#1
SM_A_DQ3 SADQ2 SA_BS2# SM_A_BS#2 22,23 SM_B_DQ3 SBDQ2 SB_BS1# SM_B_BS#2 SM_B_BS#1 20,21,23
AL37 SADQ3 SM_A_DM[0:7] 22 AG36 SBDQ3 SB_BS2# AG21 SM_B_BS#2 20,21,23
SM_A_DQ4 AH36 AJ37 SM_A_DM0 SM_B_DQ4 AE34
SM_A_DQ5 SADQ4 SA_DM0 SM_A_DM1 SM_B_DQ5 SBDQ4 SM_B_DM0 SM_B_DM[0:7] 20,21
AJ35 SADQ5 SA_DM1 AP35 AE33 SBDQ5 SB_DM0 AF32
SM_A_DQ6 AK37 AL29 SM_A_DM2 SM_B_DQ6 AF31 AK34 SM_B_DM1
SM_A_DQ7 SADQ6 SA_DM2 SM_A_DM3 SM_B_DQ7 SBDQ6 SB_DM1 SM_B_DM2
AL34 SADQ7 SA_DM3 AP24 AF30 SBDQ7 SB_DM2 AK27
SM_A_DQ8 AM36 AP9 SM_A_DM4 SM_B_DQ8 AH33 AK24 SM_B_DM3
SM_A_DQ9 SADQ8 SA_DM4 SM_A_DM5 SM_B_DQ9 SBDQ8 SB_DM3 SM_B_DM4
AN35 SADQ9 SA_DM5 AP4 AH32 SBDQ9 SB_DM4 AJ10
SM_A_DQ10 AP32 AJ2 SM_A_DM6 SM_B_DQ10 AK31 AK5 SM_B_DM5
SM_A_DQ11 SADQ10 SA_DM6 SM_A_DM7 SM_B_DQ11 SBDQ10 SB_DM5 SM_B_DM6
AM31 SADQ11 SA_DM7 AD3 AG30 SBDQ11 SB_DM6 AE7
SM_A_DQ12 AM34 SM_B_DQ12 AG34 AB7 SM_B_DM7
SM_A_DQ13 SADQ12 SM_A_DQS0 SM_A_DQS[0:7] 22 SM_B_DQ13 SBDQ12 SB_DM7
AM35 SADQ13 SA_DQS0 AK36 AG33 SBDQ13 SM_B_DQS[0:7] 20,21
SM_A_DQ14 SM_A_DQS1 SM_B_DQ14 SM_B_DQS0

DDR SYSTEM MEMORY A

AL32 SADQ14 SA_DQS1 AP33 AH31 SBDQ14 SB_DQS0 AF34
SM_A_DQ15 AM32 AN29 SM_A_DQS2 SM_B_DQ15 AJ31 AK32 SM_B_DQS1
SM_A_DQ16 SADQ15 SA_DQS2 SM_A_DQS3 SM_B_DQ16 SBDQ15 SB_DQS1 SM_B_DQS2
AN31 SADQ16 SA_DQS3 AP23 AK30 SBDQ16 SB_DQS2 AJ28
SM_A_DQ17 AP31 AM8 SM_A_DQS4 SM_B_DQ17 AJ30 AK23 SM_B_DQS3
SM_A_DQ18 SADQ17 SA_DQS4 SM_A_DQS5 SM_B_DQ18 SBDQ17 SB_DQS3 SM_B_DQS4

DDR SYSTEM MEMORY B

AN28 SADQ18 SA_DQS5 AM4 AH29 SBDQ18 SB_DQS4 AM10
SM_A_DQ19 AP28 AJ1 SM_A_DQS6 SM_B_DQ19 AH28 AH6 SM_B_DQS5
SM_A_DQ20 SADQ19 SA_DQS6 SM_A_DQS7 SM_B_DQ20 SBDQ19 SB_DQS5 SM_B_DQS6
AL30 SADQ20 SA_DQS7 AE5 AK29 SBDQ20 SB_DQS6 AF8
SM_A_DQ21 AM30 SM_B_DQ21 AH30 AB4 SM_B_DQS7
SM_A_DQ22 SADQ21 SM_A_DQS#0 SM_A_DQS#[0:7] 22 SM_B_DQ22 SBDQ21 SB_DQS7
AM28 SADQ22 SA_DQS0# AK35 AH27 SBDQ22 SM_B_DQS#[0:7] 20,21
C SM_A_DQ23 AL28 AP34 SM_A_DQS#1 SM_B_DQ23 AG28 AF35 SM_B_DQS#0 C
SM_A_DQ24 SADQ23 SA_DQS1# SM_A_DQS#2 SM_B_DQ24 SBDQ23 SB_DQS0# SM_B_DQS#1
AP27 SADQ24 SA_DQS2# AN30 AF24 SBDQ24 SB_DQS1# AK33
SM_A_DQ25 AM27 AN23 SM_A_DQS#3 SM_B_DQ25 AG23 AK28 SM_B_DQS#2
SM_A_DQ26 SADQ25 SA_DQS3# SM_A_DQS#4 SM_B_DQ26 SBDQ25 SB_DQS2# SM_B_DQS#3
AM23 SADQ26 SA_DQS4# AN8 AJ22 SBDQ26 SB_DQS3# AJ23
SM_A_DQ27 AM22 AM5 SM_A_DQS#5 SM_B_DQ27 AK22 AL10 SM_B_DQS#4
SM_A_DQ28 SADQ27 SA_DQS5# SM_A_DQS#6 SM_B_DQ28 SBDQ27 SB_DQS4# SM_B_DQS#5
AL23 SADQ28 SA_DQS6# AH1 AH24 SBDQ28 SB_DQS5# AH7
SM_A_DQ29 AM24 AE4 SM_A_DQS#7 SM_B_DQ29 AH23 AF7 SM_B_DQS#6
SM_A_DQ30 SADQ29 SA_DQS7# SM_B_DQ30 SBDQ29 SB_DQS6# SM_B_DQS#7
AN22 SADQ30 SM_A_MA[0:13] 22,23 AG22 SBDQ30 SB_DQS7# AB5
SM_A_DQ31 AP22 AL17 SM_A_MA0 SM_B_DQ31 AJ21
SM_A_DQ32 SADQ31 SA_MA0 SM_A_MA1 SM_B_DQ32 SBDQ31 SM_B_MA0 SM_B_MA[0:13] 20,21,23
AM9 SADQ32 SA_MA1 AP17 AG10 SBDQ32 SB_MA0 AH17
SM_A_DQ33 AL9 AP18 SM_A_MA2 SM_B_DQ33 AG9 AK17 SM_B_MA1
SM_A_DQ34 SADQ33 SA_MA2 SM_A_MA3 SM_B_DQ34 SBDQ33 SB_MA1 SM_B_MA2
AL6 SADQ34 SA_MA3 AM17 AG8 SBDQ34 SB_MA2 AH18
SM_A_DQ35 AP7 AN18 SM_A_MA4 SM_B_DQ35 AH8 AJ18 SM_B_MA3
SM_A_DQ36 SADQ35 SA_MA4 SM_A_MA5 SM_B_DQ36 SBDQ35 SB_MA3 SM_B_MA4
AP11 SADQ36 SA_MA5 AM18 AH11 SBDQ36 SB_MA4 AK18
SM_A_DQ37 AP10 AL19 SM_A_MA6 SM_B_DQ37 AH10 AJ19 SM_B_MA5
SM_A_DQ38 SADQ37 SA_MA6 SM_A_MA7 SM_B_DQ38 SBDQ37 SB_MA5 SM_B_MA6
AL7 SADQ38 SA_MA7 AP20 AJ9 SBDQ38 SB_MA6 AK19
SM_A_DQ39 AM7 AM19 SM_A_MA8 SM_B_DQ39 AK9 AH19 SM_B_MA7
SM_A_DQ40 SADQ39 SA_MA8 SM_A_MA9 SM_B_DQ40 SBDQ39 SB_MA7 SM_B_MA8
AN5 SADQ40 SA_MA9 AL20 AJ7 SBDQ40 SB_MA8 AJ20
SM_A_DQ41 AN6 AM16 SM_A_MA10 SM_B_DQ41 AK6 AH20 SM_B_MA9
SM_A_DQ42 SADQ41 SA_MA10 SM_A_MA11 SM_B_DQ42 SBDQ41 SB_MA9 SM_B_MA10
AN3 SADQ42 SA_MA11 AN20 AJ4 SBDQ42 SB_MA10 AJ16
SM_A_DQ43 AP3 AM20 SM_A_MA12 SM_B_DQ43 AH5 AG18 SM_B_MA11
SM_A_DQ44 SADQ43 SA_MA12 SM_A_MA13 SM_B_DQ44 SBDQ43 SB_MA11 SM_B_MA12
AP6 SADQ44 SA_MA13 AM15 AK8 SBDQ44 SB_MA12 AG20
SM_A_DQ45 AM6 SM_B_DQ45 AJ8 AG15 SM_B_MA13
SM_A_DQ46 SADQ45 SM_CAS# SM_B_DQ46 SBDQ45 SB_MA13
AL4 SADQ46 SA_CAS# AN15 SM_A_CAS# 22,23 AJ5 SBDQ46
SM_A_DQ47 AM3 AP16 SM_RAS# SM_B_DQ47 AK4 AH14 SM_B_CAS#
SM_A_DQ48 SADQ47 SA_RAS# SM_A_RAS# 22,23 SM_B_DQ48 SBDQ47 SB_CAS# SM_B_RAS# SM_B_CAS# 20,21,23
AK2 SADQ48 SA_RCVENIN# AF29 AG5 SBDQ48 SB_RAS# AK14 SM_B_RAS# 20,21,23
SM_A_DQ49 AK3 AF28 SM_B_DQ49 AG4 AF15
SM_A_DQ50 SADQ49 SA_RCVENOUT# SM_WE# SM_B_DQ50 SBDQ49 SB_RCVENIN#
AG2 SADQ50 SA_WE# AP15 SM_A_WE# 22,23 AD8 SBDQ50 SB_RCVENOUT# AF14
SM_A_DQ51 AG1 SM_B_DQ51 AD9 AH16 SM_B_WE#
SM_A_DQ52 SADQ51 SM_B_DQ52 SBDQ51 SB_WE# SM_B_WE# 20,21,23
AL3 SADQ52 AH4 SBDQ52
SM_A_DQ53 AM2 SM_B_DQ53 AG6
SM_A_DQ54 SADQ53 SM_B_DQ54 SBDQ53
AH3 SADQ54 AE8 SBDQ54
B SM_A_DQ55 AG3 SM_B_DQ55 AD7 B
SM_A_DQ56 SADQ55 SM_B_DQ56 SBDQ55
AF3 SADQ56 AC5 SBDQ56
SM_A_DQ57 AE3 SM_B_DQ57 AB8
SM_A_DQ58 SADQ57 SM_B_DQ58 SBDQ57
AD6 SADQ58 AB6 SBDQ58
SM_A_DQ59 AC4 SM_B_DQ59 AA8
SM_A_DQ60 SADQ59 SM_B_DQ60 SBDQ59
AF2 SADQ60 AC8 SBDQ60
SM_A_DQ61 AF1 SM_B_DQ61 AC7
SM_A_DQ62 SADQ61 SM_B_DQ62 SBDQ61
AD4 SADQ62 AA4 SBDQ62
SM_A_DQ63 AD5 SM_B_DQ63 AA5
SADQ63 SBDQ63

ALVISO_BGA1257 ALVISO_BGA1257

A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan Alviso GM(PM)CH - DDR (3) LIBRARY DATE :
2.0 SHEET 10 OF 61

WWW.AliSaler.Com 5 4 3 2 1
A
B
C
D

+1.5VS
+VCCP
2 1 2 1

5
5

+2.5VS_SYNC

C614
C166

0.1UF
0.1UF
+2.5VS

+2.5VS_3GBG
2 1

+1.5VS_R72

1
1

+1.5VS_L
2 1 2 1
C159

0.1UF

L30
L20

+1.5VS

+1.5VS
2
2

C647
C627

0.1UF
0.1UF

120Ohm/100Mhz
120Ohm/100Mhz

+2.5VS
2 1

+
1 2 G1
VTT51

VCCP_GMCH_CAP4
2 1 M1 2 1
VTT50

VCCP_GMCH_CAP3
VCCP_GMCH_CAP2
VCCP_GMCH_CAP1

N1
VTT49

CE14
C156
G37 V1

R208

0Ohm
0.1UF
VSSA_3GBG VTT48

100UF/4V
1 2 F37 B2

C223
C165

1
0.01U

0.1UF
VCCA_3GBG VTT47
2 1 M2

+1.5VS_3GPLL
VTT46
2 1 Y27 N2
+VCCP_GMCH

VCCA_3GPLL2 VTT45

L33
Y28 M3 2 1 2 1
VCCA_3GPLL1 VTT44
Y29 N3

C218

2
VCCA_3GPLL0 VTT43
M4

C669

0.1UF
VTT42

10uF/10V

120Ohm/100Mhz
2 1 J37 N4
C193
C163
+2.5VS_CRTDAC

0.1UF
0.1UF

VCC3G6 VTT41
L37 M5
VCC3G5 VTT40
N37 N5
VCC3G4 VTT39
R37 A6 2 1

C661
VCC3G3 VTT38
2 1 U37 M6
VCC3G2 VTT37

10uF/10V
W37 N6
VCC3G1 VTT36
AE37 M7

+1.5VS_DDRDLL
C201

VCC3G0 VTT35
N7

C239

0.1UF
VTT34
10uF/10V

2 1 AF18 M8
VCCA_SM3 VTT33
AF19 N8
VCCA_SM2 VTT32
Alviso.

AP19 J9
VCCA_SM1 VTT31
AF20 L9

C240
VCCA_SM0 VTT30
M9
VTT29

10uF/10V
+2.5VS
N9
VTT28

4
4

+1.5VS
A27 P9

PROJECT: Obi-Wan
VCCTX_LVDS2 VTT27
A28 R9
VCCTX_LVDS1 VTT26
B28 U9
VCCTX_LVDS0 VTT25
W9

0Ohm
VTT24
AE1 Y9

R209
VCCSM64 VTT23
AM1 J10

2
VCCSM63 VTT22
2 1 AP8 K10
VCCSM62 VTT21
2 1 AB9 M10
VCCSM61 VTT20

2.0
Route caps within 250mil of

AB10 N10
Alviso. Route FB within 3" of

VCCSM60 VTT19
AB11 P10

C155
Layout Note: VssA_CRTDAC

0.1UF
VCCSM59 VTT18

REVISION
AC11 R10 2 1

C217

0.1UF
VCCSM58 VTT17
+

AD11 T10
VCCSM57 VTT16
2 1 2 1 AE12 U10
VCCSM56 VTT15
2 1 AF12 V10
1.8V_DDR_CAP3
1.8V_DDR_CAP4
1.8V_DDR_CAP6
VCCSM55 VTT14
CE13

AG12 W10
VCCSM54 VTT13
100UF/4V

AH12 K11

C154
C673

0.1UF
VCCSM53 VTT12

+2.5VS_TXLVDS
AJ12 L11

C234
VCCSM52 VTT11

10uF/10V
2 1 AK12 M11

DATE:
SHEET
VCCSM51 VTT10

10uF/10V
AL12 N11
shorted internally.

+1.5VS_DLVDS
VCCSM50 VTT9
AM12 P11 2 1
VCCSM49 VTT8
AN12 R11
C677

+1.8V
0.1UF
VCCSM48 VTT7
+1.5VS_MPLL

Note: All VCCSM pins

AP12 T11
VCCSM47 VTT6
2 1 AE13 U11
C655

0.1UF

VCCSM46 VTT5
AF13 VCCSM45 V11
VTT4

+2.5VS
AG13VCCSM44 W11
VTT3

11
K12
C679
1

0.1UF

AH13VCCSM43
VTT2
AJ13 VCCSM42 J13
VTT1
AK13VCCSM41 K13
VTT0
connect to the gnd plane
cap ground lead and than

AL13 VCCSM40
from GMCH to decoupling

10uF/10V
H20
C681
2

AM13VCCSM39
VCC_SYNC
2 1
Route VssA_CRTDAC GND

AN13VCCSM38
2 1 AP13VCCSM37
2 1 G19

OF
AE14VCCSM36
VSSA_CRTDAC
E19
C662

0.1UF
AE15VCCSM35
VCCA_CRTDAC1
L84 120Ohm/100Mhz

2 1 F19

C158

0.1UF
AE16VCCSM34
VCCA_CRTDAC0
C256

3
3

0.1UF

AE17VCCSM33
AE18VCCSM32 AA2
VCCA_MPLL
2 1 2 1 AA1

Thursday, August 04, 2005

AE19VCCSM31
VCCA_HPLL
2 1 AE20VCCSM30 C35
VCCA_DPLLB

61
+

AE21VCCSM29 B23
VCCA_DPLLA
AC1

C152
C675

0.01U
0.1UF

AE22VCCSM28 VCCH_MPLL0
AC2 2 1 2 1
CE18

AE23VCCSM27 VCCH_MPLL1
+
+

+2.5VS_ALVDS 2 1 AE24VCCSM26
K17
150U/4.0V
shorted internally.

AE25VCCSM25 VCC48
K18
CE1

AF25 VCCSM24 VCC47

CE15

T18
C676

0.1UF

AG25VCCSM23 VCC46
Note: All VCCSM pins
100UF/4V
100UF/4V

AH25VCCSM22 VCC45 V18

AJ25 VCCSM21 VCC44 W18
AK25VCCSM20 VCC43 K19 2 1 2 1
+1.5VS_HPLL

U19
+1.5VS_DPLLB

AL25 VCCSM19 VCC42

AM25VCCSM18 VCC41 V19
K20
C169
C659

1
1

0.1UF
0.1UF

AN25VCCSM17 VCC40
T20
POWER

AP25VCCSM16 VCC39
AE26VCCSM15 VCC38 U20
+2.5VS

AF26 VCCSM14 VCC37 W20

2 1 K21
2
2

AG26VCCSM13 VCC36
K22

DESCRIPTION:
AH26VCCSM12 VCC35
AJ26 VCCSM11 VCC34 K23
2 1 K24
C195

0.01U
AK26VCCSM10 VCC33
10uF/10V

J25
C153
1.8V_DDR_CAP1
1.8V_DDR_CAP2
1.8V_DDR_CAP5

AL26 VCCSM9 VCC32

L18 120Ohm/100Mhz
L85 120Ohm/100Mhz

2 1 2 1 AM26VCCSM8 VCC31 K25

H26
C221

0.01U

AN26VCCSM7 VCC30
AP26VCCSM6 VCC29 K26
2 1 H27
C157

0.1UF
0.1UF

AC27VCCSM5 VCC28
+2.5VS_HV

2 1 J27
1

AD27VCCSM4 VCC27
AD28VCCSM3 VCC26 K27
L27 2 1
C212

+1.5VS_QTVDAC
0.1UF

L22

AP29VCCSM2 VCC25
+

AH37VCCSM1 VCC24 M27

N27
2

AM37VCCSM0 VCC23
+1.5VS_TVDAC

P27
CE2

VCC22
R27
+1.5VS_DLVDS

A21 VCCHV2 VCC21

2
2

C182 120Ohm/100Mhz
100UF/4V

B21 VCCHV1 VCC20 T27

B22 VCCHV0 VCC19 U27 2 1
V27 2 1
Alviso GM(PM)CH - POWER (4)
+2.5VS_ALVDS

VCC18
G28
+1.5VS_DPLLA

A35 VCCA_LVDS VCC17

H28
C191

VCC16
J28
C160

0.1UF

A25 VCCD_LVDS2 VCC15

10uF/10V

B25 VCCD_LVDS1 VCC14 K28

B26 VCCD_LVDS0 VCC13 L28
M28 2 1
1

VCC12
H17 VCC11 N28
VCCDQ_TVDAC
D19 VCC10 P28
VCCD_TVDAC
R28
C220

VCC9
+1.5VS

G18 T28
2

VSSA_TVBG VCC8
10uF/10V

2 1 H18 VCC7 U28

VCCA_TVBG
VCC6 V28
2 1 E18 VCC5 J29 2 1
VCCA_TVDACC1
F18 K29
C192

0.01U

VCCA_TVDACC0 VCC4
L17 120Ohm/100Mhz

2 1 C18 VCC3 M29

VCCA_TVDACB1
LIBRARY DATE :

2 1 D18 N29
C216
C202

0.01U

VCCA_TVDACB0 VCC2
2 1 E17 VCC1 R29
VCCA_TVDACA1
10uF/10V

2 1 F17 T29
C211

0.01U

VCCA_TVDACA0 VCC0
1

0.1UF

2 1 2 1
C200

1
0.01U
+1.5VS_HMPLL

+3VS_TVBG
0.1UF

2 1
1
U48G
0Ohm

L23

SCHEMATIC FILE NAME :

C183
R229

0.1UF
0.1UF

+3VS_TVDACC

2
2

L29

2 1
+3VS_TVDACB
0.1UF

2
1

L25

C181 120Ohm/100Mhz
+3VS_TVDACA
ALVISO_BGA1257
+VCC_GMCH_CORE
+1.5VS

C233

2
0.1UF

L24

<Doc>
C213 120Ohm/100Mhz

2 1
2

C199 120Ohm/100Mhz

Route VssATVGB GND

connect to the gnd plane

cap ground lead and than
from GMCH to decoupling
C194 120Ohm/100Mhz
C232

+3VS
0.1UF

1
1

2
1

+VCC_GMCH
D38

BAT54C

+2.5VS
3

2
2 1 3 2 1
+3VS

1
R235
R651

1KOhm
D12

BAT54C
1KOhm

DESIGN ENGINEER :
A
B
C
D
A
B
C
D

5
5

VSSALVDS B36
AL24 VSS267
AN24VSS266
A26 VSS265 VSS271 Y1
D2

+1.8V
E26 VSS264 VSS270
G26 VSS263 VSS269 G2
J26 VSS262 VSS268 J2
B27 VSS261 VSS260 L2
E27 VSS129 VSS259 P2
AB12VCCSM_NCTF31 G27 VSS128 VSS258 T2
AC12VCCSM_NCTF30 W27 VSS127 VSS257 V2
AD12VCCSM_NCTF29 AA27VSS126 VSS256 AD2
AB13VCCSM_NCTF28 AB27VSS125 VSS255 AE2
AC13VCCSM_NCTF27 AF27 VSS124 VSS254 AH2
AD13VCCSM_NCTF26 AG27VSS123 VSS253 AL2
AC14VCCSM_NCTF25 AJ27 VSS122 VSS252 AN2
AD14VCCSM_NCTF24 AL27 VSS121 VSS251 A3
AC15VCCSM_NCTF23 AN27VSS120 VSS250 C3
AD15VCCSM_NCTF22 E28 VSS119 VSS249 AA3
AC16VCCSM_NCTF21 W28 VSS118 VSS248 AB3
AD16VCCSM_NCTF20 AA28VSS117 VSS247 AC3
AC17VCCSM_NCTF19 AB28VSS116 VSS246 AJ3
AD17VCCSM_NCTF18 AC28VSS115 VSS245 C4
AC18VCCSM_NCTF17 A29 VSS114 VSS244 H4
AD18VCCSM_NCTF16 D29 VSS113 VSS243 L4
AC19VCCSM_NCTF15 E29 VSS112 VSS242 P4
U4

+VCCP
AD19VCCSM_NCTF14 F29 VSS111 VSS241
AC20VCCSM_NCTF13 G29 VSS110 VSS240 Y4
AD20VCCSM_NCTF12 H29 VSS109 VSS239 AF4
AC21VCCSM_NCTF11 VTT_NCTF17 L12 L29 VSS108 VSS238 AN4
AD21VCCSM_NCTF10 VTT_NCTF16 M12 P29 VSS107 VSS237 E5

WWW.AliSaler.Com
AC22VCCSM_NCTF9 VTT_NCTF15 N12 U29 VSS106 VSS236 W5
AD22VCCSM_NCTF8 VTT_NCTF14 P12 V29 VSS105 VSS235 AL5
AC23VCCSM_NCTF7 VTT_NCTF13 R12 W29 VSS104 VSS234 AP5

4
4

T12 B6

PROJECT: Obi-Wan
AD23VCCSM_NCTF6 VTT_NCTF12 AA29VSS103 VSS233
AC24VCCSM_NCTF5 VTT_NCTF11 U12 AD29VSS102 VSS232 J6
AD24VCCSM_NCTF4 VTT_NCTF10 V12 AG29VSS101 VSS231 L6
AC25VCCSM_NCTF3 VTT_NCTF9 W12 AJ29 VSS100 VSS230 P6
AD25VCCSM_NCTF2 VTT_NCTF8 L13 AM29VSS99 VSS229 T6
AC26VCCSM_NCTF1 VTT_NCTF7 M13 C30 VSS98 VSS228 AA6
AD26VCCSM_NCTF0 VTT_NCTF6 N13 Y30 VSS97 VSS227 AC6
VTT_NCTF5 P13 AA30VSS96 VSS226 AE6

2.0
L17 VCC_NCTF78 VTT_NCTF4 R13 AB30VSS95 VSS225 AJ6
M17 VCC_NCTF77 VTT_NCTF3 T13 AC30VSS94 VSS224 G7

REVISION
N17 VCC_NCTF76 VTT_NCTF2 U13 AE30VSS93 VSS223 V7
P17 VCC_NCTF75 VTT_NCTF1 V13 AP30VSS92 VSS222 AA7
T17 VCC_NCTF74 VTT_NCTF0 W13 D31 VSS91 VSS221 AG7
U17 VCC_NCTF73 E31 VSS90 VSS220 AK7
V17 VCC_NCTF72 F31 VSS89 VSS219 AN7
W17 VCC_NCTF71 G31 VSS88 VSS218 C8
L18 VCC_NCTF70 H31 VSS87 VSS217 E8
M18 L8

DATE:
VCC_NCTF69 J31 VSS86 VSS216

SHEET
N18 VCC_NCTF68 VSS_NCTF68 Y12 K31 VSS85 VSS215 P8
P18 VCC_NCTF67 VSS_NCTF67 AA12 L31 VSS84 VSS214 Y8
R18 VCC_NCTF66 VSS_NCTF66 Y13 M31 VSS83 VSS213 AL8
Y18 VCC_NCTF65 VSS_NCTF65 AA13 N31 VSS82 VSS212 A9
L19 VCC_NCTF64 VSS_NCTF64 L14 P31 VSS81 VSS211 H9
M19 VCC_NCTF63 VSS_NCTF63 M14 R31 VSS80 VSS210 K9
N19 VCC_NCTF62 VSS_NCTF62 N14 T31 VSS79 VSS209 T9

12
P19 VCC_NCTF61 VSS_NCTF61 P14 U31 VSS78 VSS208 V9
R19 VCC_NCTF60 VSS_NCTF60 R14 V31 VSS77 VSS207 AA9
Y19 VCC_NCTF59 VSS_NCTF59 T14 W31 VSS76 VSS206 AC9
L20 VCC_NCTF58 VSS_NCTF58 U14 AD31VSS75 VSS205 AE9
M20 VCC_NCTF57 VSS_NCTF57 V14 AG31VSS74 VSS204 AH9
N20 VCC_NCTF56 VSS_NCTF56 W14 AL31 VSS73 VSS203 AN9
NCTF

P20 VCC_NCTF55 VSS_NCTF55 Y14 A32 VSS72 VSS202 D10

R20 AA14 L10

OF
VCC_NCTF54 VSS_NCTF54 C32 VSS71 VSS201
Y20 VCC_NCTF53 VSS_NCTF53 AB14 Y32 VSS70 VSS200 Y10
L21 VCC_NCTF52 VSS_NCTF52 L15 AA32VSS69 VSS199 AA10
VSS

M21 M15 F11

3
3

VCC_NCTF51 VSS_NCTF51 AB32VSS68 VSS198

N21 VCC_NCTF50 VSS_NCTF50 N15 AC32VSS67 VSS197 H11
P21 P15 Y11

Thursday, August 04, 2005

VCC_NCTF49 VSS_NCTF49 AD32VSS66 VSS196
T21 VCC_NCTF48 VSS_NCTF48 R15 AJ32 VSS65 VSS195 AA11

61
U21 VCC_NCTF47 VSS_NCTF47 T15 AN32VSS64 VSS194 AF11
V21 VCC_NCTF46 VSS_NCTF46 U15 D33 VSS63 VSS193 AG11
W21 VCC_NCTF45 VSS_NCTF45 V15 E33 VSS62 VSS192 AJ11
L22 VCC_NCTF44 VSS_NCTF44 W15 F33 VSS61 VSS191 AL11
M22 VCC_NCTF43 VSS_NCTF43 Y15 G33 VSS60 VSS190 AN11
N22 VCC_NCTF42 VSS_NCTF42 AA15 H33 VSS59 VSS189 B12
P22 VCC_NCTF41 VSS_NCTF41 AB15 J33 VSS58 VSS188 D12
R22 VCC_NCTF40 VSS_NCTF40 L16 K33 VSS57 VSS187 J12
T22 VCC_NCTF39 VSS_NCTF39 M16 L33 VSS56 VSS186 A14
U22 VCC_NCTF38 VSS_NCTF38 N16 M33 VSS55 VSS185 B14
V22 VCC_NCTF37 VSS_NCTF37 P16 N33 VSS54 VSS184 F14
W22 VCC_NCTF36 VSS_NCTF36 R16 P33 VSS53 VSS183 J14
L23 VCC_NCTF35 VSS_NCTF35 T16 R33 VSS52 VSS182 K14
M23 VCC_NCTF34 VSS_NCTF34 U16 T33 VSS51 VSS181 AG14
N23 VCC_NCTF33 VSS_NCTF33 V16 U33 VSS50 VSS180 AJ14
P23 VCC_NCTF32 VSS_NCTF32 W16 V33 VSS49 VSS179 AL14
R23 VCC_NCTF31 VSS_NCTF31 Y16 W33 VSS48 VSS178 AN14
T23 AA16 C15

DESCRIPTION:
VCC_NCTF30 VSS_NCTF30 AD33VSS47 VSS177
U23 VCC_NCTF29 VSS_NCTF29 AB16 AF33 VSS46 VSS176 K15
V23 VCC_NCTF28 VSS_NCTF28 R17 AL33 VSS45 VSS175 A16
W23 VCC_NCTF27 VSS_NCTF27 Y17 C34 VSS44 VSS174 D16
L24 VCC_NCTF26 VSS_NCTF26 AA17 AA34VSS43 VSS173 H16
M24 VCC_NCTF25 VSS_NCTF25 AB17 AB34VSS42 VSS172 K16
N24 VCC_NCTF24 VSS_NCTF24 AA18 AC34VSS41 VSS171 AL16
P24 VCC_NCTF23 VSS_NCTF23 AB18 AD34VSS40 VSS170 C17
R24 VCC_NCTF22 VSS_NCTF22 AA19 AH34VSS39 VSS169 G17
T24 VCC_NCTF21 VSS_NCTF21 AB19 AN34VSS38 VSS168 AF17
U24 VCC_NCTF20 VSS_NCTF20 AA20 B35 VSS37 VSS167 AJ17
V24 VCC_NCTF19 VSS_NCTF19 AB20 D35 VSS36 VSS166 AN17
W24 VCC_NCTF18 VSS_NCTF18 R21 E35 VSS35 VSS165 A18
L25 VCC_NCTF17 VSS_NCTF17 Y21 F35 VSS34 VSS164 B18
M25 VCC_NCTF16 VSS_NCTF16 AA21 G35 VSS33 VSS163 U18

2
2

N25 VCC_NCTF15 VSS_NCTF15 AB21 H35 VSS32 VSS162 AL18

P25 VCC_NCTF14 VSS_NCTF14 Y22 J35 VSS31 VSS161 C19
R25 VCC_NCTF13 VSS_NCTF13 AA22 K35 VSS30 VSS160 H19
Alviso GM(PM)CH - GND (5)
T25 VCC_NCTF12 VSS_NCTF12 AB22 L35 VSS29 VSS159 J19
U25 VCC_NCTF11 VSS_NCTF11 Y23 M35 VSS28 VSS158 T19
V25 VCC_NCTF10 VSS_NCTF10 AA23 N35 VSS27 VSS157 W19
W25 VCC_NCTF9 VSS_NCTF9 AB23 P35 VSS26 VSS156 AG19
L26 VCC_NCTF8 VSS_NCTF8 Y24 R35 VSS25 VSS155 AN19
M26 VCC_NCTF7 VSS_NCTF7 AA24 T35 VSS24 VSS154 A20
N26 VCC_NCTF6 VSS_NCTF6 AB24 U35 VSS23 VSS153 D20
P26 VCC_NCTF5 VSS_NCTF5 Y25 V35 VSS22 VSS152 E20
R26 VCC_NCTF4 VSS_NCTF4 AA25 W35 VSS21 VSS151 F20
T26 VCC_NCTF3 VSS_NCTF3 AB25 Y35 VSS20 VSS150 G20
U26 VCC_NCTF2 VSS_NCTF2 Y26 AE35VSS19 VSS149 V20
V26 VCC_NCTF1 VSS_NCTF1 AA26 C36 VSS18 VSS148 AK20
W26 VCC_NCTF0 VSS_NCTF0 AB26 AA36VSS17 VSS147 C21
AB36VSS16 VSS146 F21
AC36VSS15 VSS145 AF21
LIBRARY DATE :

AD36VSS14 VSS144 AN21

U48E

AE36VSS13 VSS143 A22

AF36 VSS12 VSS142 D22
AJ36 VSS11 VSS141 E22
AL36 VSS10 VSS140 J22
AN36VSS9 VSS139 AH22
AL22
SCHEMATIC FILE NAME :

E37 VSS8 VSS138

ALVISO_BGA1257

H37 VSS7 VSS137 H23

K37 VSS6 VSS136 AF23
M37 VSS5 VSS135 B24
P37 VSS4 VSS134 D24
T37 VSS3 VSS133 F24
V37 VSS2 VSS132 J24
<Doc>

AG24
+VCC_GMCH_CORE

Y37 VSS1 VSS131

AG37VSS0 VSS130 AJ24
1
1

U48H
ALVISO_BGA1257

DESIGN ENGINEER :
A
B
C
D
5 4 3 2 1

D D

CFG5 : DMI x2 Select CFG8 : PCI-X POWER SAVING CFG18 : GMCH core VCC SELECT CFG12 : XOR/ALL Z test straps
LOW = DMI X 2 LOW = PCI-X Power Saving LOW = 1.05V (Default) CFG13 : XOR/ALL Z test straps
HIGH = DMI X 4 (Default) HIGH = (Default) HIGH = 1.5V LOW LOW = Reserved
+2.5VS LOW HIGH = XOR Mode Enabled
9 CFG5 9 CFG8
HIGH LOW = All Z Mode Enabled
HIGH HIGH = Normal Operation (Default)
2

2
R240 R248
R236
2.2KOhm @ 2.2KOhm @
2.2KOhm @ R217 2.2KOhm @
NO_STUFF NO_STUFF
1

1
9 CFG12 1 2

1
NO_STUFF
R243 2.2KOhm @
9 CFG18
9 CFG13 1 2

CFG6 : DDR vs DDR2 select CFG9 : PCI Express Graphic Lane Reversal CFG19 : CPU VTT SELECT
LOW = DDR2 LOW = Reverse Lane LOW = 1.05V (Default)
C C
HIGH = DDR (Default) HIGH = Normal Operation (Default) HIGH = 1.2V
+2.5VS
9 CFG6 9 CFG9
2

2
R232 R237
R239
2.2KOhm 2.2KOhm @
2.2KOhm @
1

1
NO_STUFF
9 CFG19

CFG7 : CPU Strap CFG16 : FSB Dynamic ODT CFG20 : SDVO Present
LOW = Reserved LOW = Dynamic ODT Disabled LOW = No SDVO device present (Default)
HIGH = Dothan (Default) HIGH = Dynamic ODT Enabled (Default) HIGH = SDVO device present
+2.5VS
9 CFG7
9 CFG16
B B

2
2

R230 R233
R245
2.2KOhm @ 2.2KOhm @
2.2KOhm @

1
NO_STUFF
1

NO_STUFF
1

NO_STUFF
9 CFG20

CFG[17..3] have internal pullup resistors.

CFG[19..18] have internal pulldown
resistors.

SDVOCRTL_DATA LOW = No SDVO device present (Default)

A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan GMCH Strapping LIBRARY DATE :
2.0 SHEET 13 OF 61
5 4 3 2 1
5 4 3 2 1

U9A
PEG_RXP0 AH30 AJ5 ATI_GPIO0
PEG_RXN0 PCIE_RX0P GPIO_0 ATI_GPIO0 17
AG30 Part 1 of 6 AH5 ATI_GPIO1 ATI_PERF# has internal pull down
PEG_RXP[0..15] PEG_RXP1 PCIE_RX0N GPIO_1 ATI_GPIO1 17
AG29 AJ4 ATI_GPIO2
9 PEG_RXP[0..15] PEG_RXN1 PCIE_RX1P GPIO_2 ATI_GPIO3 ATI_GPIO2 17 1.0V for HIGH
AF29 PCIE_RX1N GPIO_3 AK4 ATI_GPIO3 17
PEG_RXN[0..15] PEG_RXP2 AE29 AH4 ATI_GPIO4 1.2V for LOW
9 PEG_RXN[0..15] PEG_RXN2 PCIE_RX2P GPIO_4 ATI_GPIO4 17
AE30 AF4 ATI_GPIO5
EXP_RXP[0..15] PEG_RXP3 PCIE_RX2N GPIO_5 ATI_GPIO5 17
AD30 AJ3 ATI_GPIO6
9 EXP_RXP[0..15] PEG_RXN3 PCIE_RX3P GPIO_6 ATI_GPIO6 17
AD29 PCIE_RX3N GPIO_7 AK3 R560 1 2 0Ohm PWR_OK_VGA 57
EXP_RXN[0..15] PEG_RXP4 ATI_GPIO8
9 EXP_RXN[0..15] PEG_RXN4
AC29 PCIE_RX4P GPIO_8 AH3
ATI_GPIO9 ATI_GPIO8 17 DVOMODE=VSS 3.3V MODE ZV or GPIO
AB29 PCIE_RX4N GPIO_9 AJ2 ATI_GPIO9 17
PEG_RXP5 ATI_GPIO10 TP4
ER 1.1 -> PR 2.0 PEG_RXN5
AB30 PCIE_RX5P GPIO_10 AH2
ATI_GPIO11
1 DVOMODE=1.8V 1.8V MODE external TMDS
AA30 PCIE_RX5N GPIO_11 AH1 ATI_GPIO11 17
PEG_RXP6 AA29 AG3 ATI_GPIO12
PEG_RXN6 PCIE_RX6P GPIO_12 ATI_GPIO13 ATI_GPIO12 17
Y29 PCIE_RX6N GPIO_13 AG1 ATI_GPIO13 17
D +3VS PEG_RXP7 W29 AG2 1 TP69 D
PEG_RXN7 PCIE_RX7P GPIO_14 LCDDATA18 R48
W30 PCIE_RX7N GPIO_PWRCNTL AF3 ATI_PERF# 57 +1.8VS 1 2 33Ohm @
SDA_MEMSS 15
PEG_RXP8 V30 AF2
PEG_RXN8 PCIE_RX8P GPIO_MEMSSIN MEM_SSIN 15 LCDDATA19 R583 1
U47 V29 2 33Ohm @
PEG_RXP9 PCIE_RX8N DVOMODE SCL_MEMSS 15

DVO / EXT TMDS / GPIO

9,24,27,29,41,44,45 PLT_RST#_3 1 A VCC 5 +3VS U29 PCIE_RX9P DVOVMODE AE10 1 2
PEG_RXN9 T29 R580 10KOhm @ Reserve for memory clock SS
PEG_RXP10 PCIE_RX9N
2 B T30 PCIE_RX10P DVPDATA_0 AH6 1 TP67 1 2
R907 10KOhm U75 PEG_RXN10 R30 AJ6 1 TP1 R579 10KOhm
PEG_RXP11 PCIE_RX10N DVPDATA_1
3 GND 4 1 2 1 A VCC 5 R29 PCIE_RX11P DVPDATA_2 AK6 1 TP2
Y PEG_RXN11 P29 AH7 1 TP66 SR 1.0 -> ER 1.1
PEG_RXP12 PCIE_RX11N DVPDATA_3
TC7SH08FU 2 B N29 PCIE_RX12P DVPDATA_4 AK7 1 TP3

1
R621 0Ohm @ C843 PEG_RXN12 N30 AJ7 1 TP10
PCIE_RST# PEG_RXP13 PCIE_RX12N DVPDATA_5 TP5 +3VS
1 2 3 GND 4 M30 PCIE_RX13P DVPDATA_6 AH8 1
0.22UF Y PEG_RXN13 M29 PCIE_RX13N DVPDATA_7 AJ8 R555 1 2 0Ohm ATI_PANEL_ID0
ER 1.1 -> PR 2.0 c0603 TC7SH08FU PEG_RXP14 R571 1 2 0Ohm ATI_PANEL_ID1 T129 ATI Panel ID

2
L29 PCIE_RX14P DVPDATA_8 AH9 1

2
R913 0Ohm @ PEG_RXN14 K29 AJ9 1 TP6
PCIE_RX14N DVPDATA_9 TPC28t
1 2 PEG_RXP15 K30 AK9 1 TP7 R553
PEG_RXN15 PCIE_RX15P DVPDATA_10 TP8
J30 PCIE_RX15N DVPDATA_11 AH10 1
AE6 1 TP78 22KOhm @
DVPDATA_12 TP71
DVPDATA_13 AG6 1
EXP_RXP0 PEG_TXP0 TP72 ATI_PANEL_ID0

1
1 2 AF26 PCIE_TX0P DVPDATA_14 AF6 1
EXP_RXN0 C610 0.1UF 1 2 PEG_TXN0 AE26 AE7 1 TP75
PCIE_TX0N DVPDATA_15

1
EXP_RXP1 1 2 C611 0.1UF PEG_TXP1 AC25 AF7 1 TP68 No stuff for M26
PCIE_TX1P DVPDATA_16

PCI EXPRESS
EXP_RXN1 C50 0.1UF 1 2 PEG_TXN1 AB25 AE8 1 TP77 R554
EXP_RXP2 C53 0.1UF PEG_TXP2 PCIE_TX1N DVPDATA_17 LCDDATA18 +3VS
1 2 AC27 PCIE_TX2P DVPDATA_18 AG8
EXP_RXN2 C608 0.1UF 1 2 PEG_TXN2 AB27 AF8 LCDDATA19 10KOhm @
EXP_RXP3 C606 0.1UF PEG_TXP3 PCIE_TX2N DVPDATA_19
1 2 AC26 PCIE_TX3P DVPDATA_20 AE9 1 2
EXP_RXN3 C54 0.1UF PEG_TXN3 TP70 R570 8.2KOhm

2
1 2 AB26 PCIE_TX3N DVPDATA_21 AF9 1
EXP_RXP4 1 2 C60 0.1UF PEG_TXP4 Y25 AG10 MEM_ID0 +3VS
EXP_RXN4 C605 0.1UF PEG_TXN4 PCIE_TX4P DVPDATA_22 MEM_ID1 +3VS
1 2 W25 PCIE_TX4N DVPDATA_23 AF10
EXP_RXP5 1 2 C603 0.1UF PEG_TXP5 Y27 PCIE_TX5P

1
EXP_RXN5 C64 0.1UF 1 2 PEG_TXN5 W27 AJ10 DVPCNTL0 1 2 RN11A
C EXP_RXP6 PEG_TXP6 PCIE_TX5N DVPCNTL_0 DVPCNTL1 10KOhm C
1 2 C67 0.1UF Y26 AK10 3 4 RN11B R30
EXP_RXN6 PEG_TXN6 PCIE_TX6P DVPCNTL_1 DVPCNTL2 10KOhm
C600 0.1UF 1 2 W26 AJ11 5 6 RN11C
EXP_RXP7 PEG_TXP7 PCIE_TX6N DVPCNTL_2 DVPCNTL3 10KOhm +3VS
1 2 C597 0.1UF U25 AH11 7 8 RN11D 100Ohm
EXP_RXN7 PEG_TXN7 PCIE_TX7P DVPCNTL_3 10KOhm
C69 0.1UF 1 2 T25
EXP_RXP8 C72 0.1UF PEG_TXP8 PCIE_TX7N

2
1 2 U27 PCIE_TX8P VREFG AG4
EXP_RXN8 C596 0.1UF 1 2 PEG_TXN8 T27 For IO power reference
PCIE_TX8N

1
EXP_RXP9 1 2 C592 0.1UF PEG_TXP9 U26 PCIE_TX9P

1
EXP_RXN9 C79 0.1UF 1 2 PEG_TXN9 T26 AH15 C27 R29 MEM_ID0 R551 2 1 10KOhm
EXP_RXP10 PEG_TXP10 PCIE_TX9N TXOUT_L0N ATI_L1_TX0- 25
1 2 C81 0.1UF P25 AH16 @
EXP_RXN10 PEG_TXN10 PCIE_TX10P TXOUT_L0P ATI_L1_TX0+ 25
C590 0.1UF 1 2 N25 AJ16 0.1UF 100Ohm MEM_ID1 R552 2 1 10KOhm
EXP_RXP11 PEG_TXP11 PCIE_TX10N TXOUT_L1N ATI_L1_TX1- 25
C589 0.1UF @

2
1 2 P27 PCIE_TX11P TXOUT_L1P AJ17 ATI_L1_TX1+ 25
EXP_RXN11 C83 0.1UF PEG_TXN11

2
1 2 N27 PCIE_TX11N TXOUT_L2N AJ18 ATI_L1_TX2- 25
27M_SSIN_X1 R559 0Ohm @ 27M_X1 EXP_RXP12 1 2 C86 0.1UF PEG_TXP12 P26 AK18
15 27M_SSIN_X1 PCIE_TX12P TXOUT_L2P ATI_L1_TX2+ 25

1
EXP_RXN12 C586 0.1UF 1 2 PEG_TXN12 N26 AJ20
27M_SSIN_X2 27M_X2 EXP_RXP13 PEG_TXP13 PCIE_TX12N TXOUT_L3N
R563 0Ohm @ 1 2 C585 0.1UF L25 AJ21 R545 R544
15 27M_SSIN_X2 EXP_RXN13 PEG_TXN13 PCIE_TX13P TXOUT_L3P
C89 0.1UF 1 2 K25 AK19
EXP_RXP14 PEG_TXP14 PCIE_TX13N TXCLK_LN ATI_L1_TXC- 25
1 2 C90 0.1UF L27 AJ19 10KOhm 10KOhm
XTALIN EXP_RXN14 PEG_TXN14 PCIE_TX14P TXCLK_LP ATI_L1_TXC+ 25
R69 0Ohm @ C583 0.1UF

LVDS
15 27M_SSOUT 1 2 K27 PCIE_TX14N TXOUT_U0N AG16
EXP_RXP15 C581 0.1UF PEG_TXP15

2
1 2 L26 PCIE_TX15P TXOUT_U0P AG17
R68 0Ohm @ XTALOUT EXP_RXN15 C94 0.1UF 1 2 PEG_TXN15 K26 AF16
PCIE_TX15N TXOUT_U1N
C97 0.1UF AF17
TXOUT_U1P
Reserve for memory clock SS TXOUT_U2N AE18
6 CLK_PCIE_PEG AF27 PCIE_REFCLKP TXOUT_U2P AE19
6 CLK_PCIE_PEG# AE27 PCIE_REFCLKN TXOUT_U3N AF19
TXOUT_U3P AF20
+3VS +3VS +1.2VSP
TXCLK_UN AG19 MEM_ID1 MEM_ID0
R587 1 2 150Ohm AC23 AG20
PCIE_CALRP TXCLK_UP
R585 1 2 100Ohm AB24 PCIE_CALRN
2

R65 Internal 2 1 R586 1 2 10KOhm AB23 AE12 0 0 HYNIX 64MB

PCIE_CALI DIGON LCD_ENVDD 9,25
10KOhm R37 10KOhm @ AG12
@
pull straping for A21 BLON LCD_ENBACK 9,25
1 2 AE25 PCIE_TEST
down R18 10KOhm @ AK13 0 1 HYNIX 128MB
B PCIE_RST# TX0M B
AD25 PERSTb TX0P AJ13
M26_EN#
1

+3VS 2 1 AD24 PERSTb_MASK TX1M AJ14

R40 10KOhm @ R22 715 Ohm AJ15 1 0 Samsung 64MB
TX1P
M26: install when disable M26 1 2 1 2 AH21 R2SET TX2M AK15
R20 1KOhm AK16
R224 1 TX2P
9,24 TV_DACB_OUT 2 0Ohm AK21 Y_G TXCM AJ12 1 1 Samsung 128MB
R226 1 2 0Ohm AJ22 AK12 SR 1.0 -> ER 1.1
9,24 TV_DACC_OUT C_R_PR TXCP
R213 1 2 0Ohm AK22
9,24 TV_DACA_OUT COMP_B_PB
AE13 LVDS_DDC2BC 9,25

TMDS
R63 2 DDC2CLK
1 150Ohm 1 AJ24 H2SYNC DDC2DATA AE14 LVDS_DDC2BD 9,25
R66 2 1 150Ohm TP73 1 M26_EN# AK24 V2SYNC
Internal pull down
R569 2 1 150Ohm TP9 AF12 1 2
HPD1 R576 100KOhm @
1 AG22 DDC3CLK
TP74 1 AG23 AK27 R188 1 2 0Ohm
DDC3DATA R R 9,24
DAC2
TP12 AJ27 R186 1 2 0Ohm PLACE RGB TERMINATION
G G 9,24
R568 1KOhm AJ26 R187 1 2 0Ohm
B B 9,24 RESISTORS CLOSE TO ASIC
1 2 AJ23 SSIN
1 AH24 AJ25 R207 1 2 0Ohm R564 1 2 150Ohm
SSOUT HSYNC HSYNC 9,24
CLK SS

R64 0Ohm TP11 AK25 R206 1 2 0Ohm R562 1 2 150Ohm

6 CLK_ATI27 27MHZ_XTALIN VSYNC VSYNC 9,24
R557 1 2 150Ohm
27M_X1 R62 0Ohm XTALIN AH28 AH26 M24_RSET 1 2
XTALIN RSET
X2 27Mhz @ @ R41 499Ohm
DAC1

1 2 27M_X2 R60 0Ohm XTALOUT AJ29 AG25

XTALOUT DDC1DATA DDC2BD 9,24
@ AF24
DDC1CLK DDC2BC 9,24
R61 1MOhm 1 2 AH27 AG24 GPIO_AUX 2 1 IF GPIO_AUXWIN
TESTEN GPIO__AUXWIN
@ R17 1KOhm E8 R21 10KOhm IS NOT USED PULL IT TO GND
TEST_YCLK
1

B6 TEST_MCLK
THERM

C23 C22 1 AF25 AF11

PLLTEST DPLUS VGA_THERM_DA 7
R908 12PF/50V 12PF/50V TP13 AE11
XTALIN DMINUS VGA_THERM_DC 7
27MHZ_XTALIN @ @
2

1 2 2 1 AH25 STEREOSYNC
R19 10KOhm
A 121Ohm A
2

R909
Vxtalin=1.18V M24_P
86.6Ohm
1

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan M24-P - MAIN (1) LIBRARY DATE :
2.0 SHEET 14 OF 61

WWW.AliSaler.Com 5 4 3 2 1
5 4 3 2 1

MAA[0:13] 18
18 MDA[0:63] 19 MDB[0:63] MAB[0:13] 19
U9B U9C
MDA0 H28 E22 MAA0 MDB0 D7 N5 MAB0
MDA1 DQA0 Part 2 of 6 MAA0 MAA1 MDB1 DQB0 Part 3 of 6 MAB0 MAB1
H29 DQA1 MAA1 B22 F7 DQB1 MAB1 M1
MDA2 J28 B23 MAA2 MDB2 E7 M3 MAB2
MDA3 DQA2 MAA2 MAA3 MDB3 DQB2 MAB2 MAB3
J29 DQA3 MAA3 B24 G6 DQB3 MAB3 L3
MDA4 J26 C23 MAA4 MDB4 G5 L2 MAB4
MDA5 DQA4 MAA4 MAA5 MDB5 DQB4 MAB4 MAB5
H25 DQA5 MAA5 C22 F5 DQB5 MAB5 M2
MDA6 H26 F22 MAA6 MDB6 E5 M5 MAB6
MDA7 DQA6 MAA6 MAA7 MDB7 DQB6 MAB6 MAB7
G26 DQA7 MAA7 F21 C4 DQB7 MAB7 P6
MDA8 G30 C21 MAA8 MDB8 B5 N3 MAB8
MDA9 DQA8 MAA8 MAA9 MDB9 DQB8 MAB8 MAB9
D29 DQA9 MAA9 A24 C5 DQB9 MAB9 K2
D MDA10 D28 C24 MAA10 MDB10 A4 K3 MAB10 D
MDA11 DQA10 MAA10 MAA11 MDB11 DQB10 MAB10 MAB11
E28 DQA11 MAA11 A25 B4 DQB11 MAB11 J2
MDA12 E29 E21 MAA12 MDB12 C2 P5 MAB12
MDA13 DQA12 MAA12 MAA13 MDB13 DQB12 MAB12 MAB13
G29 DQA13 MAA13 B20 DQMA#[0:7] 18 D3 DQB13 MAB13 P3 DQMB#[0:7] 19
MDA14 G28 C19 MDB14 D1 P2
MDA15 DQA14 MAA14 MDB15 DQB14 MAB14
F28 DQA15 D2 DQB15
MDA16 G25 J25 DQMA#0 MDB16 G4 E6 DQMB#0
MDA17 DQA16 DQMA#0 DQMA#1 MDB17 DQB16 DQMB#0 DQMB#1
F26 DQA17 DQMA#1 F29 H6 DQB17 DQMB#1 B2
MDA18 E26 E25 DQMA#2 MDB18 H5 J5 DQMB#2
MDA19 DQA18 DQMA#2 DQMA#3 MDB19 DQB18 DQMB#2 DQMB#3
F25 DQA19 DQMA#3 A27 J6 DQB19 DQMB#3 G3
MDA20 E24 F15 DQMA#4 MDB20 K5 W6 DQMB#4
MDA21 DQA20 DQMA#4 DQMA#5 MDB21 DQB20 DQMB#4 DQMB#5
F23 DQA21 DQMA#5 C15 K4 DQB21 DQMB#5 W2
MDA22 E23 C11 DQMA#6 MDB22 L6 AC6 DQMB#6
MDA23 DQA22 DQMA#6 DQMA#7 MDB23 DQB22 DQMB#6 DQMB#7
D22 DQA23 DQMA#7 E11 QSA[0:7] 18 L5 DQB23 DQMB#7 AD2 QSB[0:7] 19
MDA24 B29 MDB24 G2
MDA25 DQA24 QSA0 MDB25 DQB24 QSB0
C29 DQA25 QSA0 J27 F3 DQB25 QSB0 F6
MDA26 C25 F30 QSA1 MDB26 H2 B3 QSB1
MDA27 DQA26 QSA1 QSA2 MDB27 DQB26 QSB1 QSB2
C27 DQA27 QSA2 F24 E2 DQB27 QSB2 K6
MDA28 B28 B27 QSA3 MDB28 F2 G1 QSB3
MDA29 DQA28 QSA3 QSA4 MDB29 DQB28 QSB3 QSB4
B25 DQA29 QSA4 E16 J3 DQB29 QSB4 V5
MDA30 C26 B16 QSA5 MDB30 F1 W1 QSB5
MDA31 DQA30 QSA5 QSA6 MDB31 DQB30 QSB5 QSB6
B26 DQA31 QSA6 B11 H3 DQB31 QSB6 AC5
MDA32 F17 F10 QSA7 MDB32 U6 AD1 QSB7
MDA33 DQA32 QSA7 MDB33 DQB32 QSB7
E17 DQA33 U5 DQB33
MDA34 D16 A19 RASA# MDB34 U3 R2 RASB#
MDA35 DQA34 RASA# RASA# 18 MDB35 DQB34 RASB# RASB# 19
F16 DQA35 V6 DQB35
MDA36 E15 E18 CASA# MDB36 W5 T5 CASB#
MDA37 DQA36 CASA# CASA# 18 MDB37 DQB36 CASB# CASB# 19
F14 DQA37 W4 DQB37
MDA38 E14 E19 WEA# MDB38 Y6 T6 WEB#
MDA39 DQA38 WEA# WEA# 18 MDB39 DQB38 WEB# WEB# 19
F13 DQA39 Y5 DQB39
MDA40 C17 E20 CSA0# MDB40 U2 R5 CSB0#
MDA41 DQA40 CSA0# CSA0# 18 MDB41 DQB40 CSB0# CSB0# 19
B18 DQA41 V2 DQB41
C MDA42 B17 F20 CSA1# MDB42 V1 R6 CSB1# C
MDA43 DQA42 CSA1# CSA1# 18 MDB43 DQB42 CSB1# CSB1# 19
B15 DQA43 V3 DQB43
MDA44 C13 B19 CKEA MDB44 W3 R3 CKEB
MDA45 DQA44 CKEA CKEA 18 MDB45 DQB44 CKEB CKEB 19
B14 DQA45 Y2 DQB45
MDA46 C14 MDB46 Y3 N1 CLKB0
MDA47 DQA46 DQB46 CLKB0 CLKB0 19
C16 DQA47 CLKA0 B21 CLKA0 CLKA0 18
MDB47 AA2 DQB47 CLKB0# N2 CLKB0#
CLKB0# 19
MDA48 A13 C20 CLKA0# MDB48 AA6
MDA49 DQA48 CLKA0# CLKA0# 18 MDB49 DQB48 CLKB1
A12 DQA49 AA5 DQB49 CLKB1 T2 CLKB1 19
MDA50 C12 C18 CLKA1 MDB50 AB6 T3 CLKB1#
MDA51 DQA50 CLKA1 CLKA1 18 DQB50 CLKB1# CLKB1# 19
B12 DQA51 CLKA1# A18 CLKA1# CLKA1# 18
MDB51 AB5 DQB51
MDA52 C10 MDB52 AD6
MDA53 DQA52 MDB53 DQB52
C9 DQA53 AD5 DQB53 DIMB_0 E3
MDA54 B9 +ATI_MEM +ATI_MEM MDB54 AE5 AA3 +3VS
MDA55 DQA54 MDB55 DQB54 DIMB_1 +1.8VS
B10 DQA55 MVREFD B7 AE4 DQB55
MDA56 E13 MDB56 AB2
DQA56 DQB56
1

1
MDA57 E12 B8 MDB57 AB3 AF5 1 2
MDA58 DQA57 MVREFS R147 R79 MDB58 DQB57 ROMCS# R77 10KOhm R595 4.7KOhm @
E10 DQA58 AC2 DQB58
MDA59 F12 MDB59 AC3 C6 1 2
MDA60 DQA59 100Ohm 100Ohm MDB60 DQB59 MEMVMODE_0
F11 DQA60 DIMA_0 D30 AD3 DQB60 MEMVMODE_1 C7 1 2
MDA61 E9 B13 MDB61 AE1 R596 4.7KOhm
MDA62 DQA61 DIMA_1 MDB62 DQB61
2

2
F9 DQA62 AE2 DQB62 MEMTEST C8
MDA63 F8 MDB63 AE3
DQA63 DQB63

1
M24_P M24_P R593 R597 R594
1

1
1

1
R149 C114 R152 C118 47 OHM 1/16W 4.7KOhm 4.7KOhm
@
100Ohm 0.1UF 100Ohm 0.1UF

2
2

2
2

B B
VDDR1 MEMVMODE_0 MEMVMODE_1

1.8V GND +1.8VS

2.5V +1.8VS GND

+1.8VS +3VS
R558 1KOhm @ +3VS
2 1 R566 8.2KOhm @
U41 2 1 L67 120Ohm/100Mhz@
14 27M_SSIN_X1 2 X1_CLKIN VDD 6 1 2
14 27M_SSIN_X2 3 X2 VDDA 5 1 2
16 R561 10Ohm @
VDDREF
12 PD#
15 R578 75Ohm @
VDDREFSEL25_3#
9 SSEN/FS1 VDDO1/REFOUT 14 1.8VS 1 2 1.2VS 27M_SSOUT 14
R567 22.1Ohm @
13 REF_STOP CLKOUT/FS0 8 1 2 MEM_SSIN 14
1

2
C506 C515 C521 C520
11 1 R582
14 SCL_MEMSS SCLK GND0
10 7 0.1UF @ 22UF/6.3V @ 0.1UF @ 22UF/6.3V @
14 SDA_MEMSS SDA GND1 150Ohm @
2

GNDA 4
2

R584 ICS91719AG_T
1

A @ A
8.2KOhm
@ Internal pull down: FS_IN0, REF_OUT(pin14), REF_Stop
1

Internal pull up: FS_IN1, VDDREF(pin15), PD#

Reserve for memory clk SS

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan M24-P - MEMORY INTERFACE (2) LIBRARY DATE :
2.0 SHEET 15 OF 61
5 4 3 2 1
5 4 3 2 1

U9F
+3VS P17 M16
VDDC16 Part 6 of 6 VSS201
DIODE SUPPLIES POWER P18 VDDC17 VSS207 N16
TO VDDC RAIL +3VS P19 N15
VDDC18 VSS206
WHILE VDDC REGULATOR U12 VDDC19 VSS213 P15
STABALIZES DURING POWER ON U13 VDDC20 VSS214 P16

1
U14 VDDC21 VSS227 R18
2.4V D34 D32 2.4V U17 R17
VDDC22 VSS226
MMSZ4681T1 MMSZ4681T1
1.2V +/- 30mV U18
U19
VDDC23 VSS225 R16
R15
@ @ +ATI_VCORE MAX:8A V19
VDDC24
VDDC30
VSS224
VSS223 R14
D D

2
V18 VDDC29 VSS222 R13
+ATI_MEM CE11 U9D V17 R12
150U/4.0V VDDC28 VSS221

CENTER ARRAY
V14 VDDC27 VSS233 T13
VDDR1_VDDM T7 Part 4 of 6 AC13 V13 T14
VDDR1_45 VDDC37 VDDC26 VSS234
R4 VDDR1_44 VDDC40 AD13 V12 VDDC25 VSS235 T15
R1 VDDR1_43 VDDC41 AD15 N18 VDDC11 VSS263 W15
1

C561

C554

C544

C545

C526

C547

C536

C539

C546

C557

C543

C556

C542

C541

C553

C559
C584 C576 C578 C579 C574 C577 C572 C575 C582 + N8 AC15 + N17 V16
VDDR1_42 VDDC38 VDDC10 VSS254

1
N7 AC17 CE10 C530 N14 V15
0.1UF 1000PF 0.1UF 1000PF 0.1UF 1000PF 0.1UF 1000PF 0.1UF VDDR1_41 VDDC39 VDDC9 VSS253
M4 VDDR1_39 W17 VDDC34 VSS246 U15

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF
220UF/2V 10uF/10V
2

2
L8 VDDR1_37 VDD15_4 P8 W18 VDDC35 VSS247 U16
@

2
K23 VDDR1_35 VDD15_5 Y8 W12 VDDC31 VSS239 T19
K24 VDDR1_36 VDD15_7 AC11 W13 VDDC32 VSS238 T18
N4 VDDR1_40 VDD15_8 AC20 W14 VDDC33 VSS237 T17
J8 VDDR1_34 VDD15_2 H20 N13 VDDC8 VSS236 T16
J7 H11 L79 120Ohm/100Mhz N19
VDDR1_33 VDD15_1 +VDDC_CT VDDC12
J4 VDDR1_32 VDD15_3 M23 1 2 +1.5VS M19 VDDC6
J1 VDDR1_31 VDD15_6 Y23 M18 VDDC5

1
+MPVDD / 10mA +PNL_PLL / 15mA H10 VDDR1_25 M12 VDDC1
H13 AD7 C567 C571 C562 C522 N12
+PVDD / 30mA +PNL_IO / 60mA VDDR1_26 VDDR3_5 10uF/10V 0.1UF 0.1UF 0.1UF +ATI_VCORE VDDC7
H15 VDDR1_27 VDDR3_6 AD19 M13 VDDC2
+VDDI / 10mA +LVDDR_25 / 200mA L72 VDDC

2
H17 VDDR1_28 VDDR3_7 AD21 M14 VDDC3 VDDCI4 W16
+AVDD / 70mA +VDDC_CT / 40mA T8 AC22 120Ohm/100Mhz P12 M15
VDDR1_46 VDDR3_4 L68 VDDC VDDC13 VDDCI1
V4 VDDR1_47 VDDR3_1 AC8 1 2 P13 VDDC14 VDDCI2 R19
+A2VDDQ / 5mA PCIE_VDDR & PCIE_PVDD_12 / 1.52A V7 AC21 1 2 +3VS P14 T12
VDDR1_48 VDDR3_3 VDDC15 VDDCI3

1
+A2VDD / 80mA PCIE_PVDD_18 / 180mA V8 VDDR1_49 VDDR3_2 AC19 M17 VDDC4
AA1 C529 C527 120Ohm/100Mhz C531 C537 C570 C532 W19
VDDR4 / N/A +ATI_VCORE / 8A VDDR1_50 VDDC36
AA4 AG7 1UF/10V 1UF/10V 0.1UF 0.1UF 0.1UF 0.1UF
VDDR1_VDDM / N/A VDDR1_51 VDDR4_5 M24_P

2
AA7 VDDR1_52 VDDR4_3 AD9
AA8 AC9 +3VS
L8 +A2VDDQ VDDR1_53 VDDR4_1
+1.8VS 1 2 120Ohm/100Mhz A3 VDDR1_1 VDDR4_2 AC10 L69
A9 AD10 1 2 U9E
L7 +AVDD VDDR1_2 VDDR4_4
1 2 120Ohm/100Mhz A15 VDDR1_3 A2 VSS1 VSS242 U4

1
C 120Ohm/100Mhz Part 5 of 6 C
A21 VDDR1_4 PCIE_VDDR_12_1 AG26 A10 VSS3 VSS245 U8
L73 1 2 120Ohm/100MhzPCIE_PVDD_18 A28 AK29 C534 C528 +1.2VSP A16 W7
VDDR1_5 PCIE_VDDR_12_5 10uF/10V 1UF/10V VSS6 VSS261
B1 VDDR1_6 PCIE_VDDR_12_4 AJ30 A22 VSS9 VSS262 W8
L15 2 120Ohm/100Mhz +MPVDD L60

2
1 B30 VDDR1_7 PCIE_VDDR_12_3 AG28 A29 VSS13 VSS266 Y4
D26 AG27 120Ohm/100Mhz C1 AB8
L9 VDDR1_15 PCIE_VDDR_12_2 VSS39 VSS279
1 2 120Ohm/100Mhz +PVDD D23 VDDR1_14
PCIE_VDDR 1 2 C3 VSS41 VSS278 AB7
D20 VDDR1_13 PCIE_PVDD_12_2 N24 C28 VSS63 VSS273 AB1
L63 1 2 120Ohm/100Mhz +PNL_PLL D17 N23 C30 AC4
VDDR1_12 PCIE_PVDD_12_1 VSS65 VSS282

C517

C492

C518

C516
D14 VDDR1_11 PCIE_PVDD_12_3 P23 D27 VSS80 VSS285 AC12

1
D11 VDDR1_10 D24 VSS79 VSS286 AC14
LVDDR R575 D8 U23 C483 C490 D21 AD16
VDDR1_9 PCIE_PVDD_18_2 VSS77 VSS295

0.01UF/16V

0.01UF/16V

0.01UF/16V

0.01UF/16V
0Ohm D5 T23 10uF/10V 1UF/10V D18 AC16
+LVDDR_25 VDDR1_8 PCIE_PVDD_18_1 VSS76 VSS287

2
1 2 E27 VDDR1_16 PCIE_PVDD_18_3 V23 D15 VSS74 VSS288 AC18

CORE GND
F4 VDDR1_17 PCIE_PVDD_18_4 W23 D12 VSS73 VSS296 AD18
1

G7 VDDR1_18 D10 VSS72 VSS306 AK2

C514 C519 G10 VDDR1_19 NC1 D9 VDDR1_VDDM D6 VSS70 VSS305 AJ1
10uF/10V 0.1UF G13 D13 D4
VDDR1_20 NC2 VSS69
2

G15 VDDR1_21 NC3 D19 PCIE_VSS1 K28

G19 D25 PCIE_PVDD_12 1 2 L28
VDDR1_22 NC4 PCIE_VSS2
G22 VDDR1_23 NC5 E4 PCIE_VSS6 M27
G27 T4 L61 F27 M26
VDDR1_24 NC6 VSS132 PCIE_VSS5

C564

C560

C566

C565
H22 AB4 120Ohm/100Mhz G9 M24
VDDR1_30 NC7 VSS142 PCIE_VSS3

1
+PNL_PLL H19 G12 M25
VDDR1_29 C484 C491 VSS143 PCIE_VSS4
AD4 VDDR1_54 G16 VSS144 PCIE_VSS7 M28
1

0.01UF/16V

0.01UF/16V

0.01UF/16V

0.01UF/16V
C489 C488 C487 L23 10uF/10V 1UF/10V G18 P28
C493 VDDR1_38 VSS145 PCIE_VSS9

2
G21 VSS146 PCIE_VSS8 N28
10uF/10V 1UF/10V 1UF/10V 100PF G24 R25
VSS147 PCIE_VSS12
2

H27 VSS168 PCIE_VSS10 R23

AVSSQ AD22 H23 VSS165 PCIE_VSS11 R24
H21 VSS164 PCIE_VSS13 R26
+1.8VS H18 R27
L64 120Ohm/100Mhz PCIE_PVDD_18 VSS163 PCIE_VSS14
AE16 LVDDR_25_1 LVSSR1 AF18 H16 VSS162 PCIE_VSS15 R28
B 1 2 +PNL_IO AE17 AH17 H14 T28 B
LVDDR_25_2 LVSSR4 VSS161 PCIE_VSS17
AF15 LVDDR_18_1 LVSSR2 AG15 H12 VSS160 PCIE_VSS16 T24
1

C548

C552

C551

C549
C507 AE15 AG18 H9 U28
LVDDR_18_2 LVSSR3 VSS159 PCIE_VSS18

1
C504 C508 H8 V24
10uF/10V 1UF/10V 100PF C535 C538 VSS158 PCIE_VSS19
H4 VSS155 PCIE_VSS21 V26

0.01UF/16V

0.01UF/16V

0.01UF/16V

0.01UF/16V
1UF/10V 1UF/10V
2

AH19 LPVDD LPVSS AH18 J23 VSS175 PCIE_VSS22 V27

2
AH13 TPVDD TPVSS AH12 J24 VSS176 PCIE_VSS20 V25
PCIE_VSS23 V28
L78 120Ohm/100Mhz AF13 AH14 Y28
+ATI_MEM VDD_MEM_CLK TXVDDR1 TXVSSR3 PCIE_VSS26
1 2 AF14 TXVDDR2 TXVSSR1 AG13 AD12 VSS294 PCIE_VSS24 W24
+2.5VS AG14 AG5 W28
TXVSSR2 VSS302 PCIE_VSS25
1

AG9 VSS303 PCIE_VSS30 AA26

C573 C568 C569 F18 F19 AG11 AA27
VDDRH0 VSSRH0 VSS304 PCIE_VSS31
2

10uF/10V 0.1UF 1000PF N6 M6 AA23

L66 VDDRH1 VSSRH1 PCIE_VSS27
2

PCIE_VSS28 AA24
120Ohm/100Mhz
POWER

Power Sequence: R7 VSS219 PCIE_VSS29 AA25

AF21 A2VDD2 A2VSSN2 AH20 VDDR3(3VS)-->VDDR4(3VS or 1.8VS) < 1ms P4 VSS210 PCIE_VSS32 AA28
+A2VDD
1

AE20 A2VDD1 A2VSSN1 AG21 M7 VSS199 PCIE_VSS33 AB28

VDDR3(3VS)-->VDDR1(1.8VS) < 1ms M8 AC28
VSS200 PCIE_VSS34
1

+A2VDDQ
I/O

AF23 A2VDDQ A2VSSQ AF22 VDDR4(3VS)-->VDDC(VCORE) < 1ms L4 VSS192 PCIE_VSS37 AD28
C505 C510 K1 AD26
PCIE_PVDD_18(1.8VS)-->PCIE_PVDD_12(1.2VS) > 0 VSS182 PCIE_VSS35
1

10uF/10V 1UF/10V +AVDD AH23 AH22 K7 AD27

C31 C41 AVDD AVSSN VSS188 PCIE_VSS36
PCIE_PVDD_12(1.2VS)-->VDDC(VCORE) > 0
2

K8 VSS189 PCIE_VSS38 AE28

1

10uF/10V 1UF/10V R8 AF28

VDDC(VCORE)-->VDD_15(1.5VS) < 1ms VSS220 PCIE_VSS39
C30 C40
2

AE23 VDD1DI VSS1DI AE24 T1 VSS228 PCIE_VSS40 AH29

10uF/10V 1UF/10V +VDDI AE22 AE21
VDD2DI VSS2DI M24_P
Conclusion:
2

L10 +PVDD +3VS ----> 1.8VS ----> 1.2VSP ----> VCORE ----> 1.5VS
AK28 PVDD PVSS AJ28
1 2 <1ms >0ms >0ms <1ms
+1.8VS
+MPVDD A7 A6 ------------------------------> VCORE
MPVDD MPVSS
1

120Ohm/100Mhz
<1ms
1

A C29 C39 A
10uF/10V 1UF/10V C28 C38 C116 C115 M24_P
10uF/10V 1UF/10V 10uF/10V 1UF/10V
2

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan M24-P - POWER (3) LIBRARY DATE :
2.0 SHEET 16 OF 61

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5 4 3 2 1
5 4 3 2 1

D D

STRAPS PIN DESCRIPTION ASIC DEFAULT

OPTION STRAPS
B_PTX_PWRS_ENB GPIO0 Transmitter Power Savings Enable 0
0: 50% Tx output swing for mobile mode
1: full Tx output swing
+3VS
B_PTX_DEEMPH_EN GPIO1 Transmitter De-emphasis Enable 0
0: Tx de-emphasis disable for mobile mode
1: Tx de_emphasis enable
ATI_GPIO0 1 2
14 ATI_GPIO0
R44 10KOhm
PCIE_MODE(1:0) GPIO(3:2) 00: PCI Express 1.0A mode 00
ATI_GPIO1 1 2 01: Kyrene-compatible mode
14 ATI_GPIO1
R43 10KOhm @ 10: PCI Express 1.0 mode
ATI_GPIO2 11: PCI Express 1.0A mode and short-circuit internal
14 ATI_GPIO2 1 2
R46 10KOhm @
B_PTX_IEXT GPIO4 0: normal mode 0
ATI_GPIO3 1 2 1: extra current in Tx output stage
C 14 ATI_GPIO3 C
R47 10KOhm @

ATI_GPIO4 1 2 FORCE_COMPLIANCE GPIO5 Force chip to go to compliance state quickly for test purposes 0
14 ATI_GPIO4
R45 10KOhm @

ATI_GPIO5 1 2 B_PPLL_BW GPIO6 0: Full PLL Bandwidth 0

14 ATI_GPIO5
R72 10KOhm @ 1: Reduce PLL Bandwidth
ATI_GPIO6 1 2
14 ATI_GPIO6
R67 10KOhm @ DEBUG_ACCESS GPIO8 Strap to set the debug muxes to bring out DEBUG signals 0
even if registers are inaccessible.
ATI_GPIO11 1 2
14 ATI_GPIO11
R78 10KOhm @
ROMIDCFG(3:0) GPIO(9,13:11) If no ROM attached, comtrols chip IDis. If rom attached identifies ROM type 0000
ATI_GPIO12 1 2 0000 - No ROM, CHG_ID=0
14 ATI_GPIO12
R74 10KOhm @ 0001 - No ROM, CHG_ID=1
0100 - reserved
ATI_GPIO13 1 2 0110 - reserved
14 ATI_GPIO13
R80 10KOhm @ 1000 - Parallel ROM, chip IDis from ROM
1001 - Serial AT25F1024 ROM (Atmel), chip IDis from ROM
ATI_GPIO9 1 2 1010 - Serial AT45DB011 ROM (Atmel), chip IDis from ROM
14 ATI_GPIO9
R71 10KOhm @ 1011 - Serial M25P10 ROM (ST), chip IDis from ROM
1100 - Serial M25P05 ROM (ST), chip IDis from ROM
ATI_GPIO8 1 2 1100 - Serial NX25F011B ROM (ISSI), chip IDis from ROM
14 ATI_GPIO8
R42 10KOhm @

DVPDATA_20 0: Slave VIP host port device peesent 0

1: No slave VIP host port device

GPIO[0:13] : Internal PD
M26: GPIO11 is memory aperture (0=128M 1=256M)
B B

A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan M22-P - STRAPING (4) LIBRARY DATE :
2.0 SHEET 17 OF 61
5 4 3 2 1
5 4 3 2 1

15 MAA[0:13]
U45 MDA[0:31] 15 U46 MDA[32:63] 15
MAA12 N4 B8 MDA9 MAA12 N4 B8 MDA51
MAA13 BA0 DQ31 MDA10 MAA13 BA0 DQ31 MDA49
M5 BA1 DQ30 C9 M5 BA1 DQ30 C9
B9 MDA11 B9 MDA55
MAA11 DQ29 MDA12 MAA11 DQ29 MDA50
M7 A11 DQ28 B10 M7 A11 DQ28 B10
MAA10 L6 C13 MDA15 MAA10 L6 C13 MDA52
MAA9 A10 DQ27 MDA14 MAA9 A10 DQ27 MDA53
M8 A9 DQ26 D12 M8 A9 DQ26 D12
MAA8 N11 D13 MDA8 MAA8 N11 D13 MDA54
MAA7 A8/AP DQ25 MDA13 MAA7 A8/AP DQ25 MDA48
MAA6
N10
N9
A7 DQ24 E13
K3 MDA22 MAA6
N10
N9
A7 DQ24 E13
K3 MDA39 ALLOW FOOTPRINTS FOR
A6 DQ23 A6 DQ23
MAA5
MAA4
M9 A5 DQ22 K2 MDA23
MDA21
MAA5
MAA4
M9 A5 DQ22 K2 MDA33
MDA35
DIFFERENTIAL MEMORY CLOCKS
N8 J2 N8 J2
D MAA3 N7
A4 DQ21
J3 MDA20 MAA3 N7
A4 DQ21
J3 MDA37 TERMINATING R/C COMPONENTS D
MAA2 A3 DQ20 MDA18 MAA2 A3 DQ20 MDA36
MAA1
M6
N6
A2 DQ19 G2
G3 MDA19 MAA1
M6
N6
A2 DQ19 G2
G3 MDA34 PLACED CLOSE TO THE MEMORIES
A1 DQ18 A1 DQ18
MAA0 N5 A0 DQ17 F2 MDA16 MAA0 N5 A0 DQ17 F2 MDA38 INSTALL WITH 56R/470PF AS DEFAULT
F3 MDA17 F3 MDA32
DQ16 MDA7 DQ16 MDA46
DQ15 F12 DQ15 F12
CLKA0_R M11 F13 MDA6 CLKA1_R M11 F13 MDA44
CLK DQ14 MDA5 CLK DQ14 MDA45 R151 1 CLKA0_R
DQ13 G12 DQ13 G12 15 CLKA0 2 10Ohm
CLKA0#_R M12 G13 MDA4 CLKA1#_R M12 G13 MDA43
CLK# DQ12 MDA3 CLK# DQ12 MDA47 R150 1 CLKA0#_R
DQ11 J12 DQ11 J12 15 CLKA0# 2 10Ohm
CKEA N12 J13 MDA2 CKEA N12 J13 MDA42
15 CKEA CKE DQ10 MDA1 CKE DQ10 MDA41
DQ9 K12 DQ9 K12

2
CSA0# N2 K13 MDA0 CSA0# N2 K13 MDA40
15 CSA0# CS# DQ8 MDA29 CS# DQ8 MDA56
E2 E2 R156 R155
RASA# DQ7 MDA30 RASA# DQ7 MDA60
15 RASA# M2 RAS# DQ6 D2 M2 RAS# DQ6 D2
D3 MDA27 D3 MDA59 56Ohm 56Ohm
CASA# DQ5 MDA31 CASA# DQ5 MDA57
15 CASA# L2 CAS# DQ4 C2 L2 CAS# DQ4 C2
MDA26 MDA61

1
DQ3 B5 DQ3 B5
WEA# L3 B6 MDA28 WEA# L3 B6 MDA58
15 WEA# WE# DQ2 MDA24 WE# DQ2 MDA63
+ATI_MEM +ATI_MEM
DQ1 C6 DQ1 C6 PLACED CLOSE TO

1
B7 MDA25 B7 MDA62
DQ0 DQ0
THE M24-P(U61) C129
QSA1 B13 C3 QSA6 B13 C3 470PF/50V
15 QSA1 DQS3 VDDQ1 15 QSA6 DQS3 VDDQ1

2
VDDQ2 C5 VDDQ2 C5
QSA2 H2 C7 QSA4 H2 C7
15 QSA2 DQS2 VDDQ3 15 QSA4 DQS2 VDDQ3
VDDQ4 C8 VDDQ4 C8
QSA0 H13 C10 QSA5 H13 C10
15 QSA0 DQS1 VDDQ5 15 QSA5 DQS1 VDDQ5
VDDQ6 C12 VDDQ6 C12
QSA3 B2 E3 QSA7 B2 E3
15 QSA3 DQS0 VDDQ7 15 QSA7 DQS0 VDDQ7 CLKA1_R
E12 E12 R145 1 2 10Ohm
VDDQ8 VDDQ8 15 CLKA1
VDDQ9 F4 VDDQ9 F4
DQMA#1 B12 F11 DQMA#6 B12 F11 R146 1 2 10Ohm CLKA1#_R
C 15 DQMA#1 DM3 VDDQ10 15 DQMA#6 DM3 VDDQ10 15 CLKA1# C
VDDQ11 G4 VDDQ11 G4
DQMA#2 H3 G11 DQMA#4 H3 G11
15 DQMA#2 DM2 VDDQ12 15 DQMA#4 DM2 VDDQ12

2
VDDQ13 J4 VDDQ13 J4
DQMA#0 H12 J11 DQMA#5 H12 J11 R153 R154
15 DQMA#0 DM1 VDDQ14 15 DQMA#5 DM1 VDDQ14 +ATI_MEM
K4 +ATI_MEM K4
DQMA#3 VDDQ15 DQMA#7 VDDQ15 56Ohm 56Ohm
15 DQMA#3 B3 DM0 VDDQ16 K11 15 DQMA#7 B3 DM0 VDDQ16 K11

+ATI_MEM +ATI_MEM

1
VDD1 D7 VDD1 D7
N13 VREF VDD2 D8 N13 VREF VDD2 D8
VDD3 E4 VDD3 E4
1

1
M13 MCL VDD4 E11 M13 MCL VDD4 E11
R175 L4 R171 L4 C126
VDD5 VDD5
L9 RFU1 VDD6 L7 L9 RFU1 VDD6 L7 470PF/50V
1KOhm 1KOhm

2
VDD7 L8 VDD7 L8
M10 RFU2 VDD8 L11 M10 RFU2 VDD8 L11
2

2
C4 NC1 VSSQ1 B4 C4 NC1 VSSQ1 B4
1

1
C11 NC2 VSSQ2 B11 C11 NC2 VSSQ2 B11
1

1
R174 C151 H4 D4 R173 C150 H4 D4
NC3 VSSQ3 NC3 VSSQ3 +ATI_MEM
H11 NC4 VSSQ4 D5 H11 NC4 VSSQ4 D5
1KOhm 0.1UF L12 D6 1KOhm 0.1UF L12 D6
NC5 VSSQ5 NC5 VSSQ5
2

2
L13 NC6 VSSQ6 D9 L13 NC6 VSSQ6 D9
2

2
M3 NC7 VSSQ7 D10 M3 NC7 VSSQ7 D10

1
M4 NC8 VSSQ8 D11 M4 NC8 VSSQ8 D11
N3 E6 CSA1# N3 E6 C119 C139 C120 C143 C121 C141 C132 C142 C127 C147
15 CSA1# NC9 VSSQ9 NC9 VSSQ9
VSSQ10 E9 VSSQ10 E9 0.1UF 1UF/6.3V 1000P 0.01UF/16V 22UF/6.3V 0.1UF 1UF/6.3V 1000P 0.01UF/16V 22UF/6.3V

2
VSSQ11 F5 VSSQ11 F5
VSSQ12 F10 VSSQ12 F10
VSSQ13 G5 VSSQ13 G5
VSSQ14 G10 VSSQ14 G10
VSSQ15 H5 VSSQ15 H5
F6 VSS TH1 VSSQ16 H10 F6 VSS TH1 VSSQ16 H10
B F7 J5 F7 J5 B
VSS TH2 VSSQ17 VSS TH2 VSSQ17 +ATI_MEM
F8 VSS TH3 VSSQ18 J10 F8 VSS TH3 VSSQ18 J10
F9 VSS TH4 VSSQ19 K5 F9 VSS TH4 VSSQ19 K5
G6 VSS TH5 VSSQ20 K10 G6 VSS TH5 VSSQ20 K10
G7 VSS TH6 G7 VSS TH6

1
G8 VSS TH7 VSS1 E5 G8 VSS TH7 VSS1 E5
G9 E7 G9 E7 C125 C140 C144 C130 C145 C137 C123 C124 C131 C133
VSS TH8 VSS2 VSS TH8 VSS2
H6 VSS TH9 VSS3 E8 H6 VSS TH9 VSS3 E8 0.1UF 1UF/6.3V 1000P 0.01UF/16V 22UF/6.3V 0.1UF 1UF/6.3V 1000P 0.01UF/16V 22UF/6.3V

2
H7 VSS TH10 VSS4 E10 H7 VSS TH10 VSS4 E10
H8 VSS TH11 VSS5 K6 H8 VSS TH11 VSS5 K6
H9 VSS TH12 VSS6 K7 H9 VSS TH12 VSS6 K7
J6 VSS TH13 VSS7 K8 J6 VSS TH13 VSS7 K8
J7 VSS TH14 VSS8 K9 J7 VSS TH14 VSS8 K9
J8 VSS TH15 VSS9 L5 J8 VSS TH15 VSS9 L5
J9 VSS TH16 VSS10 L10 J9 VSS TH16 VSS10 L10

HY5DS573222F_33 HY5DS573222F_33

Samsung 03-15124E011
Hynix 03-15124E120HQ
A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan M24-C - DDR MEMORY A LIBRARY DATE :
2.0 SHEET 18 OF 61

WWW.AliSaler.Com 5 4 3 2 1
5 4 3 2 1

15 MAB[0:13] U43 MDB[0:31] 15 U42 MDB[32:63] 15

MAB12 N4 B8 MDB14 MAB12 N4 B8 MDB56
MAB13 BA0 DQ31 MDB15 MAB13 BA0 DQ31 MDB59
M5 BA1 DQ30 C9 M5 BA1 DQ30 C9
B9 MDB13 B9 MDB57
MAB11 DQ29 MDB12 MAB11 DQ29 MDB58
M7 A11 DQ28 B10 M7 A11 DQ28 B10
MAB10 L6 C13 MDB8 MAB10 L6 C13 MDB62
MAB9 A10 DQ27 MDB11 MAB9 A10 DQ27 MDB63
M8 A9 DQ26 D12 M8 A9 DQ26 D12
MAB8 N11 D13 MDB10 MAB8 N11 D13 MDB61
MAB7 A8/AP DQ25 MDB9 MAB7 A8/AP DQ25 MDB60
N10 A7 DQ24 E13 N10 A7 DQ24 E13
MAB6 MDB21 MAB6 MDB32
MAB5
N9
M9
A6 DQ23 K3
K2 MDB23 MAB5
N9
M9
A6 DQ23 K3
K2 MDB35 ALLOW FOOTPRINTS FOR
A5 DQ22 A5 DQ22
D MAB4
MAB3
N8 A4 DQ21 J2 MDB20
MDB22
MAB4
MAB3
N8 A4 DQ21 J2 MDB33
MDB34
DIFFERENTIAL MEMORY CLOCKS D
N7 J3 N7 J3
MAB2 M6
A3 DQ20
G2 MDB17 MAB2 M6
A3 DQ20
G2 MDB37 TERMINATING R/C COMPONENTS
MAB1 A2 DQ19 MDB18 MAB1 A2 DQ19 MDB36
MAB0
N6
N5
A1 DQ18 G3
F2 MDB16 MAB0
N6
N5
A1 DQ18 G3
F2 MDB39 PLACED CLOSE TO THE MEMORIES
A0 DQ17 A0 DQ17
DQ16 F3 MDB19
DQ16 F3 MDB38 INSTALL WITH 56R/470PF AS DEFAULT
F12 MDB0 F12 MDB47
CLKB0_R DQ15 MDB1 CLKB1_R DQ15 MDB43
M11 CLK DQ14 F13 M11 CLK DQ14 F13
G12 MDB4 G12 MDB45
CLKB0#_R DQ13 MDB2 CLKB1#_R DQ13 MDB46 R120 1 CLKB0_R
M12 CLK# DQ12 G13 M12 CLK# DQ12 G13 15 CLKB0 2 10Ohm
J12 MDB5 J12 MDB42
CKEB DQ11 MDB6 CKEB DQ11 MDB41 R121 1 CLKB0#_R
15 CKEB N12 CKE DQ10 J13 N12 CKE DQ10 J13 15 CLKB0# 2 10Ohm
K12 MDB3 K12 MDB44
CSB0# DQ9 MDB7 CSB0# DQ9 MDB40
15 CSB0# N2 CS# DQ8 K13 N2 CS# DQ8 K13

2
E2 MDB29 E2 MDB49
RASB# DQ7 MDB24 RASB# DQ7 MDB51 R126 R125
15 RASB# M2 RAS# DQ6 D2 M2 RAS# DQ6 D2
D3 MDB31 D3 MDB55
CASB# DQ5 MDB26 CASB# DQ5 MDB48 56Ohm 56Ohm
15 CASB# L2 CAS# DQ4 C2 L2 CAS# DQ4 C2
B5 MDB30 B5 MDB54
WEB# DQ3 MDB28 WEB# DQ3 MDB53

1
15 WEB# L3 WE# DQ2 B6 L3 WE# DQ2 B6
C6 MDB27 +ATI_MEM C6 MDB52 +ATI_MEM
DQ1 MDB25 DQ1 MDB50
DQ0 B7 DQ0 B7 PLACED CLOSE TO

1
C100
15 QSB1
QSB1 B13 DQS3 VDDQ1 C3 15 QSB7
QSB7 B13 DQS3 VDDQ1 C3 THE M24-C(U61)
C5 C5 470PF/50V
QSB2 VDDQ2 QSB4 VDDQ2

2
15 QSB2 H2 DQS2 VDDQ3 C7 15 QSB4 H2 DQS2 VDDQ3 C7
VDDQ4 C8 VDDQ4 C8
QSB0 H13 C10 QSB5 H13 C10
15 QSB0 DQS1 VDDQ5 15 QSB5 DQS1 VDDQ5
VDDQ6 C12 VDDQ6 C12
QSB3 B2 E3 QSB6 B2 E3
15 QSB3 DQS0 VDDQ7 15 QSB6 DQS0 VDDQ7
VDDQ8 E12 VDDQ8 E12
F4 F4 R106 1 2 10Ohm CLKB1_R
C DQMB#1 VDDQ9 DQMB#7 VDDQ9 15 CLKB1 C
15 DQMB#1 B12 DM3 VDDQ10 F11 15 DQMB#7 B12 DM3 VDDQ10 F11
G4 G4 R110 1 2 10Ohm CLKB1#_R
DQMB#2 VDDQ11 DQMB#4 VDDQ11 15 CLKB1#
15 DQMB#2 H3 DM2 VDDQ12 G11 15 DQMB#4 H3 DM2 VDDQ12 G11
VDDQ13 J4 VDDQ13 J4

2
DQMB#0 H12 J11 DQMB#5 H12 J11
15 DQMB#0 DM1 VDDQ14 15 DQMB#5 DM1 VDDQ14
K4 +ATI_MEM K4 +ATI_MEM R90 R86
DQMB#3 VDDQ15 DQMB#6 VDDQ15
15 DQMB#3 B3 DM0 VDDQ16 K11 15 DQMB#6 B3 DM0 VDDQ16 K11
56Ohm 56Ohm
+ATI_MEM D7 +ATI_MEM D7
VDD1 VDD1

1
N13 VREF VDD2 D8 N13 VREF VDD2 D8
VDD3 E4 VDD3 E4
1

1
M13 MCL VDD4 E11 M13 MCL VDD4 E11

1
R598 L4 R589 L4 C84
VDD5 VDD5
L9 RFU1 VDD6 L7 L9 RFU1 VDD6 L7
1KOhm L8 1KOhm L8 470PF/50V
VDD7 VDD7

2
M10 RFU2 VDD8 L11 M10 RFU2 VDD8 L11
2

2
C4 NC1 VSSQ1 B4 C4 NC1 VSSQ1 B4
1

1
C11 NC2 VSSQ2 B11 C11 NC2 VSSQ2 B11
1

1
R599 C588 H4 D4 R591 C558 H4 D4
NC3 VSSQ3 NC3 VSSQ3
H11 NC4 VSSQ4 D5 H11 NC4 VSSQ4 D5
1KOhm 0.1UF L12 D6 1KOhm 0.1UF L12 D6
NC5 VSSQ5 NC5 VSSQ5
2

2
L13 NC6 VSSQ6 D9 L13 NC6 VSSQ6 D9
2

M3 NC7 VSSQ7 D10 2 M3 NC7 VSSQ7 D10

M4 D11 M4 D11 +ATI_MEM
NC8 VSSQ8 CSB1# NC8 VSSQ8
15 CSB1# N3 NC9 VSSQ9 E6 N3 NC9 VSSQ9 E6
VSSQ10 E9 VSSQ10 E9
VSSQ11 F5 VSSQ11 F5

1
VSSQ12 F10 VSSQ12 F10
G5 G5 C78 C61 C66 C62 C56 C82 C65 C73 C75 C55
VSSQ13 VSSQ13
VSSQ14 G10 VSSQ14 G10 0.1UF 1UF/6.3V 1000P 0.01UF/16V 22UF/6.3V 0.1UF 1UF/6.3V 1000P 0.01UF/16V 22UF/6.3V

2
VSSQ15 H5 VSSQ15 H5
B F6 H10 F6 H10 B
VSS TH1 VSSQ16 VSS TH1 VSSQ16
F7 VSS TH2 VSSQ17 J5 F7 VSS TH2 VSSQ17 J5
F8 VSS TH3 VSSQ18 J10 F8 VSS TH3 VSSQ18 J10
F9 VSS TH4 VSSQ19 K5 F9 VSS TH4 VSSQ19 K5
G6 VSS TH5 VSSQ20 K10 G6 VSS TH5 VSSQ20 K10
G7 VSS TH6 G7 VSS TH6
G8 E5 G8 E5 +ATI_MEM
VSS TH7 VSS1 VSS TH7 VSS1
G9 VSS TH8 VSS2 E7 G9 VSS TH8 VSS2 E7
H6 VSS TH9 VSS3 E8 H6 VSS TH9 VSS3 E8
H7 VSS TH10 VSS4 E10 H7 VSS TH10 VSS4 E10

1
H8 VSS TH11 VSS5 K6 H8 VSS TH11 VSS5 K6
H9 K7 H9 K7 C113 C112 C107 C102 C95 C108 C111 C109 C99 C98
VSS TH12 VSS6 VSS TH12 VSS6
J6 VSS TH13 VSS7 K8 J6 VSS TH13 VSS7 K8 0.1UF 1UF/6.3V 1000P 0.01UF/16V 22UF/6.3V 0.1UF 1UF/6.3V 1000P 0.01UF/16V 22UF/6.3V

2
J7 VSS TH14 VSS8 K9 J7 VSS TH14 VSS8 K9
J8 VSS TH15 VSS9 L5 J8 VSS TH15 VSS9 L5
J9 VSS TH16 VSS10 L10 J9 VSS TH16 VSS10 L10

HY5DS573222F_33 HY5DS573222F_33

A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan 61
M24-C - DDR MEMORY B LIBRARY DATE :
2.0 SHEET 19 OF
5 4 3 2 1
5 4 3 2 1

U56
U22 SM_B_MA0 R8 K8 SM_B_DQ6
SM_B_MA0 SM_B_DQ49 SM_B_MA1 A0 DQ0 SM_B_DQ4 +1.8V
R8 A0 DQ0 K8 R3 A1 DQ1 K2
SM_B_MA1 R3 K2 SM_B_DQ48 SM_B_MA2 R7 L7 SM_B_DQ1
SM_B_MA2 A1 DQ1 SM_B_DQ51 SM_B_MA3 A2 DQ2 SM_B_DQ5
R7 A2 DQ2 L7 T2 A3 DQ3 L3
SM_B_MA3 T2 L3 SM_B_DQ55 SM_B_MA4 T8 L1 SM_B_DQ3
A3 DQ3 A4 DQ4

1
SM_B_MA4 T8 L1 SM_B_DQ54 SM_B_MA5 T3 L9 SM_B_DQ7 C296 C300 C276 C299 C298
SM_B_MA5 A4 DQ4 SM_B_DQ50 SM_B_MA6 A5 DQ5 SM_B_DQ0
T3 A5 DQ5 L9 T7 A6 DQ6 J1
SM_B_MA6 T7 J1 SM_B_DQ52 SM_B_MA7 U2 J9 SM_B_DQ2
SM_B_MA7 A6 DQ6 SM_B_DQ53 SM_B_MA8 A7 DQ7 SM_B_DQ13 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V

2
U2 A7 DQ7 J9 U8 A8 DQ8 F8
SM_B_MA8 U8 F8 SM_B_DQ42 SM_B_MA9 U3 F2 SM_B_DQ14
SM_B_MA9 A8 DQ8 SM_B_DQ44 SM_B_MA10 A9 DQ9 SM_B_DQ8
U3 A9 DQ9 F2 R2 A10 DQ10 G7
D SM_B_MA10 R2 G7 SM_B_DQ43 SM_B_MA11 U7 G3 SM_B_DQ9 D
SM_B_MA11 A10 DQ10 SM_B_DQ41 SM_B_MA12 A11 DQ11 SM_B_DQ10
U7 A11 DQ11 G3 V2 A12 DQ12 G1
SM_B_MA12 SM_B_DQ45 SM_B_MA13 SM_B_DQ11
SM_B_MA13
V2 A12 DQ12 G1
SM_B_DQ47
V8 NC/A13 DQ13 G9
SM_B_DQ15
Layout Note: Place these Caps near Memory Module
V8 NC/A13 DQ13 G9 V3 RFU/A14 DQ14 E1
V3 E1 SM_B_DQ40 V7 E9 SM_B_DQ12
RFU/A14 DQ14 SM_B_DQ46 RFU/A15 DQ15
V7 RFU/A15 DQ15 E9
SM_B_BS#0 P2 D3
SM_B_BS#0 SM_B_BS#1 BA0 VSS0 +1.8V
10,21,23 SM_B_BS#0 P2 BA0 VSS0 D3 P3 BA1 VSS1 H3
SM_B_BS#1 P3 H3 SM_B_BS#2 P1 M3
10,21,23 SM_B_BS#1 SM_B_BS#2 BA1 VSS1 RFU/BA2 VSS2
10,21,23 SM_B_BS#2 P1 RFU/BA2 VSS2 M3 VSS3 T1
T1 CLK_DCLK3 M8 U9
CLK_DCLK4 VSS3 9,21 CLK_DCLK3 CLK_DCLK3# CK VSS4
9,21 CLK_DCLK4 M8 CK VSS4 U9 9,21 CLK_DCLK3# N8 CK#

1
CLK_DCLK4# N8 SM_CKE2 N2 D7
9,21 CLK_DCLK4# SM_CKE2 CK# CKE VSSQ0 C776 C781 C775 C779
N2 CKE VSSQ0 D7 VSSQ1 E2
9,23 SM_CKE2 +1.8V 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V
VSSQ1 E2 VSSQ2 E8
+1.8V

2
VSSQ2 E8 D1 VDD0 VSSQ3 G2
D1 VDD0 VSSQ3 G2 H1 VDD1 VSSQ4 G8
H1 VDD1 VSSQ4 G8 M9 VDD2 VSSQ5 H7
M9 VDD2 VSSQ5 H7 R9 VDD3 VSSQ6 J2
R9 VDD3 VSSQ6 J2 V1 VDD4 VSSQ7 J8
V1 VDD4 VSSQ7 J8 VSSQ8 L2
L2 D9 L8 +1.8V
VSSQ8 +1.8V VDDQ0 VSSQ9
D9 VDDQ0 VSSQ9 L8 F1 VDDQ1
F1 VDDQ1 F3 VDDQ2 VDDL M1
F3 VDDQ2 VDDL M1 F7 VDDQ3 VSSDL M7
F7 VDDQ3 VSSDL M7 F9 VDDQ4
F9 VDDQ4 H9 VDDQ5 NC0 A1
H9 VDDQ5 NC0 A1 K1 VDDQ6 NC1 A2
K1 A2 K3 A8 SM_B_MA[0:13]
VDDQ6 NC1 VDDQ7 NC2 SM_B_MA[0:13] 10,21,23
K3 VDDQ7 NC2 A8 K7 VDDQ8 NC3 A9
K7 VDDQ8 NC3 A9 K9 VDDQ9 NC4 AA1
K9 AA1 AA2 SM_B_DQ[0:63]
C VDDQ9 NC4 SM_ODT2 NC5 SM_B_DQ[0:63] 10,21 C
NC5 AA2 N9 ODT NC6 AA8
SM_ODT2 N9 AA8 SM_VREF_DDR M2 AA9
9,23 SM_ODT2 SM_VREF_DDR M2 ODT NC6 VREF NC7 SM_B_DM[0:7]
9,21,22 SM_VREF_DDR VREF NC7 AA9 NC8 D2 SM_B_DM[0:7] 10,21
D2 SM_B_DM0 J3 H2
SM_B_DM6 NC8 SM_B_DM1 LDM NC9
J3 LDM NC9 H2 E3 UDM
SM_B_DM5 E3 SM_B_DQS0 J7 N3 SM_B_WE# SM_B_DQS[0:7]
SM_B_DQS6 UDM SM_B_WE# SM_B_DQS1 LDQS WE# SM_B_RAS# SM_B_DQS[0:7] 10,21
J7 LDQS WE# N3 SM_B_WE# 10,21,23 E7 UDQS RAS# N7
SM_B_DQS5 E7 N7 SM_B_RAS# SM_B_DQS#0 H8 P8 SM_CS2#
SM_B_DQS#6 UDQS RAS# SM_CS2# SM_B_RAS# 10,21,23 SM_B_DQS#1 LDQS#/NU CS# SM_B_CAS# SM_B_DQS#[0:7]
H8 LDQS#/NU CS# P8 SM_CS2# 9,23 D8 UDQS#/NU CAS# P7 SM_B_DQS#[0:7] 10,21
SM_B_DQS#5 D8 P7 SM_B_CAS#
UDQS#/NU CAS# SM_B_CAS# 10,21,23
BGA_92P
BGA_92P SM_B_BS#[0:2]
SM_B_BS#[0:2] 10,21,23

U57 U21
SM_B_MA0 R8 K8 SM_B_DQ19 SM_B_MA0 R8 K8 SM_B_DQ32
SM_B_MA1 A0 DQ0 SM_B_DQ20 SM_B_MA1 A0 DQ0 SM_B_DQ36
R3 A1 DQ1 K2 R3 A1 DQ1 K2
SM_B_MA2 R7 L7 SM_B_DQ16 SM_B_MA2 R7 L7 SM_B_DQ39
SM_B_MA3 A2 DQ2 SM_B_DQ17 SM_B_MA3 A2 DQ2 SM_B_DQ35
T2 A3 DQ3 L3 T2 A3 DQ3 L3
SM_B_MA4 T8 L1 SM_B_DQ18 SM_B_MA4 T8 L1 SM_B_DQ37 CLK_DCLK4
SM_B_MA5 A4 DQ4 SM_B_DQ21 SM_B_MA5 A4 DQ4 SM_B_DQ38
T3 A5 DQ5 L9 T3 A5 DQ5 L9
SM_B_MA6 T7 J1 SM_B_DQ22 SM_B_MA6 T7 J1 SM_B_DQ34
A6 DQ6 A6 DQ6

1
SM_B_MA7 U2 J9 SM_B_DQ23 SM_B_MA7 U2 J9 SM_B_DQ33
SM_B_MA8 A7 DQ7 SM_B_DQ28 SM_B_MA8 A7 DQ7 SM_B_DQ62 R363
U8 A8 DQ8 F8 U8 A8 DQ8 F8
SM_B_MA9 U3 F2 SM_B_DQ27 SM_B_MA9 U3 F2 SM_B_DQ63
SM_B_MA10 A9 DQ9 SM_B_DQ29 SM_B_MA10 A9 DQ9 SM_B_DQ56 100Ohm
R2 A10 DQ10 G7 R2 A10 DQ10 G7
SM_B_MA11 U7 G3 SM_B_DQ30 SM_B_MA11 U7 G3 SM_B_DQ58
SM_B_MA12 A11 DQ11 SM_B_DQ31 SM_B_MA12 A11 DQ11 SM_B_DQ59

2
V2 A12 DQ12 G1 V2 A12 DQ12 G1
SM_B_MA13 V8 G9 SM_B_DQ25 SM_B_MA13 V8 G9 SM_B_DQ61 CLK_DCLK4# PLACE NEAR SO-DIMM
NC/A13 DQ13 SM_B_DQ26 NC/A13 DQ13 SM_B_DQ57
V3 RFU/A14 DQ14 E1 V3 RFU/A14 DQ14 E1
V7 E9 SM_B_DQ24 V7 E9 SM_B_DQ60
RFU/A15 DQ15 RFU/A15 DQ15 CLK_DCLK3
B SM_B_BS#0 P2 D3 SM_B_BS#0 P2 D3 B
BA0 VSS0 BA0 VSS0

1
SM_B_BS#1 P3 H3 SM_B_BS#1 P3 H3
SM_B_BS#2 BA1 VSS1 SM_B_BS#2 BA1 VSS1 R362
P1 RFU/BA2 VSS2 M3 P1 RFU/BA2 VSS2 M3
T1 T1 PLACE NEAR SO-DIMM
CLK_DCLK3 VSS3 CLK_DCLK4 VSS3 100Ohm
M8 CK VSS4 U9 M8 CK VSS4 U9
CLK_DCLK3# N8 CLK_DCLK4# N8
SM_CKE2 CK# SM_CKE2 CK# CLK_DCLK3#

2
N2 CKE VSSQ0 D7 N2 CKE VSSQ0 D7
VSSQ1 E2 VSSQ1 E2
+1.8V E8 +1.8V E8
VSSQ2 VSSQ2
D1 VDD0 VSSQ3 G2 D1 VDD0 VSSQ3 G2
H1 VDD1 VSSQ4 G8 H1 VDD1 VSSQ4 G8
M9 VDD2 VSSQ5 H7 M9 VDD2 VSSQ5 H7
R9 VDD3 VSSQ6 J2 R9 VDD3 VSSQ6 J2
V1 VDD4 VSSQ7 J8 V1 VDD4 VSSQ7 J8
L2 L2 SM_VREF_DDR
VSSQ8 +1.8V VSSQ8 +1.8V
D9 VDDQ0 VSSQ9 L8 D9 VDDQ0 VSSQ9 L8
F1 VDDQ1 F1 VDDQ1
F3 VDDQ2 VDDL M1 F3 VDDQ2 VDDL M1
F7 VDDQ3 VSSDL M7 F7 VDDQ3 VSSDL M7

1
F9 F9 C331 C321 C302 C303
VDDQ4 VDDQ4
H9 VDDQ5 NC0 A1 H9 VDDQ5 NC0 A1
K1 A2 K1 A2 2.2UF/6.3V 2.2UF/6.3V 0.1uF/10V 0.1uF/10V
VDDQ6 NC1 VDDQ6 NC1

2
K3 VDDQ7 NC2 A8 K3 VDDQ7 NC2 A8
K7 VDDQ8 NC3 A9 K7 VDDQ8 NC3 A9
K9 VDDQ9 NC4 AA1 K9 VDDQ9 NC4 AA1
NC5 AA2 NC5 AA2
SM_ODT2 N9 AA8 SM_ODT2 N9 AA8
SM_VREF_DDR M2 ODT NC6 SM_VREF_DDR M2 ODT NC6
VREF NC7 AA9 VREF NC7 AA9
NC8 D2 NC8 D2
SM_B_DM2 J3 H2 SM_B_DM4 J3 H2
SM_B_DM3 LDM NC9 SM_B_DM7 LDM NC9
E3 E3
A
SM_B_DQS2
SM_B_DQS3
J7
UDM
LDQS WE# N3 SM_B_WE#
SM_B_RAS#
SM_B_DQS4
SM_B_DQS7
J7
UDM
LDQS WE# N3 SM_B_WE#
SM_B_RAS#
DDRII 533HMz 512MB A
E7 N7 E7 N7
SM_B_DQS#2
SM_B_DQS#3
H8
UDQS
LDQS#/NU
RAS#
CS# P8 SM_CS2#
SM_B_CAS#
SM_B_DQS#4
SM_B_DQS#7
H8
UDQS
LDQS#/NU
RAS#
CS# P8 SM_CS2#
SM_B_CAS#
Nanya 03-15133E110HQ
D8 P7 D8 P7
UDQS#/NU CAS# UDQS#/NU CAS# Infineon 03-15073B011HQ
BGA_92P BGA_92P

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan DDR2 (1) LIBRARY DATE :
2.0 SHEET 20 OF 61

WWW.AliSaler.Com 5 4 3 2 1
5 4 3 2 1

U19
U59 SM_B_MA0 R8 K8 SM_B_DQ4
SM_B_MA0 SM_B_DQ48 SM_B_MA1 A0 DQ0 SM_B_DQ6 +1.8V
R8 A0 DQ0 K8 R3 A1 DQ1 K2
SM_B_MA1 R3 K2 SM_B_DQ49 SM_B_MA2 R7 L7 SM_B_DQ5
SM_B_MA2 A1 DQ1 SM_B_DQ55 SM_B_MA3 A2 DQ2 SM_B_DQ1
R7 A2 DQ2 L7 T2 A3 DQ3 L3
SM_B_MA3 T2 L3 SM_B_DQ51 SM_B_MA4 T8 L1 SM_B_DQ7
A3 DQ3 A4 DQ4

1
SM_B_MA4 T8 L1 SM_B_DQ50 SM_B_MA5 T3 L9 SM_B_DQ3 C320 C343 C336 C311 C307
SM_B_MA5 A4 DQ4 SM_B_DQ54 SM_B_MA6 A5 DQ5 SM_B_DQ2
T3 A5 DQ5 L9 T7 A6 DQ6 J1
SM_B_MA6 T7 J1 SM_B_DQ53 SM_B_MA7 U2 J9 SM_B_DQ0
SM_B_MA7 A6 DQ6 SM_B_DQ52 SM_B_MA8 A7 DQ7 SM_B_DQ14 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V 2.2UF/6.3V

2
U2 A7 DQ7 J9 U8 A8 DQ8 F8
SM_B_MA8 U8 F8 SM_B_DQ44 SM_B_MA9 U3 F2 SM_B_DQ13
SM_B_MA9 A8 DQ8 SM_B_DQ42 SM_B_MA10 A9 DQ9 SM_B_DQ9
U3 A9 DQ9 F2 R2 A10 DQ10 G7
D SM_B_MA10 R2 G7 SM_B_DQ41 SM_B_MA11 U7 G3 SM_B_DQ8 D
SM_B_MA11 A10 DQ10 SM_B_DQ43 SM_B_MA12 A11 DQ11 SM_B_DQ11
U7 A11 DQ11 G3 V2 A12 DQ12 G1
SM_B_MA12 SM_B_DQ47 SM_B_MA13 SM_B_DQ10
SM_B_MA13
V2 A12 DQ12 G1
SM_B_DQ45
V8 NC/A13 DQ13 G9
SM_B_DQ12
Layout Note: Place these Caps near Memory Module
V8 NC/A13 DQ13 G9 V3 RFU/A14 DQ14 E1
V3 E1 SM_B_DQ46 V7 E9 SM_B_DQ15
RFU/A14 DQ14 SM_B_DQ40 RFU/A15 DQ15
V7 RFU/A15 DQ15 E9
SM_B_BS#0 P2 D3
SM_B_BS#0 SM_B_BS#1 BA0 VSS0 +1.8V
10,20,23 SM_B_BS#0 P2 BA0 VSS0 D3 P3 BA1 VSS1 H3
SM_B_BS#1 P3 H3 SM_B_BS#2 P1 M3
10,20,23 SM_B_BS#1 SM_B_BS#2 BA1 VSS1 RFU/BA2 VSS2
10,20,23 SM_B_BS#2 P1 RFU/BA2 VSS2 M3 VSS3 T1
T1 CLK_DCLK3 M8 U9
CLK_DCLK4 VSS3 9,20 CLK_DCLK3 CLK_DCLK3# CK VSS4
9,20 CLK_DCLK4 M8 CK VSS4 U9 9,20 CLK_DCLK3# N8 CK#

1
CLK_DCLK4# N8 SM_CKE3 N2 D7
9,20 CLK_DCLK4# SM_CKE3 CK# CKE VSSQ0 C339 C308 C306 C341
N2 CKE VSSQ0 D7 VSSQ1 E2
9,23 SM_CKE3 +1.8V 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V
VSSQ1 E2 VSSQ2 E8
+1.8V

2
VSSQ2 E8 D1 VDD0 VSSQ3 G2
D1 VDD0 VSSQ3 G2 H1 VDD1 VSSQ4 G8
H1 VDD1 VSSQ4 G8 M9 VDD2 VSSQ5 H7
M9 VDD2 VSSQ5 H7 R9 VDD3 VSSQ6 J2
R9 VDD3 VSSQ6 J2 V1 VDD4 VSSQ7 J8
V1 VDD4 VSSQ7 J8 VSSQ8 L2
L2 D9 L8 +1.8V
VSSQ8 +1.8V VDDQ0 VSSQ9
D9 VDDQ0 VSSQ9 L8 F1 VDDQ1
F1 VDDQ1 F3 VDDQ2 VDDL M1
F3 VDDQ2 VDDL M1 F7 VDDQ3 VSSDL M7
F7 VDDQ3 VSSDL M7 F9 VDDQ4
F9 VDDQ4 H9 VDDQ5 NC0 A1
H9 VDDQ5 NC0 A1 K1 VDDQ6 NC1 A2
K1 A2 K3 A8 SM_B_MA[0:13]
VDDQ6 NC1 VDDQ7 NC2 SM_B_MA[0:13] 10,20,23
K3 VDDQ7 NC2 A8 K7 VDDQ8 NC3 A9
K7 VDDQ8 NC3 A9 K9 VDDQ9 NC4 AA1
K9 AA1 AA2 SM_B_DQ[0:63]
C VDDQ9 NC4 SM_ODT3 NC5 SM_B_DQ[0:63] 10,20 C
NC5 AA2 N9 ODT NC6 AA8
SM_ODT3 N9 AA8 SM_VREF_DDR M2 AA9
9,23 SM_ODT3 SM_VREF_DDR M2 ODT NC6 VREF NC7 SM_B_DM[0:7]
9,20,22 SM_VREF_DDR VREF NC7 AA9 NC8 D2 SM_B_DM[0:7] 10,20
D2 SM_B_DM0 J3 H2
SM_B_DM6 NC8 SM_B_DM1 LDM NC9
J3 LDM NC9 H2 E3 UDM
SM_B_DM5 E3 SM_B_DQS0 J7 N3 SM_B_WE# SM_B_DQS[0:7]
SM_B_DQS6 UDM SM_B_WE# SM_B_DQS1 LDQS WE# SM_B_RAS# SM_B_DQS[0:7] 10,20
J7 LDQS WE# N3 SM_B_WE# 10,20,23 E7 UDQS RAS# N7
SM_B_DQS5 E7 N7 SM_B_RAS# SM_B_DQS#0 H8 P8 SM_CS3#
SM_B_DQS#6 UDQS RAS# SM_CS3# SM_B_RAS# 10,20,23 SM_B_DQS#1 LDQS#/NU CS# SM_B_CAS# SM_B_DQS#[0:7]
H8 LDQS#/NU CS# P8 SM_CS3# 9,23 D8 UDQS#/NU CAS# P7 SM_B_DQS#[0:7] 10,20
SM_B_DQS#5 D8 P7 SM_B_CAS#
UDQS#/NU CAS# SM_B_CAS# 10,20,23 SM_B_BS#[0:2]
BGA_92P
SM_B_BS#[0:2] 10,20,23
BGA_92P

U20 U58
SM_B_MA0 R8 K8 SM_B_DQ20 SM_B_MA0 R8 K8 SM_B_DQ36
SM_B_MA1 A0 DQ0 SM_B_DQ19 SM_B_MA1 A0 DQ0 SM_B_DQ32
R3 A1 DQ1 K2 R3 A1 DQ1 K2
SM_B_MA2 R7 L7 SM_B_DQ17 SM_B_MA2 R7 L7 SM_B_DQ35
SM_B_MA3 A2 DQ2 SM_B_DQ16 SM_B_MA3 A2 DQ2 SM_B_DQ39
T2 A3 DQ3 L3 T2 A3 DQ3 L3
SM_B_MA4 T8 L1 SM_B_DQ21 SM_B_MA4 T8 L1 SM_B_DQ38
SM_B_MA5 A4 DQ4 SM_B_DQ18 SM_B_MA5 A4 DQ4 SM_B_DQ37 CLK_DCLK4
T3 A5 DQ5 L9 T3 A5 DQ5 L9
SM_B_MA6 T7 J1 SM_B_DQ23 SM_B_MA6 T7 J1 SM_B_DQ33
SM_B_MA7 A6 DQ6 SM_B_DQ22 SM_B_MA7 A6 DQ6 SM_B_DQ34 PLACE NEAR SO-DIMM
U2 A7 DQ7 J9 U2 A7 DQ7 J9

1
SM_B_MA8 U8 F8 SM_B_DQ27 SM_B_MA8 U8 F8 SM_B_DQ63
SM_B_MA9 A8 DQ8 SM_B_DQ28 SM_B_MA9 A8 DQ8 SM_B_DQ62 C769
U3 A9 DQ9 F2 U3 A9 DQ9 F2
SM_B_MA10 R2 G7 SM_B_DQ30 SM_B_MA10 R2 G7 SM_B_DQ58 5PF
SM_B_MA11 A10 DQ10 SM_B_DQ29 SM_B_MA11 A10 DQ10 SM_B_DQ56

2
U7 A11 DQ11 G3 U7 A11 DQ11 G3
SM_B_MA12 V2 G1 SM_B_DQ25 SM_B_MA12 V2 G1 SM_B_DQ61 CLK_DCLK4#
SM_B_MA13 A12 DQ12 SM_B_DQ31 SM_B_MA13 A12 DQ12 SM_B_DQ59
V8 NC/A13 DQ13 G9 V8 NC/A13 DQ13 G9
V3 E1 SM_B_DQ24 V3 E1 SM_B_DQ60
RFU/A14 DQ14 SM_B_DQ26 RFU/A14 DQ14 SM_B_DQ57
V7 RFU/A15 DQ15 E9 V7 RFU/A15 DQ15 E9
CLK_DCLK3
B SM_B_BS#0 P2 D3 SM_B_BS#0 P2 D3 B
SM_B_BS#1 BA0 VSS0 SM_B_BS#1 BA0 VSS0 PLACE NEAR SO-DIMM
P3 BA1 VSS1 H3 P3 BA1 VSS1 H3

1
SM_B_BS#2 P1 M3 SM_B_BS#2 P1 M3
RFU/BA2 VSS2 RFU/BA2 VSS2 C768
VSS3 T1 VSS3 T1
CLK_DCLK3 M8 U9 CLK_DCLK4 M8 U9 5PF
CLK_DCLK3# CK VSS4 CLK_DCLK4# CK VSS4

2
N8 CK# N8 CK#
SM_CKE3 N2 D7 SM_CKE3 N2 D7 CLK_DCLK3#
CKE VSSQ0 CKE VSSQ0
VSSQ1 E2 VSSQ1 E2
+1.8V E8 +1.8V E8
VSSQ2 VSSQ2
D1 VDD0 VSSQ3 G2 D1 VDD0 VSSQ3 G2
H1 VDD1 VSSQ4 G8 H1 VDD1 VSSQ4 G8
M9 VDD2 VSSQ5 H7 M9 VDD2 VSSQ5 H7
R9 VDD3 VSSQ6 J2 R9 VDD3 VSSQ6 J2
V1 VDD4 VSSQ7 J8 V1 VDD4 VSSQ7 J8
L2 L2 SM_VREF_DDR
VSSQ8 +1.8V VSSQ8 +1.8V
D9 VDDQ0 VSSQ9 L8 D9 VDDQ0 VSSQ9 L8
F1 VDDQ1 F1 VDDQ1
F3 VDDQ2 VDDL M1 F3 VDDQ2 VDDL M1
F7 VDDQ3 VSSDL M7 F7 VDDQ3 VSSDL M7

1
F9 VDDQ4 F9 VDDQ4
H9 A1 H9 A1 C318 C326 C305 C312
VDDQ5 NC0 VDDQ5 NC0 2.2UF/6.3V 2.2UF/6.3V 0.1uF/10V 0.1uF/10V
K1 VDDQ6 NC1 A2 K1 VDDQ6 NC1 A2

2
K3 VDDQ7 NC2 A8 K3 VDDQ7 NC2 A8
K7 VDDQ8 NC3 A9 K7 VDDQ8 NC3 A9
K9 VDDQ9 NC4 AA1 K9 VDDQ9 NC4 AA1
NC5 AA2 NC5 AA2
SM_ODT3 N9 AA8 SM_ODT3 N9 AA8
SM_VREF_DDR M2 ODT NC6 SM_VREF_DDR M2 ODT NC6
VREF NC7 AA9 VREF NC7 AA9
NC8 D2 NC8 D2
SM_B_DM2 J3 H2 SM_B_DM4 J3 H2
SM_B_DM3 LDM NC9 SM_B_DM7 LDM NC9
E3 UDM E3 UDM
SM_B_DQS2 J7 N3 SM_B_WE# SM_B_DQS4 J7 N3 SM_B_WE#
A SM_B_DQS3 LDQS WE# SM_B_RAS# SM_B_DQS7 LDQS WE# SM_B_RAS# A
E7 UDQS RAS# N7 E7 UDQS RAS# N7
SM_B_DQS#2 H8 P8 SM_CS3# SM_B_DQS#4 H8 P8 SM_CS3#
SM_B_DQS#3 LDQS#/NU CS# SM_B_CAS# SM_B_DQS#7 LDQS#/NU CS# SM_B_CAS#
D8 UDQS#/NU CAS# P7 D8 UDQS#/NU CAS# P7

BGA_92P BGA_92P

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan DDR2 (2) LIBRARY DATE :
2.0 SHEET 21 OF 61
5 4 3 2 1
5 4 3 2 1

SM_A_DQ[63:0] 10

SM_A_MA[13:0] 10,23

SM_A_DM[7:0] 10
D D
SM_A_DQS[0:7]
SM_A_DQS[0:7] 10
SM_A_DQS#[0:7]
SM_A_DQS#[0:7] 10

+1.8V
NO STUFF
*
10,23 SM_A_MA[0:13] SM_A_DQ[0:63] 10
+3VS
CN28A
CLK_DCLK0 SM_A_MA0 102 5 SM_A_DQ0
SM_A_MA1 A0 DQ0 SM_A_DQ5 CN28B
101 A1 DQ1 7
C723 SM_A_MA2 100 17 SM_A_DQ2 112 18
A2 DQ2 VDD1 VSS16
2

SM_A_MA3 99 19 SM_A_DQ7 111 24

PLACE NEAR SO-DIMM_1 SM_A_MA4 A3 DQ3 SM_A_DQ4 VDD2 VSS17
98 A4 DQ4 4 117 VDD3 VSS18 41

1
10P @ SM_A_MA5 97 6 SM_A_DQ1 C700 C699 96 53
SM_A_MA6 A5 DQ5 SM_A_DQ6 VDD4 VSS19
1

94 A6 DQ6 14 95 VDD5 VSS20 42

CLK_DCLK0# SM_A_MA7 92 16 SM_A_DQ3 0.1UF 0.1UF 118 54
SM_A_MA8 A7 DQ7 SM_A_DQ13 VDD6 VSS21

2
93 A8 DQ8 23 81 VDD7 VSS22 59
SM_A_MA9 91 25 SM_A_DQ12 82 65
SM_A_MA10 A9 DQ9 SM_A_DQ10 VDD8 VSS23
105 A10/AP DQ10 35 87 VDD9 VSS24 60
CLK_DCLK1 SM_A_MA11 90 37 SM_A_DQ11 103 66
SM_A_MA12 A11 DQ11 SM_A_DQ8 VDD10 VSS25
89 A12 DQ12 20 88 VDD11 VSS26 127
C724 SM_A_MA13 116 22 SM_A_DQ9 104 139
A13 DQ13 VDD12 VSS27
2

86 36 SM_A_DQ14 128
PLACE NEAR SO-DIMM_1 A14 DQ14 SM_A_DQ15 VSS28
84 A15 DQ15 38 199 VDDSPD VSS29 145
10P @ 85 43 SM_A_DQ16 165
10,23 SM_A_BS#2 A16_BA2 DQ16 SM_A_DQ20 VSS30
1

DQ17 45 83 NC1 VSS31 171

CLK_DCLK1# 107 55 SM_A_DQ22 120 172
10,23 SM_A_BS#0 BA0 DQ18 SM_A_DQ23 NC2 VSS32
10,23 SM_A_BS#1 106 BA1 DQ19 57 50 NC3 VSS33 177
C SM_A_DQ17 M_VREF_DIMM1 C
9,23 SM_CS0# 110 S0# DQ20 44 69 NC4 VSS34 187
115 46 SM_A_DQ21 163 178
9,23 SM_CS1# S1# DQ21 SM_A_DQ18 NCTEST VSS35
9 CLK_DCLK0 30 CK0 DQ22 56 VSS36 190
32 58 SM_A_DQ19 1 9
9 CLK_DCLK0# CK0# DQ23 SM_A_DQ24 9,20,21 SM_VREF_DDR VREF VSS37
9 CLK_DCLK1 164 CK1 DQ24 61 VSS38 21
166 63 SM_A_DQ25 201 33
9 CLK_DCLK1# CK1# DQ25 GND0 VSS39

1
79 73 SM_A_DQ27 C657 C643 202 155
9,23 SM_CKE0 CKE0 DQ26 SM_A_DQ31 GND1 VSS40
9,23 SM_CKE1 80 CKE1 DQ27 75 VSS41 34
113 62 SM_A_DQ29 2.2uF/6.3V 0.1UF 203 132
10,23 SM_A_CAS# CAS# DQ28 SM_A_DQ28 NP_NC1 VSS42

2
10,23 SM_A_RAS# 108 RAS# DQ29 64 204 NP_NC2 VSS43 144
109 74 SM_A_DQ26 156
10,23 SM_A_WE# WE# DQ30 SM_A_DQ30 VSS44
198 SA0 DQ31 76 47 VSS1 VSS45 168
200 123 SM_A_DQ32 133 2
SA1 DQ32 SM_A_DQ33 VSS2 VSS46
6,7,42 SMBCK_3S 197 SCL DQ33 125 183 VSS3 VSS47 3
1

195 135 SM_A_DQ39 77 15

6,7,42 SMBDA_3S SDA DQ34 SM_A_DQ34 VSS4 VSS48
R328 R329 137 12 27
DQ35 SM_A_DQ36 VSS5 VSS49
9,23 SM_ODT0 114 ODT0 DQ36 124 48 VSS6 VSS50 39
10KOhm 10KOhm 119 126 SM_A_DQ37 184 149
9,23 SM_ODT1 ODT1 DQ37 SM_A_DQ38 VSS7 VSS51
10 SM_A_DM[0..7] DQ38 134 78 VSS8 VSS52 161
SM_A_DM0 SM_A_DQ35
2

10 DM0 DQ39 136 71 VSS9 VSS53 28

SM_A_DM1 26 141 SM_A_DQ45 72 40
SM_A_DM2 DM1 DQ40 SM_A_DQ40 VSS10 VSS54
52 DM2 DQ41 143 121 VSS11 VSS55 138
SM_A_DM3 SM_A_DQ47
SM_A_DM4
67 DM3 DQ42 151
SM_A_DQ46
Layout Note: Place these Caps near SO DIMM 1 122 VSS12 VSS56 150
130 DM4 DQ43 153 196 VSS13 VSS57 162
SM_A_DM5 147 140 SM_A_DQ44 193
SM_A_DM6 DM5 DQ44 SM_A_DQ41 +1.8V VSS14
170 DM6 DQ45 142 8 VSS15
SM_A_DM7 185 152 SM_A_DQ43
DM7 DQ46 SM_A_DQ42
10 SM_A_DQS[0..7] DQ47 154
SM_A_DQS0 13 157 SM_A_DQ49 DDR_DIMM_200P
DQS0 DQ48

1
SM_A_DQS1 31 159 SM_A_DQ48 C286 C285 C284 C283
SM_A_DQS2 DQS1 DQ49 SM_A_DQ55
51 DQS2 DQ50 173
SM_A_DQS3 70 175 SM_A_DQ54 0.1UF 0.1UF 0.1UF 0.1UF
B SM_A_DQS4 DQS3 DQ51 SM_A_DQ52 B

2
131 DQS4 DQ52 158
SM_A_DQS5 148 160 SM_A_DQ53
SM_A_DQS6 DQS5 DQ53 SM_A_DQ50
169 DQS6 DQ54 174
SM_A_DQS7 188 176 SM_A_DQ51
10 SM_A_DQS#[0..7] SM_A_DQS#0 DQS7 DQ55 SM_A_DQ56
11 DQS#0 DQ56 179
SM_A_DQS#1 29 181 SM_A_DQ60
SM_A_DQS#2 DQS#1 DQ57 SM_A_DQ63
49 DQS#2 DQ58 189
SM_A_DQS#3 68 191 SM_A_DQ62
SM_A_DQS#4 DQS#3 DQ59 SM_A_DQ61
129 DQS#4 DQ60 180
SM_A_DQS#5 SM_A_DQ57
SM_A_DQS#6
146 DQS#5 DQ61 182
SM_A_DQ58
Layout Note: Place these Caps near SO DIMM 1
167 DQS#6 DQ62 192
SM_A_DQS#7 186 194 SM_A_DQ59
DQS#7 DQ63
+1.8V
DDR_DIMM_200P

1
C278 C277 C279 C275 C274

2.2uF/6.3V 2.2uF/6.3V 2.2uF/6.3V 2.2uF/6.3V 2.2uF/6.3V

2
A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan STANDARD DDR2 SO-DIMM LIBRARY DATE :
2.0 SHEET 22 OF 61

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5 4 3 2 1

+0.9VS

R678 1 2 56Ohm SM_CKE0

R724 1 2 56Ohm SM_CKE1
R722 1 2 56Ohm SM_CKE2
R723 1 2 56Ohm SM_CKE3
D D

SM_A_MA[0..13] 10,22 SM_ODT0

R720 1 2 56Ohm
R684 1 2 56Ohm SM_ODT1
R686 1 2 56Ohm SM_ODT2
SM_A_BS#[0..2] 10,22 SM_ODT3
R687 1 2 56Ohm

SM_B_MA[0..13] 10,20,21
R680 1 2 56Ohm SM_A_BS#0
R717 1 2 56Ohm SM_A_BS#1
R679 1 2 56Ohm SM_A_BS#2
SM_B_BS#[0..2] 10,20,21

SM_CKE[0:3] 9,20,21,22
R682 1 2 56Ohm SM_A_CAS# 10,22
R718 1 2 56Ohm SM_A_RAS# 10,22
R681 1 2 56Ohm
SM_ODT[0:3] 9,20,21,22 SM_A_WE# 10,22

R671 1 2 56Ohm SM_B_BS#0

R670 1 2 56Ohm SM_B_BS#1
R672 1 2 56Ohm SM_B_BS#2

R669 1 2 56Ohm SM_B_CAS# 10,20,21

R668 1 2 56Ohm SM_B_RAS# 10,20,21
R667 1 2 56Ohm SM_B_WE# 10,20,21

+0.9VS R719 1 2 56Ohm SM_CS0#

C SM_CS1# SM_CS0# 9,22 C
R683 1 2 56Ohm
SM_CS2# SM_CS1# 9,22
R685 1 2 56Ohm
SM_CS3# SM_CS2# 9,20
R688 1 2 56Ohm
SM_CS3# 9,21
1

1
C739 C725 C726 C727 C728 C729 C737 C730 C731 C736 C691 C693 C692
1 16 RN17A SM_A_MA0
56Ohm SM_A_MA1
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 2 15 RN17B
56Ohm SM_A_MA2
RN17C
2

2
3 56Ohm 14
4 13 RN17D SM_A_MA3
56Ohm SM_A_MA4
5 12 RN17E
56Ohm SM_A_MA5
6 11 RN17F
56Ohm SM_A_MA6
7 10 RN17G
56Ohm SM_A_MA7
8 9 RN17H
56Ohm

Layout note: Place one cap close to every 2 pullup resistors terminated to +0.9VS 1 16 RN16A SM_A_MA12
56Ohm SM_A_MA9
2 15 RN16B
+0.9VS 56Ohm SM_A_MA8
3 14 RN16C
56Ohm SM_A_MA11
4 13 RN16D
56Ohm SM_A_MA10
5 12 RN16E
56Ohm
6 11 RN16F
56Ohm
7 10 RN16G
56Ohm
8 9 RN16H
56Ohm
1

1
C735 C734 C733 C732 C685 C683 C684 C738 C686 C687 C688 C689 C690
R721 1 2 56Ohm SM_A_MA13
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
RN7A SM_B_MA0
2

1 56Ohm 16
2 15 RN7B SM_B_MA1
56Ohm SM_B_MA2
3 14 RN7C
56Ohm SM_B_MA3
4 13 RN7D
B 56Ohm SM_B_MA4 B
5 12 RN7E
56Ohm SM_B_MA5
6 11 RN7F
56Ohm SM_B_MA6
7 10 RN7G
56Ohm SM_B_MA7
8 9 RN7H
56Ohm

1 16 RN8A SM_B_MA8
56Ohm SM_B_MA9
2 15 RN8B
56Ohm SM_B_MA10
3 14 RN8C
56Ohm SM_B_MA11
4 13 RN8D
56Ohm SM_B_MA12
5 12 RN8E
56Ohm SM_B_MA13
6 11 RN8F
56Ohm
7 10 RN8G
56Ohm
8 9 RN8H
56Ohm

A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan DDR2 ADDRESS TERMINATION LIBRARY DATE :
2.0 SHEET 23 OF 61
5 4 3 2 1
A B C D E

TV OUT CN16
MINI_DIN_7P

8
L55 0.068UH
TV_C 1 2 C_CON 4

P_GND1
9,14 TV_DACC_OUT C
2 GND2
L54 0.068UH 6
TV_CVBS CVBS_CON CVBS2
9,14 TV_DACA_OUT 1 2
1 1
5 CVBS1

P_GND2
7 NC
L53 0.068UH 1
TV_Y Y_CON GND1
9,14 TV_DACB_OUT 1 2 3 Y

9
1

1
R534 R532 R526 C472 C474 C477 C478 C475 C473

150Ohm 150Ohm 150Ohm 5.6PF 5.6PF 5.6PF 5.6PF 5.6PF 5.6PF

1% 1% 1%

2
2

2
U38

TV_CVBS 1 6
2
PLACE ESD 2

2 5 +3VS Diodes near

U44
TV_Y 3 4 TV_C

SRV05_4 @

+12VS
CRT Connector
3 L12 3
HSYNC_Q 1 2 HSYNC_Q_OUT
9,14 VSYNC
1 2 120Ohm/100Mhz ER1.1 -> PR2.0 (Obi-Wan)

1
C80
R6 100KOhm

1
C70 100PF/50V

4
L76 R931 0Ohm

2
1UF/10V Q19 2 1 1 2 R

D1

G2

S2
R 9,14
2
SI1902DL
80Ohm/100Mhz

1
1

1
L71 C563 C859 C860 R592
VSYNC_Q 1 2
33PF/50V 33PF/50V 33PF/50V

G1

D2
S1
60Ohm/100Mhz @ @ 150Ohm

2
1
C533

2
1

3
100PF/50V

2
9,14 HSYNC
L75 R932 0Ohm
+3VALWAYS 2 1 1 2 G
G 9,14
80Ohm/100Mhz

2
4 4
2

1
L13 C550 C861 C862 R590
R4 DDC2BD_Q 1 2
CN19 33PF/50V 33PF/50V 33PF/50V 150Ohm

16
100KOhm 9,14 DDC2BC 120Ohm/100Mhz @ @

2
1
C88

1
+5VS
2
1

3 100PF/50V 6
D
6

R82 11 1

2
Q4 2.2KOhm Q16 7
D1

G2

S2

11 2N7002 SI1902DL DDC2BD_Q_OUT 12 2

G L74 R933 0Ohm
8
1

2 S
3

3 13 3 2 1 1 2 B
D B 9,14
2

9
Q3 VSYNC_Q_OUT 14 4 80Ohm/100Mhz

2
2

11 2N7002 L70
G1

D2

10
S1

9,14,27,29,41,44,45 PLT_RST#_3

1
G 1 2 DDC2BC_Q_OUT 15 5 C540 C863 C864 R588
2 S R81
2.2KOhm 120Ohm/100Mhz 33PF/50V 33PF/50V 33PF/50V 150Ohm
2

C525 @ @

2
DDC2BC_Q

1
1

17
9,14 DDC2BD 100PF/50V D_SUB_15P3R
2

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan CRT & TV OUT LIBRARY DATE :
2.0 SHEET 24 OF 61

WWW.AliSaler.Com
A B C D E
5 4 3 2 1

+12VS +3VS LCD_+3VS

2
R56 C46 R55
Q70
D 1MOhm 0.1uF 1MOhm LCD_+3VS LCD_VCC D

2
1 6
2 D 5
S 4 L81

1
3
G 1 2
SI3456DV

3
3 80Ohm/100Mhz
D
l0805

1
Q11
11 C45 C615 C612 C613 C602 C609 C607
G 2N7002 47pF 1000PF 0.1uF/10V 10UF/25V 0.1uF/10V 0.1uF/10V
2 S 0.1uF/10V C1210

2
3
3

2
D
Q10
9,14 LCD_ENVDD 11
G 2N7002
2 S
2

R14

100KOhm
1

PLACED CLOSE TO CN8

14 ATI_L1_TX0- 3 0Ohm 4 RN2B

14 ATI_L1_TX0+ 1 0Ohm 2 RN2A

C C
14 ATI_L1_TX1- 1 0Ohm 2 RN13A
3 0Ohm 4 RN13B
14 ATI_L1_TX1+
LCD_VCC
14 ATI_L1_TX2- 3 0Ohm 4 RN4B
CN8
14 ATI_L1_TX2+ 1 0Ohm 2 RN4A
NP_NC1 25
21 GND1 GND3 23
14 ATI_L1_TXC- 1 0Ohm 2 RN15A LCD_VCC 1 1
14 ATI_L1_TXC+ 3 0Ohm 4 RN15B 2 2
3 3
4 4
9 L1_TX0- 1 0Ohm 2 RN12A @ 5 5
9 L1_TX0+ 3 0Ohm 4 RN12B @ 6 6
7 7
9 L1_TX1- 3 0Ohm 4 RN3B @ 8 8
1 0Ohm 2 RN3A @ 9 9
9 L1_TX1+
10 10
9 L1_TX2- 1 0Ohm 2 RN14A @ 11 11
9 L1_TX2+ 3 0Ohm 4 RN14B @ 12 12
13 13
CN3 9 L1_TXC- 3 4 RN5B @ 14
0Ohm 14
ER 1.1 -> PR 2.0 9 1 2 RN5A @ 15
AC_BAT_SYS SIDE2 9 L1_TXC+ 0Ohm 15
L56 1 2 80Ohm/100Mhz 1 16
AC_BAT_SYS 1 +3VS 16
2 R234 1 2 2.2KOhm 0Ohm 1 2 R609 17
2 +3VS 17
L58 2 1 60Ohm/100Mhz @ 3 R255 1 2 2.2KOhm 0Ohm 1 2 R185 18
9 LCD_BACK_ADJ 3 +3VS 18
4 0Ohm 1 2 R189 19
4 9,14 LVDS_DDC2BC 19
L57 2 1 60Ohm/100Mhz 5 0Ohm 1 2 R190 20
45 ADJ_BL 5 9,14 LVDS_DDC2BD 20
FPBACK_5 L59 2 1 60Ohm/100Mhz 6 22 24
6 GND2 GND4
7 7 NP_NC2 26
SIDE1 8
+3VS R546 2 1 100KOhm
B SR 1.0 -> ER 1.1 WTOB_CON_20P B
WTOB_CON_7P
D31
26,27 BACK_OFF# 2 1

RB751V_40
1

1 D27 C485
26,29,45 LID_RSM#
3
2 0.1uF/10V
9,14 LCD_ENBACK
RB717F
2
1

C494 C486
R238
1000PF 1000PF
10KOhm
1

1
2

A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan LCD & INVERTER LIBRARY DATE :
2.0 SHEET 25 OF 61
5 4 3 2 1
5 4 3 2 1

+3VS ER 1.1 -> PR 2.0

U62C

41 PDD[0:15]

1
PDD15 AD13 AE3 R432 10KOhm
PDD14 DD_15 SATA_0RXN R789
AG15 DD_14 SATA_0RXP AD3 1 2 +3VALWAYS
PDD13 AE15 AG2
PDD12 DD_13 SATA_0TXN U62D R787 0Ohm 10KOhm @
AC13 DD_12 SATA_0TXP AF2
PDD11 AB13 AC5 AD19 PM_BMBUSY#_R 1 2
PDD10 DD_11 SATA_1RXN PANEL_ID1 BMBUSY#/GPI6 PM_BMBUSY# 9

2
AB12 DD_10 SATA_1RXP AD5 27 PANEL_ID1 P4 LDRQ_1#/GPIO41 GPI7 AE19
PDD9 AF13 AF4 R1
DD_9 SATA_1TXN GPI8 EXTSMI# 45

1
PDD8 AE13 AG4 W6 R428 1 2 0Ohm @
D PDD7 DD_8 SATA_1TXP SMBALERT#/GPIO11 LID_RSM# 25,29,45 D
AB11 AD7 P2 M2 R786
PDD6 DD_7 SATA_2RXN 5,44,45 LAD0 LAD_0/FWH0 GPI12 KB_SCI# 27,45
AD11 AC7 N3 R6 R429 1 2 10KOhm
PDD5 DD_6 SATA_2RXP 5,44,45 LAD1 LAD_1/FWH1 GPI13 +3VALWAYS
AC11 AF6 N5 AC21 10KOhm
PDD4 DD_5 SATA_2TXN 5,44,45 LAD2 LAD_2/FWH2 STP_PCI#/GPO18 STP_PCI# 6
AE14 DD_4 SATA_2TXP AG6 5,44,45 LAD3 N4 LAD_3/FWH3 GPIO19 AB21 GPIO_MUTE_POP 27,31
PDD3

2
AD12 DD_3 SATA_3RXN AC9 STP_CPU#/GPO20 AD22 STP_CPU# 6,48
PDD2 AF14 AD9 LDRQ0# N6 AD20
PDD1 DD_2 SATA_3RXP 27 LDRQ0# LDRQ_0# GPIO21 BACK_OFF# 25,27
AF15 AF8 P3 AD21 ER 1.1 -> PR 2.0 GPI7 MF
PDD0 DD_1 SATA_3TXN 5,44,45 LFRAME# LFRAME#/FWH4 GPIO23 MEN_ID2 FWH_WP# 27,44
AD14 DD_0 SATA_3TXP AG8 GPIO24 V3
SR 1.0 -> ER 1.1 R899 1 2 33Ohm P5
39 ACZ_BCLK_MDC GPIO25 CB_SD# 37
R414 1 2 33Ohm C10 R3 1 400Mhz
30 ACZ_BCLK_AC ACZ_BIT_CLK GPIO27 PCB_ID0 27
AC2 R420 1 2 33Ohm A10 T3
SATA_CLKN 30,31,39 ACZ_RST# ACZ_RST# GPIO28 PCB_ID1 27
AC1 R411 1 2 33Ohm F11 AF19
SATA_CLKP 30 ACZ_SDIN0 ACZ_SDIN_0 CLKRUN#/GPIO32 MEN_ID0 CLKRUN#_3 27,34,38,40,44,45
R410 1 2 33Ohm F10 AF20 0 533Mhz
39 ACZ_SDIN1 ACZ_SDIN_1 GPIO33 MEN_ID1
AB15 R417 1 2 33Ohm @ B10 AC18
41 PDDACK#_3 DDACK# 30 ACZ_SDIN2 ACZ_SDIN_2 GPIO34
AB14 AG11 R437 1 2 33Ohm C9 AG25
41 PDDREQ_35 DDREQ SATARBIAS# 30,39 ACZ_SDOUT ACZ_SDOUT CPUPWRGD/GPIO49 H_PWRGD 3
AE16 AF11 R438 1 2 33Ohm B9
41 PDIOR#_3 DIOR# SATARBIAS 30,39 ACZ_SYNC ACZ_SYNC
41 PDIOW#_3 AC14 DIOW# 6 CLK_ICH14 E10 CLK14
41 PIORDY_35 AF16 IORDY 1 2 1 2 +3VS
@ R783 10KOhm R776 10KOhm
1 2 1 2 +3VS
D12 R403 10KOhm R402 10KOhm @
EE_CS
F13 EE_DIN 1 2 1 2 +3VS
AC16 D11 @ R472 10KOhm R473 10KOhm
41 PDA0_3 DA0 EE_DOUT
41 PDA1_3 AB17 DA1 B12 EE_SHCLK 1 2 +3VALWAYS
AC17 R474 10KOhm @
41 PDA2_3 DA2
AG21 MCH_SYNC#
MCH_SYNC# PWRBTN#_RSM MCH_SYNC# 27
SMBCLK Y4 SMBCK_ICH 42 F12 LAN_CLK PWRBTN# U1 PWRBTN#_RSM 29
41 PDCS1#_3 AD16 DCS1# SMBDATA W5 SMBDA_ICH 42 B11 LAN_RSTSYNC RI# T2 RIA# 37
41 PDCS3#_3 AE17 DCS3# E12 LAN_RXD_0
+VCCP E11 LAN_RXD_1
C13 LAN_RXD_2
C C
C12 LAN_TXD_0

2
C11 T4 SLP_S3#_R
LAN_TXD_1 SLP_S3# SLP_S4#1 SUSB#_3 29,37,38,47,55,56
E13 T5 R441 2 0Ohm
R766 LAN_TXD_2 SLP_S4# SLP_S5#1 R434 2 0Ohm @
27,41 IRQ14_3 AB16 IDEIRQ SLP_S5# T6 SUSC#_3 29,56
56Ohm

ER 1.1 -> PR 2.0

1
Y5 LINKALERT#
LINKALERT# LINKALERT# 27
W4 AF22 R920 0Ohm @
SMLINK_0 SM_LINK0 27 45 A20GATE_3 A20GATE
SMLINK_1 U6 SM_LINK1 27 3 H_A20M# AF23 A20M# 1 2 LPCPD# 44
3,8 H_CPUSLP#
R756 1 2 0Ohm @ H_CPUSLP#_R AE27 CPUSLP#
AE20 W3 PM_SUS_STAT#
27,48 PM_DPRSLPVR PM_DPRSTP#_R DPRSLPVR/TP_1 SUS_STAT#/LPCPD# SUS_STAT# 27
AC19 R757 1 2 0Ohm AE24
SATALED# 3 H_DPRSTP# H_DPSLP#_R AD27 DPRSLP#/TP_2 SUSCLK
SATA_0GP/GPI26 AF17 10KOhm 1 2 R794 +3VS 3 H_DPSLP#
R758 1 2 0Ohm DPSTP# SUSCLK V6 1 TP55
SATA_1GP/GPI29 AE18 PCB_ID2 27 3 H_IGNNE# AG26 IGNNE#
SATA_2GP/GPI30 AF18 10KOhm 1 2 R793 +3VS 44 FWH_INIT# AE22 INIT3_3V# SYS_RESET# U2 SYSRST# 29
SATA_3GP/GPI31 AG18 PEG_PRESENCE# 27 3 H_INIT# AF27 INIT#
INTRUDER# AA3 1MOhm 1 2 R461 +RTCVCC 3 H_INTR AG24 INTR LAN_RST# V5 LAN_RST# 29
3 H_FERR#
R754 1 2 56Ohm H_FERR#_R AF24 FERR#
AF25 V2 BAT_LLOW#_OC_ICH
5 NMI_ICH NMI BATLOW# BAT_LLOW#_OC_ICH 27
RSMRST# Y3 RSMRST# 27 45 RCIN# AD23 RCIN#
27,34,44,45 INT_SERIRQ AB20 SERIRQ TP_3 U3
C814 R755 1 2 0Ohm H_SMI#_R AG27
3 H_SMI# SMI#
Y1 RTC_X1 2 1 AE26
RTCX1 3 H_STPCLK# STPCLK#
1

H_THRMTRIP# AE23
THRMTRIP#
1

12PF/50V
R841 2
Y2 RTC_X2 X7
RTCX2 10MOhm 32.768KHZ
3
AF21 R770 1 2 0Ohm
C813 VRMPWRGD VRM_PWRGD 6,9,29,48,55
2

B 2 1 AC20 B
RTC_RST# THRM# PM_THRM# 7
4

RTCRST# AA2 RTC_RST# 42

12PF/50V

INTVRMEN AA5

SPKR F8 SPKRICH_3 30

ICH6_M
U5 PCIE_WAKE#
WAKE# PCIE_WAKE# 27

PWROK AA1 PWROK_ICH 27,29

+VCCP ICH6_M

MEMORY ID TABLE MEM_ID0 MEM_ID1 MEM_ID2

R289 (PU Resistor) should be placed within 2" GPIO33 GPIO34 GPIO24
from R290 (series resistor)
ON BOARD 256 MB 0 0 1
2

R290 (series resistor) should be placed within 1"

R759 from H_THRMTRIP# pin (of ICH6).
ON BOARD 512 MB 1 0 1
75Ohm
A A
1

R747 1 2 56OhmH_THRMTRIP#
3,9 PM_THRMTRIP#
ICH6-M P/N is 02-010004402HQ

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan ICH6M - LPC & IDE (1) LIBRARY DATE :
2.0 SHEET 26 OF 61

WWW.AliSaler.Com 5 4 3 2 1
5 4 3 2 1

+3VS

U62A
AD[0:31] 34,38,40 U62B
PAR_3 E1 E2 AD0 FRAME#_3 RP3A 1 5
34,38,40 PAR_3 DEVSEL#_3 PAR AD_0 DMI_RXN0 8.2KOhm
C3 E5 AD1 T25 C21 10
34,38,40 DEVSEL#_3 DEVSEL# AD_1 9 DMI_RXN0 DMI_RXP0 DMI_0RXN USBP_0N USBP0-_5 33 IRDY#_3
G6 C2 AD2 T24 D21 RP3B 2 5
6 CLK_ICHPCI PCIRST#_ICH PCICLK AD_2 9 DMI_RXP0 DMI_TXN0 DMI_0RXP USBP_0P USBP0+_5 33 8.2KOhm
R2 F5 AD3 R27 A20 10
34,38,40 PCIRST#_ICH PLT_RST#_3 PCIRST# AD_3 9 DMI_TXN0 DMI_TXP0 DMI_0TXN USBP_1N USBP1-_5 43 TRDY#_3
R5 F3 AD4 R26 B20 RP3C 3 5
9,14,24,29,41,44,45 PLT_RST#_3 IRDY#_3 PLTRST# AD_4 9 DMI_TXP0 DMI_RXN1 DMI_0TXP USBP_1P USBP1+_5 43 8.2KOhm
A3 E9 AD5 V25 D19 10
34,38,40 IRDY#_3 PME#_3 IRDY# AD_5 9 DMI_RXN1 DMI_RXP1 DMI_1RXN USBP_2N USBP2-_5 43 STOP#_3
P6 F2 AD6 V24 C19 RP3D 4 5
34,38,40 PME# SERR#_3 PME# AD_6 9 DMI_RXP1 DMI_TXN1 DMI_1RXP USBP_2P USBP2+_5 43 8.2KOhm
G5 D6 AD7 U27 A18 10
34,38,40 SERR#_3 STOP#_3 SERR# AD_7 9 DMI_TXN1 DMI_TXP1 DMI_1TXN USBP_3N USBP3-_5 43 SERR#_3
J1 E6 AD8 U26 B18 RP3E 6 5
34,38,40 STOP#_3 PLOCK#_3 STOP# AD_8 9 DMI_TXP1 DMI_RXN2 DMI_1TXP USBP_3P USBP3+_5 43 8.2KOhm
C5 D3 AD9 Y25 E17 10
D TRDY#_3 PLOCK# AD_9 9 DMI_RXN2 DMI_RXP2 DMI_2RXN USBP_4N USBP4-_5 43 DEVSEL#_3 D
J2 A2 AD10 Y24 D17 RP3F 7 5
34,38,40 TRDY#_3 PERR#_3 TRDY# AD_10 9 DMI_RXP2 DMI_TXN2 DMI_2RXP USBP_4P USBP4+_5 43 8.2KOhm
E3 D2 AD11 W27 B16 10
34,38,40 PERR#_3 FRAME#_3 PERR# AD_11 9 DMI_TXN2 DMI_TXP2 DMI_2TXN USBP_5N USBP5-_5 35 PERR#_3
J3 D5 AD12 W26 A16 RP3G 8 5
34,38,40 FRAME#_3 FRAME# AD_12 9 DMI_TXP2 DMI_RXN3 DMI_2TXP USBP_5P USBP5+_5 35 8.2KOhm
H3 AD13 AB24 C15 10
AD_13 9 DMI_RXN3 DMI_RXP3 DMI_3RXN USBP_6N USBP6-_5 33 PLOCK#_3
B4 AD14 AB23 D15 RP3H 9 5
AD_14 9 DMI_RXP3 DMI_TXN3 DMI_3RXP USBP_6P USBP6+_5 33 8.2KOhm
J5 AD15 AA27 A14 1 10
TP108 AD_15 9 DMI_TXN3 DMI_TXP3 DMI_3TXN USBP_7N
K2 AD16 AA26 B14 1 TP103 SR 1.0 -> ER 1.1
GNT0#_3 AD_16 9 DMI_TXP3 DMI_3TXP USBP_7P
1 C1 K5 AD17 TP105
GNT_0# AD_17 AD18 INT_PIRQA# RP2A
38 GNT1#_3 B6 GNT_1# AD_18 D4 1 5
8.2KOhm
F1 L6 AD19 C27 USB_OC_R#0 R762 1 2 0Ohm USB_OC_01# 10
34 GNT2#_3 GNT_2# AD_19 OC_0# USB_OC_01# 43 INT_PIRQB#
C8 G3 AD20 B27 RP2B 2 5
40 GNT3#_3 GNT4#_3 GNT_3# AD_20 OC_1# USB_OC_R#2 R763 1 8.2KOhm
E7 GNT_4#/GPIO48 AD_21 H4 AD21
OC_2# B26 2 0Ohm USB_OC_23# USB_OC_23# 43 10
F6 H2 AD22 C26 INT_PIRQC# RP2C 3 5
GNT4#_3 GNT_5#/GPIO17 AD_22 OC_3# USB_OC_R#4 R777 1 8.2KOhm
TP56 1 D8 GNT_6#/GPIO16 AD_23 H5 AD23
OC_4#/GPIO9 C23 2 0Ohm USB_OC_45# USB_OC_45# 43 10
B3 AD24 D23 INT_PIRQD# RP2D 4 5
AD_24 OC_5#/GPIO10 USB_OC_R#6 R764 1 8.2KOhm
+3VS
AD_25 M6 AD25 H25 HSIN_0 OC_6#/GPIO14 C25 2 0Ohm USB_OC_67# USB_OC_67# 43 10
B2 AD26 H24 C24 INT_PIRQE# RP2E 6 5
AD_26 HSIP_0 OC_7#/GPIO15 8.2KOhm
K6 AD27 G27 10
TP57 REQ0#_3 AD_27 AD28 HSON_0 INT_PIRQF# RP2F
1 L5 REQ_0# AD_28 K3 G26 HSOP_0 7 5
8.2KOhm
REQ1#_3 B5 A5 AD29 K25 10
38 REQ1#_3 REQ2#_3 REQ_1# AD_29 HSIN_1
34 REQ2#_3 M5 REQ_2# AD_30 L1 AD30 K24 HSIP_1 USBRBIAS B22 USBRBIAS INT_PIRQG# RP2G 8 5
8.2KOhm
REQ3#_3 B8 K4 AD31 J27 A22 R784 1 2 22.6Ohm 10
40 REQ3#_3 PANEL_ID0 REQ_3# AD_31 HSON_1 USBRBIAS# INT_PIRQH#
F7 J26 RP2H 9 5
REQ_4#/GPIO40 HSOP_1 8.2KOhm
R430 1 2 10KOhm E8 M25 10
R435 1 REQ_5#/GPIO1 HSIN_2
2 10KOhm B7 REQ_6#/GPIO0 M24 HSIP_2
L27 HSON_2
L26 HSOP_2
P24 HSIN_3
INT_PIRQA# N2 P23
INT_PIRQB# PIRQA# HSIP_3
L2 PIRQB# N27 HSON_3
INT_PIRQC# M1 N26
40 INT_PIRQC# INT_PIRQD# PIRQC# HSOP_3 REQ0#_3
L3 +1.5VS RP4A 1 5
C 40 INT_PIRQD# INT_PIRQE# PIRQD# 8.2KOhm C
34,38 INT_PIRQE# D9 PIRQE#/GPIO2 10
INT_PIRQF# C7 R376 REQ1#_3 RP4B 2 5
34 INT_PIRQF# INT_PIRQG# PIRQF#/GPIO3 8.2KOhm
34 INT_PIRQG# C6 PIRQG#/GPIO4 1 2 F24 DMI_ZCOMP CLK48 A27 CLK_USB48 6 10
INT_PIRQH# M3 G2 F23 REQ2#_3 RP4C 3 5
PIRQH#/GPIO5 C_BE_3# C/BE3#_3 34,38,40 DMI_IRCOMP 8.2KOhm
G4 24.9Ohm 1% 10
C_BE_2# C/BE2#_3 34,38,40 REQ3#_3
H6 RP4D 4 5
C_BE_1# C/BE1#_3 34,38,40 8.2KOhm
C_BE_0# J6 C/BE0#_3 34,38,40 10
PANEL_ID0 RP4E 6 5
8.2KOhm
10

RP4F 7 5
26 PANEL_ID1 8.2KOhm
R501 0Ohm 10
1 2 RP4G 8 5
8.2KOhm
10
RP4H 9 5
26,34,44,45 INT_SERIRQ 8.2KOhm
Q59 10
RSMRST#

C
3

E
2
RST_BTN# 29,55
RN9A 1 2
25,26 BACK_OFF# 8.2KOhm
PMBS3906 RN9B

1 B
6 CLK_PCIE_ICH# AD25 DMI_CLKN 26 PEG_PRESENCE# 3 8.2KOhm 4
AC25 @ RN9C 5 6
6 CLK_PCIE_ICH DMI_CLKP 26 LDRQ0# 8.2KOhm
D25 RN9D 7 8
26,44 FWH_WP# 8.2KOhm
1
D22
ICH6_M 3
1 2 R384 1 2 8.2KOhm
26,34,38,40,44,45 CLKRUN#_3
ICH6_M 3 R647 1 2 8.2KOhm
26,41 IRQ14_3
2 BAV99-7
@ R839 1 2 8.2KOhm
26,45 KB_SCI#
BAV99-7

1
@
R499 R493 +3VS

B 2.2KOhm 0Ohm R782 1 2 10KOhm B

26,31 GPIO_MUTE_POP
@
ER 1.1 -> PR 2.0 R453 1 2 4.7KOhm @

2
+3VALWAYS 26 SUS_STAT#
R773 1 2 20KOhm 1%
26 MCH_SYNC#
+3VALWAYS +3VALWAYS +3VS

R439 1 2 8.2KOhm
26 PCIE_WAKE#
2

PME#_3 R421 1 2 8.2KOhm PAR_3 R843 1 2 10KOhm YAGEO/RC0603FR-0710KL <G>

R463 R452 R792 R840 1 2 10KOhm YAGEO/RC0603FR-0710KL <G>
26,29 PWROK_ICH
R838 1 2 8.2KOhm R785 1 2 10KOhm YAGEO/RC0603FR-0710KL <G>
26 BAT_LLOW#_OC_ICH 26,48 PM_DPRSLPVR
4.7KOhm 4.7KOhm 4.7KOhm
@ @ R446 1 2 10KOhm
26 SM_LINK0 RSMRST# R451 1 2 10KOhm YAGEO/RC0603FR-0710KL <G>
1

PCB_ID0 26 26 RSMRST#
R431 1 2 10KOhm
PCB_ID1 26 26 SM_LINK1
PCB_ID2 26
2

R455 1 2 10KOhm
26 LINKALERT#
R464 R440 R790
SR 1.0 -> ER 1.1
4.7KOhm 4.7KOhm 4.7KOhm
@
ID2 ID1 ID0 USB_OC_67# R752 1 2 8.2KOhm
1

0 0 0 N/A USB_OC_45# R771 1 2 8.2KOhm

0 0 1 Enable Audio DJ USB_OC_23# R751 1 2 8.2KOhm
0 1 0 N/A USB_OC_01# R750 1 2 8.2KOhm
0 1 1 N/A
A 1 0 0 N/A A

1 0 1 N/A
1 1 0 N/A
1 1 1 Disable Audio DJ

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan ICH6M - USB&PCI-E&PMIO (2) LIBRARY DATE :
2.0 SHEET 27 OF 61
5 4 3 2 1
5 4 3 2 1

+5VS +3VS +5V +5VALWAYS +3VALWAYS

TP107 TP58
U62E

1
AA19 A8 +5VREF
+1.5VS VCC1_5_21 V5REF1 R436 D16 R923 D54 R864 D50

1
AA20 VCC1_5_22 V5REF2 AA18

1
C359 C367 C393 C381 C368 AA21 VCC1_5_23 10Ohm BAT54C 10Ohm 10Ohm BAT54C
L11 VCC1_5_24 VCC2_5_1 AB18
0.01U 0.1UF 0.1UF 0.1UF 0.1UF L12 P7 +2.5VS_PCI_IDE @ F01J2E @
VCC1_5_25 VCC2_5_2

1
L14 VCC1_5_26 U62F
+5VREF 1 +5VREF_SUS

3
L16 VCC1_5_27 2
L17 R847 0Ohm A1 G21
VCC1_5_28 +5VREF_SUS VSS1 VSS87
M11 VCC1_5_29 V5REF_SUS F21 A12 VSS2 VSS88 G7
M17 ER 1.1 -> PR 2.0 ER 1.1 -> PR 2.0 A15 G9
D VCC1_5_30 VSS3 VSS89 D
P11 VCC1_5_31 A19 VSS4 VSS90 H23
Place 0.01uF Place 4X0.1uF P17 VCC1_5_32 R848 10Ohm @
A21 VSS5 VSS91 H26
T11 VCC1_5_33 A23 VSS6 VSS92 H27
within 100mils Distribute near T17 VCC1_5_34
R413 0Ohm r1206 2 1 A26 VSS93 J23
+2.5VS_PCI_IDE VSS7
of ICH near pin ICH6 U11 VCC1_5_35 2 1 +2.5VS A4 VSS8 VSS94 J24
U12 VCC1_5_36 A7 VSS9 VSS95 J25
pin AA19 Package edge U14 VCC1_5_37
Q101 A9 VSS10 VSS96 J4

1
U16 C378 SI2301BDS AA11 K1
VCC1_5_38 @ VSS11 VSS97
U17 VCC1_5_39 AA13 VSS12 VSS98 K23
G8 10uF/10V 2 3 AA16 K26

3 D
VCC1_5_40 +5VALWAYS VSS13 VSS99
c0805

2
D24 VCC1_5_41 AA4 VSS14 VSS100 K27
D25 AB1 K7

G
VCC1_5_42 VSS15 VSS101
D26 AB10 L13

11
VCC1_5_43 R851 VSS16 VSS102
D27 VCC1_5_44 AB19 VSS17 VSS103 L15
Place BOTH E20 L89 R745 2 1 AB2 L23
VCC1_5_45 VSS18 VSS104

1
C327 C328 E21 +1.5VS_DMIPLL 1 2 2 1 AB7 L24
VCC1_5_46 +1.5VS VSS19 VSS105

3
within 100mils of E22 VCC1_5_47
100KOhm 3
D AB9 VSS106 L25
0.1UF 0.1UF 120Ohm/100Mhz 0Ohm @ VSS20
ICH near pin E23 VCC1_5_48 AC10 VSS21 VSS107 M12
r1206 Q102

2
E24 VCC1_5_49 AC12 VSS22 VSS108 M13

1
D27 F20 VCC1_5_50
C757 C747
+3VALWAYS 11 AC22 VSS23 VSS109 M14
G20 G 2N7002 AC23 M15
VCC1_5_51 2 S VSS24 VSS110

2
F9 0.01U 10uF/10V @ AC24 M16
VCC1_5_52 VSS25 VSS111
c0805 R842

2
AC26 VSS26 VSS112 M23
AC3 VSS27 VSS113 M26
AB22 1MOhm AC6 M27
+VCCP V_CPU_IO_1 VSS28 VSS114
AD26 AC27 @ AD1 M4
1

C347 V_CPU_IO_2 VCCDMIPLL VSS29 VSS115

1
AG23 V_CPU_IO_3 AD10 VSS30 VSS116 N1
AE1 +1.5VS_SATAPLL AD15 N11
0.1UF VCCSATAPLL VSS31 VSS117
Place 0.1uF within 100mils AD18 VSS32 VSS118 N12
2

A25 +1.5VS_USBPLL AD2 N13

of ICH near pin AG23 VCCUSBPLL VSS33 VSS119
120Ohm/100Mhz AD24 N14
VSS34 VSS120
VCCDMIPWR1 AA22 1 2 +1.5VS AD6 VSS35 VSS121 N15
C C
VCCDMIPWR2 AA23 AE10 VSS36 VSS122 N16

1
AA12 AA24 + L90 AE11 N17
+3VS VCC3_3_1 VCCDMIPWR3 VSS37 VSS123

1
AA14 AA25 CE19 C751 C759 C758 AE12 N7
VCC3_3_2 VCCDMIPWR4 VSS38 VSS124
1

C429 C334 C386 C419 AA15 AB25 150U/4.0V AE2 P12

VCC3_3_3 VCCDMIPWR5 VSS39 VSS125
AA17 AB26 C7343D 0.1UF 0.1UF 0.1UF AE21 P13
VCC3_3_4 VCCDMIPWR6 VSS40 VSS126
10uF/10V 0.1UF 0.1UF 0.1UF

2
AC15 VCC3_3_5 VCCDMIPWR7 AB27 AE25 VSS41 VSS127 P14
c0805
2

AD17 VCC3_3_6 VCCDMIPWR8 F25 AE6 VSS42 VSS128 P15

C402 0.1U @ AG13 F26 AE7 P16
VCC3_3_7 VCCDMIPWR9 VSS43 VSS129
1 2 AG16 VCC3_3_8 VCCDMIPWR10 F27 AF1 VSS44 VSS130 P22
AG19 VCC3_3_9 VCCDMIPWR11 G22 Place 150uF, 3 X 0.1uF AF12 VSS45 VSS131 R11
A6 VCC3_3_10 VCCDMIPWR12 G23 AF26 VSS46 VSS132 R12
+1.5VS +3VS B1 VCC3_3_11 G24 within 100mils of ICH near AF3 VSS47 VSS133 R13
VCCDMIPWR13
E4 VCC3_3_12 VCCDMIPWR14 G25 pin F27, P27, AB27 AF7 VSS48 VSS134 R14
H1 VCC3_3_13 VCCDMIPWR15 H21 AG1 VSS49 VSS135 R15
1

1 2 C416 C388 C394 C438 H7 H22 AG12 R16

VCC3_3_14 VCCDMIPWR16 VSS50 VSS136
J7 VCC3_3_15 VCCDMIPWR17 J21 AG14 VSS51 VSS137 R17
C399 0.1U @ 0.1UF 0.1UF 0.1UF 0.1UF L4 J22 R837 0Ohm AG17 R23
VCC3_3_16 VCCDMIPWR18 VSS52 VSS138
+1.5VS_SATAPLL
2

L7 VCC3_3_17 VCCDMIPWR19 K21 1 2 +1.5VS AG20 VSS53 VSS139 R24

M7 VCC3_3_18 VCCDMIPWR20 K22 AG22 VSS54 VSS140 R25
P1 VCC3_3_19 VCCDMIPWR21 L21 AG3 VSS55 VSS141 R4

1
E26 L22 C425 AG7 T1
VCC3_3_20 VCCDMIPWR22 VSS56 VSS142
AA10 VCC3_3_21 VCCDMIPWR23 M21 B13 VSS57 VSS143 T12
LAN3.3V/VCC3.3SUS +3.3V_VCCPAUX AG10 M22 0.1UF B15 T13
+3VS VCC3_3_22 VCCDMIPWR24 VSS58 VSS144

2
N21 B19 T14
1

VCCDMIPWR25 VSS59 VSS145

C382 C385 N22 B21 T15
VCCDMIPWR26 VSS60 VSS146
A13 VCCSUS3_3_1 VCCDMIPWR27 N23 B23 VSS61 VSS147 T16
0.1UF 0.1UF F14 N24 B25 T23
VCCSUS3_3_2 VCCDMIPWR28 VSS62 VSS148
2

G13 VCCSUS3_3_3 VCCDMIPWR29 N25 C14 VSS63 VSS149 T26

G14 VCCSUS3_3_4 VCCDMIPWR30 P21 C18 VSS64 VSS150 T27
+3VALWAYS +3.3V_VCCPSUS A11 P25 R370 0Ohm C20 T7
VCCSUS3_3_5 VCCDMIPWR31 VSS65 VSS151
U4 P26 +1.5VS_USBPLL 1 2 C22 U13
1

VCCSUS3_3_6 VCCDMIPWR32 +1.5VS VSS66 VSS152

C370 V1 P27 C4 U15
B VCCSUS3_3_7 VCCDMIPWR33 VSS67 VSS153 B
V7 VCCSUS3_3_8 VCCDMIPWR34 R21 D1 VSS68 VSS154 U23

1
0.1UF W2 R22 C332 D10 U24
VCCSUS3_3_9 VCCDMIPWR35 VSS69 VSS155
2

Y7 VCCSUS3_3_10 VCCDMIPWR36 T21 D13 VSS70 VSS156 U25

+3VA_ICH A17 T22 0.01U D14 V23
VCCSUS3_3_11 VCCDMIPWR37 VSS71 VSS157
+3VALWAYS

2
B17 VCCSUS3_3_12 VCCDMIPWR38 U21 D18 VSS72 VSS158 V26
1

C369 C375 C16 U22 D20 V27

VCCSUS3_3_13 VCCDMIPWR39 VSS73 VSS159
C17 VCCSUS3_3_14 VCCDMIPWR40 V21 D22 VSS74 VSS160 V4
0.1UF 0.1UF D16 V22 D7 W1
VCCSUS3_3_15 VCCDMIPWR41 VSS75 VSS161
Place BOTH within
2

E16 VCCSUS3_3_16 VCCDMIPWR42 W21 E14 VSS76 VSS162 W23

F15 VCCSUS3_3_17 VCCDMIPWR43 W22 E15 VSS77 VSS164 W25
100mils of ICH near pin F16 VCCSUS3_3_18 VCCDMIPWR44 Y21 E18 VSS78 VSS165 W7
+3VA_ICH F18 Y22 E19 Y23
A17 VCCSUS3_3_19 VCCDMIPWR45 VSS79 VSS166
G15 E25 Y26
1

C344 VCCSUS3_3_20 +1.5VS_SATA VSS80 VSS167

+RTCVCC G16 VCCSUS3_3_21 VCC1_5_1 AA6 +1.5VS F17 VSS81 VSS168 Y27
0.1UF G17 VCCSUS3_3_22 VCC1_5_2 AB4 F19 VSS82 VSS169 Y6
1

C426 C423 G18 AB5 F22 W24

VCCSUS3_3_23 VCC1_5_3 VSS83 VSS170
2

A24 VCCSUS3_3_24 VCC1_5_4 AB6 F4 VSS84 VSS171 E27

1

0.01U 0.1UF AC4 C405 Place within G1 B24

VCC1_5_5 VSS85 VSS172
2

VCC1_5_6 AD4 G12 VSS86 VSS173 AF10

AB3 VCCRTC VCC1_5_7 AE4 0.1UF 100mils of ICH
R396 0Ohm
2

VCC1_5_8 AE5 near pin AG5 ICH6_M

1 2 +1.5VA_USB R7 AG5
VCCSUS1_5_A VCC1_5_9
+1.5VALWAYS AF5
1

C404 C403 C364 VCC1_5_10

U7 VCCSUS1_5_B VCC1_5_11 AA7
R418 0Ohm AA8
0.1UF 0.1UF 0.1UF VCC1_5_12
+1.5VS 1 2 G19 VCCSUS1_5_C VCC1_5_13 AA9
2

VCC1_5_14 AB8 Place within

1

G10 AC8 C397

R425 0Ohm @ VCCSUS1_5_D VCC1_5_15 100mils of ICH
VCC1_5_16 AD8
1 2 +1.5V_VCCAUX G11 AE8 0.1UF
+1.5VALWAYS VCCSUS1_5_E VCC1_5_17 near pin AG9
2

AE9
1

C398 VCC1_5_18
VCC1_5_19 AF9
A AG9 A
0.1UF VCC1_5_20
2

ICH6_M

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan ICH6M - PWR & GND (3) LIBRARY DATE :
2.0 SHEET 28 OF 61

WWW.AliSaler.Com 5 4 3 2 1
A B C D E

+3VS
+5VS
+3VALWAYS_P

1
+3VALWAYS

1
R447

2
R467 2
S

1
Q52 220KOhm C818 C816

1
220KOhm Q51 R852
11 R849 1UF/10V 0.1uF/10V

2
1 S1 D1 6
1 G NDS0610 47KOhm 1

2
3 D 100KOhm 1%
ER1.1 -> PR2.0 (Obi-Wan) @

2
2 G1 G2 5
TP109

2
1

3
3

14
3 D2 S2 4 D
1

1
C421 SW3 74LV14APWR

1
R466 6 5 VCC Q100 C821
0.01UF/16V SI1902DL 2 1 1 2 11 ADD FOR

3
220KOhm 2N7002 1UF/10V
2

G RC-RESET
+5VS Q53 GND 2 S @ @

2
VDD

1
C823 U66A

2
LM809M3X-2.93 4 3
4.7u

7
1

RESET#
U30 R481 1mA/5V C1206
1 A C422 @

2
5 1 2

GND
6,9,26,48,55 VRM_PWRGD VCC LAN_RST# 26 TP60
0Ohm +3VALWAYS_P
2 B 0.1uF/10V R480

2
55 POWERGD
1 2 SYSRST# 26
0Ohm

1
14
3 GND 4
Y 74LV14APWR
NC7SZ08P5X D51 VCC
PWROK_ICH 26,27 RST_BTN#
@ 2 1 3 4
55 PWRERR# RST_BTN# 27,55
GND
1SS355 U66B

7
2 2
R456 D67
1 2 7,54 OTP#_P 2 1
0Ohm
+3VALWAYS_P +3VALWAYS
1SS355

+3VS
ER 1.1 -> PR 2.0
+3VALWAYS_P +3VALWAYS_P
1

1
R832

1
R834 1 2 R874 C834

2
0Ohm 2
14

14
S
100KOhm 74LV14APWR 74LV14APWR 1MOhm 1000PF
D48 VCC VCC D47 Q116

2
11
2

2
26,37,38,47,55,56 SUSB#_3 2 1 5 6 9 8 1 2 CPU_VRON 48,50 G IRLML5103TR
3 D
1

C805 GND GND 1SS355 @

3
1SS355 U66C U66D 3

3
+3VALWAYS D
0.1uF/10V Q112
7

2
R871
2

D61 R850 11
1SS355 1MOhm G
S 2
1MOhm 2N7002

2
1

1
3 3
52 BAT_IN
R880

1
C839
10uF/10V R879 100Ohm
c0805 Q106 Q117

3
3 100KOhm

32
D

1
2N7002 2N7002 N/A 3

1
D60 D

G
+3V

2
11 Q107 Q61

2 S

2 S

3
26,56 SUSC#_3 2 3 2 3 2 1

D
G 11
U26 C383 2 S 2N7002 G 2N7002
1 A RB751V_40 2 S

2
9,14,24,27,41,44,45 PLT_RST#_3 VCC 5 2 1

2
45 PCIRST#_GATE 2 B 0.1uF/10V
3 GND 4 PCIRSTNS#_3 5,34,38,45
Y
1

NC7SZ32P5 +3VALWAYS_P +3VALWAYS_P +3VALWAYS

R412

1MOhm

14

14

1
U66E U66F
2

VCC VCC R845

26 PWRBTN#_RSM 10 11 12 13
4
100KOhm ER1.1 -> PR2.0 (Obi-Wan) 4
GND GND
74LV14APWR 74LV14APWR

2
D55 D56
7

7
1 1
3 3 PWRON#_DJ 47
2 2 SR 1.0 -> ER 1.1
7 THERM_PRO#
R859 JP22 +3VALWAYS_P RB715F RB715F

3
1 2 1 2 3 @ +5VS +5V
+3V D

1
1KOhm OPEN2MM Q103 C810 R895 1 2 0Ohm
45 ANYKEY_RSM 11 R877 @
G 2N7002 0.1uF/10V R894 1 2 0Ohm
2 S 1MOhm

2
1

C831

2
1 LID_BOT# 46
TP111 0.1uF/10V
2

11

1
C838

1
G
G
0.1uF/10V

2 S

3
3 2 2 3

S 2
LID_RSM# 25,26,45

D
D
11
Q62 2N7002 Q60 2N7002

G
5 5
3 2

S 2
PWRON# 46

D
Q115 2N7002 1 TP23

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan RESRT CIRCUIT LIBRARY DATE :
2.0 SHEET 29 OF 61
A B C D E
5 4 3 2 1

+3VS

C353 0.01UF/16V R407 0Ohm

2 1 1 2 PCSPKI +3VS

C354 0.1uF/10V U23 DVDD

34 SPKRCB 2 1@ 1 A VCC 5

1
26 SPKRICH_3 2 B C406 C407 C418
D D
3 GND 4 10uF/10V 0.1UF 0.1UF

2
Y
C365 0.1uF/10V NC7SZ86P5X
2 1 @
LINE_OUT_R S/PDIF 32
LINE_OUT_L AC_SDOUTR 31
SR 1.0 -> ER 1.1
AC_SDOUTL 31
AVDD
+5VA
R891 1 2 0Ohm

1
@ C420 C424
U32
10uF/10V 0.1UF

49
48
47
46
45
44
43
42
41
40
39
38
37
AD1986AJCP

2
GND

EAPD
AVDD5
LINE_OUT_R
AVSS4

AVDD4
HEADPHONE_R
AVSS3

AVDD2
S/PDIF_OUT

LINE_OUT_L

HEADPHONE_L

MONO_OUT
AGND_A
1 DVDD1 SURR_OUT_R 36
2 AC97CK SURR_OUT_L 35
31 MUTE_POP_AZGPIO#
R449 1 2 0Ohm GPO 3 GPO AVDD3 34
R496 C430 4 33
CD-L SDATA_OUT DVSS1 VREF_OUT/C/LFE
41 CD-L_A 1 2 2 1 26,39 ACZ_SDOUT 5 SDATA_OUT LFE_OUT 32
SR 1.0 -> ER 1.1 R454 1 2 22Ohm BIT_CLK 6 31
26 ACZ_BCLK_AC BIT_CLK CENTER_OUT
4.7KOhm 1UF/10V C412 2 1 10PF 7 30
DVSS2 AVSS2
1

R458 1 2 33Ohm SDATA_IN 8 29

26 ACZ_SDIN0 SDATA_IN VREF_OUT/LINE_IN VREF_OUT/MIC_1/2
R491 R457 1 2 33Ohm 9 28
26 ACZ_SDIN2 SYNC DVDD2 VREF_OUT/MIC_1/2 VREF_FILT MIC_VREF 33
@ 10 27

JACK_SENSE_A
JACK_SENSE_B
26,39 ACZ_SYNC RESET# SYNC VREF_FILT
4.7KOhm R465 1 2 0Ohm 11 26
26,31,39 ACZ_RST# RESET# AVSS1
C428 0.1UF 12 25
PCBEEP AVDD1

2
PHONE_IN

LINE_IN_R
LINE_IN_L
PCSPKI 1 PCSPKI_AC PCBEEP C413 C415
2

2 1 2

CD_GND
C R469 4.7KOhm C

AUX_R
AUX_L
1

MIC_1
MIC_2
CD_R
1U 0.1UF

CD_L
1
R478 C442 R889

1
AGND_A
4.7KOhm 0.1UF/16V 10KOhm

13
14
15
16
17
18
19
20
21
22
23
24
2
2

2
SR 1.0 -> ER 1.1 AGND_A
LINE_IN_R C446 2 1 1UF/10V
@
LINE_IN_L C437 2 1 1UF/10V PCSPKI_AC
AGND_A @

R498 C431
1 2 2 1 CD-G AVDD R477 1 2 2.2KOhm JACK_SENSE_A
41 CD_GND
R492 1 2 2.2KOhm JACK_SENSE_B
2.4KOhm 1UF/10V
1

CD-L MIC_2 C434 2 1 1UF/10V

R487 CD-G
CD-R MIC_1 C433 2 1 1UF/10V MIC_AC 33
2.4KOhm
2

AGND_A

B B

+5VS

R500 C432

1
1 2 2 1 CD-R
41 CD-R_A
R505
4.7KOhm 1UF/10V 0Ohm
1

+5V +5VA
R488 U37
MAX8863 TP61

2
4.7KOhm 1 4 1
L50 SHDN# OUT
2 GND C449 2 1 1000PF
2

1 2 3 IN SET 5

400Ohm/100Mhz R497 100KOhm

2
MAX8863 1 2
1

AGND_A C459 C457 C461 C460 C462

1
C455
10uF/10V 1UF/10V R868 1UF/10V 0.1UF 0.1UF

1
10uF/10V
2

34KOhm

2
L94 R875 R878 1%

1
1 2 1 2 1 2

400Ohm/100Mhz 0Ohm 0Ohm

A AGND_A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan AZALIA AD1986A
LIBRARY DATE :
2.0 SHEET 30 OF 61

WWW.AliSaler.Com 5 4 3 2 1
A B C D E

1 1

+5VAMP

+5V +5VS +5VAMP +5VAMP_PVDD

L42 1 2 80Ohm/100Mhz L43 1 2 80Ohm/100Mhz

2

l0805 l0805

1
R401 R397 L41 1 2 80Ohm/100Mhz @ +

1
10KOhm @ 10KOhm @ l0805 C390

1
+ 10U/16V_TAN C384
GAIN0 C361 C3528 0.1uF/10V
1

10U/16V_TAN

2
GAIN1 C3528 +3VALWAYS

2
2

2
GAIN0 GAIN1 SE/BTL# Av (inv) +5VAMP
R399 R390 0 0 0 6 dB R422
0Ohm 0Ohm 0 1 0 10 dB AGND_A
1 0 0 15.6 dB 47KOhm
1 1 0 21.6 dB U24
1

X X 1 4.1 dB C366 0.47UF/6.3V

1
2 1 GND1 GND4 24 2
GAIN0 2 23 1 2
GAIN1 PCB ENABLE RLINEIN
3 VOLUME SHUTDOWN# 22
INTSPKL+ 4 21 INTSPKR+ R427
AGND_A 33 INTSPKL+ LOUT+ ROUT+ INTSPKR+ 33
C374 2 1 0.47UF/6.3V 5 20 1 2 1 2
LLINEIN RHPIN AC_SDOUTR 30
30 AC_SDOUTL 2 1 6 LHPIN VDD 19
C380 0.47UF/6.3V @ 7 18 C373 0.47UF/6.3V @ 0Ohm
PVDD1 PVDD2

1
8 RIN CLK 17
INTSPKL- 9 16 INTSPKR- R426
33 INTSPKL- LOUT- ROUT- SE/BTL# INTSPKR- 33
10 15 10KOhm
LIN SE/BTL#
11 BYPASS PC-BEEP 14
12 13 @
GND2 GND3

1
C387 C389 C391

2
2
TPA0312
0.47UF/6.3V 0.47UF/6.3V 0.47UF/6.3V
R409

2
0Ohm AGND_A +5VAMP

+5VAMP

2
"1" headphone
U25 "0" Intspeak R424
5 VCC A 1 10KOhm
JACK_SENSE 32
AGND_A B depop_5

1
2
3 4 3 Q49 3
GND

3
Y 3 2N7002
D
NC7SZ32P5
11 MUTE_POP#
G
AGND_A S 2

2
+12V

AGND_A

AC_LNLVL_R 32
1

R486 R485 D20

2 1 MUTE_POP#
100KOhm 100KOhm
AC_LNLVL_L 32
1SS355
ER1.1 -> PR2.0 MUTE_POP#
2

2
6

R448 1KOhm R476 1 2 1MOhm

2 1 2 Q55A
4 30 MUTE_POP_AZGPIO# 4
2

UM6K1N
3

R468
1

4
R450 0Ohm @ C435
2 1 5 Q55B 240KOhm 10uF/10V Q47 Q46

D1

G2

S2

D1

G2

S2
26,30,39 ACZ_RST#
UM6K1N SI1902DL SI1902DL
2
4

D66 Substitute by a
26,27 GPIO_MUTE_POP 2 1 1uF/25V(0805)
11-032110520 G1

G1
D2

D2
S1

S1
RB751V_40
1

3
INTSPKR+

INTSPKL+
Can be
substituted by
5
UM6K1N or 5
SI1902DL

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan AUDIO AMP & INT SPK LIBRARY DATE :
2.0 SHEET 31 OF 61
A B C D E
A B C D E

+12V

INT_MIC
33 INT_MIC
+5VA

1
R760 R739
INT/EXT#_MIC 1 2 INT/EXT#_MIC_1
100KOhm

2
1 1
0Ohm

3
3 R738

2
D

3
INT/EXT#_MIC Q40 3 Q41
D
2N7002 10KOhm
11 2N7002

1
C742 11

1
G
2 S G
S
470PF/50V 2

22

1
S 2 R736 420 Ohm/100MHz

2
G
1 Q42
1 CN29
2N7002 8 NP_NC2
+5VAMP

2
D 5
3 AGND_A AGND_A
4
MIC_IN_1

3
3
+5VAMP R748 R749 6
MIC_IN 1 2 1_AJK 1 2 MIC_IN_0 2
33 MIC_IN
1

1
0Ohm 420 Ohm/100MHz 7

1
NP_NC1
R378 R382 C748 C749 C752
R741
10KOhm 10KOhm 1000PF 1000PF 470PF/50V PHONE_JACK_6P
0Ohm

2
R375 @

2
R357 0Ohm

2
1 2
2 1 2 AUD_GND 2
31 JACK_SENSE
3 0Ohm @
3 Q88 AGND_A
D
2N7002

11 JACK_IN# AGND_A AGND_A AGND_A

G
S 2
2

AGND_A R775 1 CN30

2 0Ohm R361 1 2 420 Ohm/100MHz 5
C767 R765 33Ohm 4
left_channel_in
+

1 2 1 2 R761 1 2 0Ohm AC_LNLVL_L_M R360 1 2 100Ohm 2

31 AC_LNLVL_L right_channel_in
1 2 R780 1 2 0Ohm AC_LNLVL_R_M R371 1 2 100Ohm 3
47U/6.3V 1 OPTIC_HP# R767 1 2 0Ohm L40 1 2 120Ohm/100MHz 1
R779 33Ohm T153
C778 TPC28t
+

31 AC_LNLVL_R 1 2

1
C325 C316 C333 C322 C329 C310 C340 C319
47U/6.3V 11
47pF/50V 47pF/50V 47pF/50V 0.1UF 47pF/50V 47pF/50V 47pF/50V 47pF/50V 12
2

C349 R380

2
R381 R367 AUD_GND
EMI 47pF/50V
1 2

1KOhm 1KOhm 0Ohm

2

3 @ @ 3
1

AGND_A AGND_A AGND_A AGND_A

8
SR 1.0 -> ER 1.1 7
R901 1 2 0Ohm R346 1 2 0Ohm
AGND_A AGND_A AGND_A

10
6
9
R928 1 2 0Ohm

ER 1.1 -> PR 2.0

AGND_A AGND_A

+5VA
+5VA +5VA AGND_A

D65 L95 L96

1 2 2 1 2 1
2

R910 R911 1N4148W-A2 120Ohm/100MHz 120Ohm/100MHz

1

1
4
10KOhm 10KOhm C846 C847 C848 C849 4
2

2 0.1UF 0.1UF 4.7UF/10V 0.1UF

1

S
2

2
Q120
11 +5VA
G SI2301BDS
3 D
3

3 U73 AGND_A AGND_A AGND_A AGND_A

D
1 A
3

VCC 5
Q119
OPTIC_HP# 11 2 B
30 S/PDIF L97 L98
JACK_IN# OPTIC_HP# G 2N7002
2 S
1

3 GND 4 2 1 2 1
JACK_IN# R912
2

Y
L H SPDIF NC7SZ08P5X 120Ohm/100MHz 120Ohm/100MHz
1

1
10KOhm C850 C851
R934 Second source:
1

L L LINE OUT C844 C845 D64 0.1UF 0.1UF

2

V0402MHS03 10KOhm
06-004046010 @ @
2

2
0.1UF 0.1UF @
H H NO CONNECT
2

AGND_A
2

AGND_A AGND_A

ER1.1 -> PR2.0 (Obi-Wan)

5 AGND_A AGND_A 5
AGND_A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan PHONE JACK LIBRARY DATE :
2.0 SHEET 32 OF 61

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A B C D E

MIC PreAmp & Mic Jack External Modules

+3V_BT
1 1
+5VA

1
R482 +5VA
Bluetooth Module CN

1
L47
1KOhm 1 2 R601
@ ER1.1 -> PR2.0 (Obi-Wan)

5
R459 0Ohm U34 80Ohm/100Mhz 0Ohm CN5

2
1 2 1 V+
30 MIC_VREF +
R495 22KOhm

2
4 SIDE1 11
2 1 1_MOP 1 2 3 1
- 1
V- 2
27 USBP0+_5 2
2

1
C443 MAX4490AXK C439 3
27 USBP0-_5 3
R484 R475 2.2UF/6.3V

2
4 4

2
0.1uF/10V CH_CLK_BT 5
2.2KOhm 1KOhm R479 5

2
6 6
@ CH_DATA_BT 7
20KOhm AGND_A 7
1

8 8
@ 9
MIC_IN R489 200KOhm 9

11
32 MIC_IN 10 10
C436 2_MOP 1 2 12
AGND_A SIDE2
1UF/10V C441 18PF/50V
2 @ 2 1 WTOB_CON_10P
MIC_AC 30
2 2

AGND_A AGND_A ER1.1 -> PR2.0 (Obi-Wan)

CN12
INTSPKR+ 1 5
31 INTSPKR+ 1 GND1
INTSPKR- 2
31 INTSPKR- 2
INTSPKL+ 3
31 INTSPKL+ INTSPKL- 3
31 INTSPKL- 4 4 GND2 6

WTOB_CON_4P

+3V Q69 +3V_BT

SI2305DS

2 3

3 D
2

G
1

1
C601 C598

11
3 0.1UF 0.1UF 3

2
R608 1 2 0Ohm
45 BTLED#/PWRCL#

ER1.1 -> PR2.0

L27
INT_MIC L26 120Ohm/100Mhz
32 INT_MIC 2 1
2 1 +3VS +3V_BT +3VS
4
120Ohm/100Mhz 4
1

1
C225 L82 80Ohm/100Mhz
@2 CN9 R914 R915 R916 R917
+5V 1 1
470PF/50V 3
R259 0Ohm TP116 NC1 10KOhm 10KOhm 10KOhm 10KOhm
2

1 SPKL-
1 @ 2 2 Q121
SPKL+

2
4 NC2
6 1 CH_CLK_BT
27 USBP6-_5 40 CH_CLK_WLAN D1 S1
AGND_A AGND_A
3

fpc_1x2p
L28 5 2
G2 G1
27 USBP6+_5
200Ohm @
CH_DATA_BT
2

4 S2 D2 3 CH_DATA_WLAN 40

SI1902DL
R258 0Ohm
1 @ 2 ER1.1 -> PR2.0 (Obi-Wan)

ER1.1 -> PR2.0 (Obi-Wan)

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan MIC PRE AMP & MIC JACK & ExtCN
LIBRARY DATE :
2.0 SHEET 33 OF 61
A B C D E
A B C D E

*As close as possible to VCC_PCI pins.

+3V
+3VS +3VS_CB
+1.8V
1 2

1
L91 0Ohm +

1
+ C771 C338 C772 C819

1
1 2 C745 C773 C753 C754
+3V

2
L93 0Ohm @ 0.01UF 0.01UF 0.01UF 10U/16V_TAN
1 1
R781 10U/16V_TAN 0.01UF 0.01UF 0.01UF

2
R778 0Ohm

2
1 2 0Ohm

1
1 2
R772 0Ohm @ 1 2
R393 0Ohm U18B
2

1
R769 C324 C323 C314 C315 + C766 C765 W3 F5
C774 C750 VCC_PCI3V_1 VCC_3V_1
R11 VCC_PCI3V_2 VCC_3V_3 J19
100KOhm 0.01UF 0.01UF 0.47U 0.47U 0.01UF 0.01UF R12 K19
10U/16V_TAN 0.1U VCC_PCI3V_3 VCC_3V_4

2
1

2
R6 VCC_RIN_1 VCC_3V_2 G5
E13 VCC_RIN_2
L1 VCC_ROUT_1
*As close as possible to VCC_ROUT pins. E14 VCC_ROUT_2 VCC_MD3V A4
R7 REGEN#
PCI Bus
AD[31..0] J1
27,38,40 AD[31..0] GND1
GND2 J5
AD31 M2 K5
AD30 AD31 GND3
M1 AD30 GND4 E9
2 AD29 N5 R10 2
AD28 AD29 GND5
N4 AD28 GND6 T10
PowerOnReset for VccCore AD27 N2 V10
AD26 AD27 GND7
N1 AD26 GND8 W10
AD25 P5 L15
AD24 AD25 GND9
P4 AD24 GND10 M19
AD23 R4 A9
AD22 AD23 AGND_1 +3V
R2 AD22 AGND_2 B9
AD21 R1 D9
AD20 AD21 AGND_3
T2 AD20 AGND_4 D14
+3V AD19 T1 A15
AD19 AGND_5

2
AD18 U2 B15 +3V
AD17 AD18 AGND_6 R387
U1 AD17
2

AD16 V1 F4
R404 AD15 AD16 TEST 10KOhm
T7 AD15

2
AD14 V7
100KOhm AD13 AD14 R386

1
W7 AD13
C355 AD12 R8
GRESET# AD11 AD12 100KOhm @
1

2 1 T8 AD11
AD10 V8 F2
AD9 AD10 HWSPND# CB_SUSP# 37

1
1UF/10V W8 AD9
AD8 R9 F1
AD7 AD8 SPKROUT SPKRCB 30
V9 AD7

2
AD6 W9
AD5 AD6 R385
T11 AD5
AD4 V11
3 AD3 AD4 100KOhm 3
W11 AD3
PCI Bus R394 0Ohm AD2 T12
CB_PCIRSTNS# AD1 AD2 TP100

1
1 2 V12 AD1 UDIO5 G1 1
AD0 W12 AD0
27,38,40 PAR_3 V6 PAR UDIO4 H5 UDIO4/SDA 36
27,38,40 C/BE3#_3 P2 C/BE3#
27,38,40 C/BE2#_3 W2 C/BE2# UDIO3 H4 UDIO3/SCL 36
27,38,40 C/BE1#_3 W6 C/BE1#
T9 H2 1 TP101
27,38,40 C/BE0#_3 C/BE0# UDIO2
CB_IDSEL P1 IDSEL TP102
UDIO1 H1 1
M4 R391 0Ohm
27 REQ2#_3 REQ#
27 GNT2#_3 M5 GNT# UDIO0/SRIRQ# J4 1 2 INT_SERIRQ 26,27,44,45
27,38,40 FRAME#_3 V3 FRAME#
27,38,40 IRDY#_3 V4 IRDY#
27,38,40 TRDY#_3 W4 TRDY#
27,38,40 DEVSEL#_3 T5 DEVSEL# PCI Bus
27,38,40 STOP#_3 V5 STOP# INTA# J2 INT_PIRQF# 27
27,38,40 PERR#_3 W5 PERR#
27,38,40 SERR#_3 T6 SERR# INTB# K4 INT_PIRQG# 27
R392 0Ohm
G2 GBRST# INTC# K2 1 2 INT_PIRQE# 27,38
SHIELD GND [3] L4 PCIRST#
6 CLK_CBPCI K1 PCICLK NC1 L2

1 2 CLKRUN# L5
4 26,27,38,40,44,45 CLKRUN#_3 CLKRUN# 4
G4 RI_OUT#/PME#
R395 0Ohm
2

R388 CoreLogic
100KOhm CLOCKRUN# R383
27,38,40 PME# 1 2
1

0Ohm
2

R379
R415 0Ohm +3V
1 2 CB_PCIRSTNS# 0Ohm @ R5C841
27,38,40 PCIRST#_ICH
2
1

1 2 R377
5,29,38,45 PCIRSTNS#_3
R416 0Ohm @
10KOhm @
1

RI_OUT#
RIC#_3 37
R389
5 AD19 1 2 CB_IDSEL 5

100Ohm

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan CardBus RICOH R5C841/PCI_B LIBRARY DATE :
2.0 SHEET 34 OF 61

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A B C D E

U18A

1 1
[1] NOT INSTALLED
CADR25 J18 AD19/A25 37
[2] AS CLOSE AS POSSIBLE TO DEVICE TERMINALS. CADR24 J15 AD17/A24 37
C1 NC2 CADR23 K16 CFRAME#/A23 37
[3] CLK LINES : SHIELDED BY GND. (RECOMMENDED) CADR22 L16 CTRDY#/A22 37
CADR21 L18 CDEVSEL#/A21 37
[4] R5C851 and R5C821 OPTIONS. (For R5C841 or R5C811, D1 NC3 CADR20 M16 CSTOP#/A20 37
N19 CBLOCK#/A19 5,37
these parts are NOT installed.) CADR19
N16
CADR18 RFU/A18 5,37
E1 P16 R355 [2] SHIELD GND[3]
NC4 CADR17 AD16/A17 37
[5] R5C851 and R5C841 OPTIONS. (For R5C821 or R5C811, CADR16 L19 1 2 CCLK/A16 37
K15 CIRDY#/A15 37
these parts are NOT installed.) C2
CADR15
N18 0Ohm *CLOCK LINE
NC5 CADR14 CPERR#/A14 5,37
CADR13 N15 CPAR/A13 37 FOR CARDBUS
CADR12 K18 CBE2#/A12 37
D2 R18 MODE
NC6 CADR11 AD12/A11 37
CADR10 U19 AD9/A10 37
CADR9 R19 AD14/A9 37
E2 NC7 CADR8 P15 CBE1#/A8 37
MDIO01--> MS Card Detect MDIO02--> xDCE# CADR7 J16 AD18/A7 37
CADR6 H15 AD20/A6 37
MDIO03--> SD Write Protect MDIO05--> SD Power Control 1 / xDWP E4 NC8 CADR5 H18 AD21/A5 37
CADR4 G15 AD22/A4 37
MDIO04--> SD Card Power0 Control/ MDIO06--> xD/MS/SD LED Control CADR3 G18 AD23/A3 37
CADR2 F15 AD24/A2 37
2 MS Power Control MDIO14--> xD Data CADR1 F18 AD25/A1 37 2
CADR0 E16 AD26/A0 37
MDIO07--> SD External Clock/ MDIO15--> xD Data
CDATA15 U18 AD8/D15 37
MS External Clock MDIO16--> xD Data CDATA14 W18 RFU/D14 5,37
CDATA13 V17 AD6/D13 37
MDIO08--> SD Command/MS Bus State MDIO17--> xD Data CDATA12 V16 AD4/D12 37
CDATA11 V15 AD2/D11 37
MDIO09--> SD Clock/MS Clock MDIO18--> xD CLE CDATA10 B19 AD31/D10 37
CDATA9 C18 AD30/D9 37
MDIO10--> SD Data 0/MS Data 0 MDIO19--> xD ALE CDATA8 D18 AD28/D8 37
CDATA7 W17 AD7/D7 37
MDIO11--> SD Data 1/MS Data 1 CDATA6 W16 AD5/D6 37
CDATA5 W15 AD3/D5 37
MDIO12--> SD Data 2/MS Data 2 CDATA4 T15 AD1/D4 37
CDATA3 R14 AD0/D3 37
MDIO13--> SD Data 3/MS Data 3 CDATA2 C19 RFU/D2 5,37 Layout of USB2.0(480MHz) signals (USBDP / USBDM / IORD# /
D19 AD29/D1 37
CDATA1
E19
IOWR#) - RECOMMENDED
CDATA0 AD27/D0 37
- The wire of USB signals should be designed on outside
MDIO19/XDALE E8 T19
layers of PCB.
37 MDIO19/XDALE MDIO19 OE# AD11/OE# 37
MDIO18/XDCLE WE# M15 CGNT#/WE# 37 - It is better with no via-hole and short wire for USB signals.
37 MDIO18/XDCLE D8 MDIO18 CE2# T18 AD10/CE2# 37
CE1# V19 CBE0#/CE1# 37 * Please refer to HighSpeed USB Platform Design
F16 CBE3#/REG# 37
3 MDIO17/XDDA7 B8
REG#
H19
Guide lines Rev 1.0 (INTEL) . 3
37 MDIO17/XDDA7 MDIO16/XDDA6 MDIO17 RESET CRST#/RESET 37
37 MDIO16/XDDA6 A8 MDIO16 WAIT# G16 CSERR#/WAIT# 5,37
MDIO15/XDDA5 E7 A18
37 MDIO15/XDDA5 MDIO14/XDDA4 MDIO15 WP/IOIS16# CLKRUN#/IOIS16# 5,37
37 MDIO14/XDDA4 D7 MDIO14 RDY/IREQ# M18 CINT#/IREQ# 37
37 MDIO13/SDDA3/MSDA3/XDDA3 B7 MDIO13 BVD2 F19 CAUDIO/SPKR_IN#/BVD2 5,37
37 MDIO12/SDDA2/MSDA2/XDDA2 A7 MDIO12 BVD1 E18 CSTSCHG/STSCHG#/BVD1 5,37
37 MDIO11/SDDA1/MSDA1/XDDA1 E6 MDIO11 VS2# H16 CVS2 37
37 MDIO10/SDDA0/MSDA0/XDDA0 D6 MDIO10 VS1# R16 CVS1 37
SHIELD GND R369[2] D15
CD2# CCD2# 37
37 MDIO09/SDCLK/MSCLK/XDDRE# 1 2 B6 MDIO09 CD1# T14 CCD1# 5,37
INPACK# G19 CREQ#/INPACK# 37
0Ohm A6
37 MDIO08/SDCMD/MSBS/XDDWE# MDIO08
DIFFERENTIAL IMPEDANCE : 90 ohms SHIELD GND
D5 MDIO07 IORD# P18 AD13/IORD# 37
P19 To PC Card I/F Ricoh suggests USBDP/USBDM & IORD#/IOWR#
MDIO06 IOWR# AD15/IOWR# 37
TP99 1 B5 - Layout on top or bottom layer
MDIO06
- No via-hole
MDIO05/XDDWP A5 V14
37 MDIO05/XDDWP MDIO05 USBDP USBP5+_5 27 - 90 ohm impedance control required
MDIO04/SDPC/MSPC USBDM W14 USBP5-_5 27 From Host
37 MDIO04/SDPC/MSPC B4 MDIO04
DIFFERENTIAL IMPEDANCE : 90 ohms SHIELD GND
MDIO03/SDWP B3 +3V
37 MDIO03/SDWP MDIO03 R733
MDIO02/XDDCE# A3 1 2
37 MDIO02/XDDCE# MDIO02
MDIO01/MSCD A2 W13 100KOhm
4 37 MDIO01/MSCD MDIO01 VPPEN1 BVPPEN1 37 4
VPPEN0 V13 BVPPEN0 37
MDIO00/SDCD B1 T13
37 MDIO00/SDCD MDIO00 VCC3EN# BVCC3EN# 37
VCC5EN# R13 BVCC5EN# 37
R732
1 2

100KOhm @

SHIELD GND [3] R5C841

2

R372

0Ohm
1

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan CardBus RICOH R5C841/PCI_A LIBRARY DATE :
2.0 SHEET 35 OF 61
A B C D E
A B C D E

+3V

R753 0Ohm L92

1 2 1 2
[2] [2] [2] [2] [2]

1
U18C + 80Ohm/100Mhz
C770 C756 C763 C755 C762
1 1
22U/10V 0.1U 1000PF 0.1U 1000PF

2
2
D11 CPS AVCC_PHY_1 E10
AVCC_PHY_2 E11
AVCC_PHY_3 A17
AS CLOSE AS POSSIBLE TO R5C841 AVCC_PHY_4 B17 AS CLOSE AS POSSIBLE TO
Shield GND AS CLOSE AS POSSIBLE TO R5C841 1394 CONNECTOR.
C309 10PF/25V C342
2 1 [2] TPBIAS0 D12 2 1
[2][2]

2
0.33U 1 2
R374 R373 C335 R708 0Ohm
X6
1

A16 XI 2 1 1 2
[2] 56Ohm 56Ohm R703 0Ohm
0.01UF/16V
24.576Mhz L88
2

1
A13 TPB0- 4 5 TPB0-_1
C313 10PF/25V TPBN0
2 1 B16 B13 TPB0+ 3 6 TPB0+_1 CN27
XO TPBP0
[2] Choke
1 1 P_GND1 5
TPA0-_1
Common
2 7 2 2
3 3 P_GND2 6
2 1 8 TPA0+_1 4 2
TPA0- 4
TPAN0 A12
[2] IEEE_1394_4P
2 1 A14 B12 TPA0+ SBCB656045T_181 @
C746 0.01UF FIL0 TPAP0
1 2
[2][2] C330 R713 0Ohm

2
[2] 2 1 1 2
1 2 B14 R368 R365 R709 0Ohm
R366 10KOhm REXT 270PF/50V
56Ohm 56Ohm
[2] R364

1
2 1 D13 VREF 1 2
C744 0.01UF
Shield GND 5.1KOhm

E12 NC9
Circuit area : As small as possible.

3 D10 1 TP50 3
TPBIAS1
*TPA/TPA#,TPB/TPB# pair trace : As close as possible.
*TPA/TPA#,TPB/TPB# pair trace : Same length electrically.
*TPBIAS traces from pin to the filiter capacitors : Short and wide.
*Termination resistor for TPA+/- TPB+/- : As close as possible
to its cable driver (device pin out).
TPBN1 A11

TPBP1 B11 [1] NOT INSTALLED

[2] AS CLOSE AS POSSIBLE TO DEVICE TERMINALS.

A10 1 TP49
TPAN1
B10 1 TP98
TPAP1

+3V

Serial EEPROM

2
4
C371 0.1uF/10V 4
R406 R405 2 1

10KOhm 10KOhm U27

8 VCC A0 1

1
7 WP A1 2
34 UDIO3/SCL 6 SCL A2 3
34 UDIO4/SDA 5 SDA GND 4

AT24C02N

R5C841

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan CardBus RICOH R5C841/PCI_C LIBRARY DATE :
2.0 SHEET 36 OF 61

WWW.AliSaler.Com A B C D E
A B C D E

Power Switch SD/MMC/MS/MS-PRO Card Reader Socket MDIO00--> SD Card Detect

[3] CLK LINE : SHIELDED BY GND. (RECOMMENDED) [5] R5C841 OPTIONS.
MDIO01--> MS Card Detect
+12V +VPPCB +VCCCB +5V +3V MDIO03--> SD Write Protect
MDIO04--> SD Card Power0 Control/
SR 1.0 -> ER 1.1
MS Power Control

1
C740 C741 C760 C764 C761
1 +VCCCA 1
R730 +3V MDIO08--> SD Command/MS Bus State
0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V
@ 10KOhm MDIO09--> SD Clock/MS Clock

2
@
MDIO10--> SD Data 0/MS Data 0

1
U55

1
8 9 C350 C777 C376 C360 C377 MDIO11--> SD Data 1/MS Data 1
VPPOUT VCCOUT1
7 NC2 NC3 10
6 11 0.01UF/16V 0.01UF/16V 1UF/10V 0.01UF/16V 0.01UF/16V MDIO12--> SD Data 2/MS Data 2
NC1 VCC3IN

2
5 FLG VCCOUT2 12
R731 1 2 0Ohm 4 13 MDIO13--> SD Data 3/MS Data 3
35 BVPPEN1 EN1 VCC5IN1
R728 1 2 0Ohm 3 14 +3V
35 BVPPEN0 EN0 VCCOUT3
R744 1 2 10KOhm 2 15
35 BVCC3EN# VCC3_EN VCC5IN2
1 VCC5_EN GND 16

2
R5531V002 R727
ER 1.1 -> PR 2.0

2
1 2 10KOhm +3V
R729 0Ohm @ Q84 R398 SR 1.0 -> ER 1.1
2N7002

1
3 2 470KOhm D63 1SS355

2 S
D
BVCC5EN# 35

1
MS_CD

3
2 1
R906

1
G
D43 D14 1SS355

1 1
+3V 1 2 10KOhm XD_PWR_EN 2 1 MDIO01/MSCD
CBDEBUGEN# 5 MDIO01/MSCD 35
2 CN31 D15 1SS355 2
RB751V_40 SD_CD SR 1.0 -> ER 1.1

2
1 MS_GND1 XD_CD 23 2 1
2

MDIO08/SDCMD/MSBS/XDDWE# 2 24
35 MDIO08/SDCMD/MSBS/XDDWE# MDIO11/SDDA1/MSDA1/XDDA1 MS_BS XD_GND1 MDIO03/SDWP
R860 3 25
35 MDIO11/SDDA1/MSDA1/XDDA1 MDIO10/SDDA0/MSDA0/XDDA0 MS_DATA1 XD_R/B MDIO09/SDCLK/MSCLK/XDDRE# MDIO03/SDWP 35
+3V +3VALWAYS 4 26
35 MDIO10/SDDA0/MSDA0/XDDA0 MDIO12/SDDA2/MSDA2/XDDA2 MS_DATA0 XD_RE MDIO02/XDDCE#
10KOhm D52 R862 0Ohm 5 27
35 MDIO12/SDDA2/MSDA2/XDDA2 MS_CD MS_DATA2 XD_CE MDIO18/XDCLE MDIO02/XDDCE# 35
1 1 2 SUSB#_3 26,29,38,47,55,56 6 MS_INS XD_CLE 28 MDIO18/XDCLE 35

2
CB_SUSP# R863 0Ohm MDIO13/SDDA3/MSDA3/XDDA3 MDIO19/XDALE
1

34 CB_SUSP# 3 35 MDIO13/SDDA3/MSDA3/XDDA3 7 MS_DATA3 XD_ALE 29 MDIO19/XDALE 35

2 1 2 R433 R442 MDIO09/SDCLK/MSCLK/XDDRE# 8 30 MDIO08/SDCMD/MSBS/XDDWE#
CB_SD# 26 35 MDIO09/SDCLK/MSCLK/XDDRE# MS_SCLK XD_WE MDIO05/XDDWP
+VCCCA 9 MS_VCC XD_WP 31 MDIO05/XDDWP 35
RB717F 10KOhm 10KOhm 10 32
SDCDAT2 MS_GND2 XD_GND2 MDIO10/SDDA0/MSDA0/XDDA0
11 SD_DAT2 XD_D0 33
MDIO13/SDDA3/MSDA3/XDDA3 MDIO11/SDDA1/MSDA1/XDDA1

1
12 SD_DAT3 XD_D1 34
RIA# 26 MDIO08/SDCMD/MSBS/XDDWE# MDIO12/SDDA2/MSDA2/XDDA2

S 2

D
2 3 13 SD_CMD XD_D2 35
MDIO13/SDDA3/MSDA3/XDDA3

3
34 RIC#_3 14 36
SD_GND1 XD_D3 MDIO14/XDDA4
15 37

G
+VCCCA SD_VCC XD_D4 MDIO15/XDDA5 MDIO14/XDDA4 35

1
Q48 16 38
SD_CLK XD_D5 MDIO16/XDDA6 MDIO15/XDDA5 35
2N7002

1
17 SD_GND2 XD_D6 39 MDIO16/XDDA6 35
18 40 MDIO17/XDDA7
+3V MDIO10/SDDA0/MSDA0/XDDA0 NC1 XD_D7 MDIO17/XDDA7 35
SR 1.0 -> ER 1.1 19 41
SDCDAT1 SD_DAT0 XD_VCC +VCCCD
20 SD_DAT1 NC2 42
MDIO00/SDCD 21 43 MDIO03/SDWP
35 MDIO00/SDCD SD_CD_SW SD_WP_SW
22 SD_CD_COM SD_WP_COM 44
SR 1.0 -> ER 1.1
CardBus Connector

1
45 NP_NC1 NP_NC2 46

1
R900 C352 C780 R788 47 48 R869 +5V
3 GND1 GND2 3
150KOhm 270PF/50V 270PF/50V 0Ohm CARD_READER_44P 0Ohm
@

2
70

72

74

76

CN13

2
1

1
1 35
SIDE2

NP_NC2

NP_NC4

P_GND2

1 35

1
2 36 R791 R870 C337 C351 C346
35 AD0/D3 2 36 CCD1# 5,35
35 AD1/D4 3 3 37 37 AD2/D11 35
1

4 38 0Ohm 0Ohm 1UF/10V 0.01UF/16V 0.01UF/16V

35 AD3/D5 4 38 AD4/D12 35
C297 SR 1.0 -> ER 1.1

2
35 AD5/D6 5 5 39 39 AD6/D13 35

2
35 AD7/D7 6 6 40 40 RFU/D14 5,35 270PF/50V
2

35 CBE0#/CE1# 7 7 41 41 AD8/D15 35
35 AD9/A10 8 8 42 42 AD10/CE2# 35
35 AD11/OE# 9 9 43 43 CVS1 35
35 AD12/A11 10 10 44 44 AD13/IORD# 35
35 AD14/A9 11 11 45 45 AD15/IOWR# 35
12 46 +3V SR 1.0 -> ER 1.1
35 CBE1#/A8 12 46 AD16/A17 35
35 CPAR/A13 13 13 47 47 RFU/A18 5,35
14 48 Q43
5,35 CPERR#/A14 14 48 CBLOCK#/A19 5,35
15 49 IRLML5103TR
35 CGNT#/WE# 15 49 CSTOP#/A20 35 +VCCCB
35 CINT#/IREQ# 16 16 50 50 CDEVSEL#/A21 35
17 51 2 3

3 D
+VCCCB 17 51 +VCCCB +VCCCA
SR 1.0 -> ER 1.1

2
18 18 52 52 +VPPCB
CCLK_A16 +VPPCB
1

19 53

G
19 53 CTRDY#/A22 35

2
20 54 R356

11
35 CIRDY#/A15 20 54 CFRAME#/A23 35

1
21 55 C357
35 CBE2#/A12 21 55 AD17/A24 35
22 56 10KOhm N/A +5V R400
4 35 AD18/A7 22 56 AD19/A25 35 4
23 57 10KOhm 0.1uF/10V
35 AD20/A6 23 57 CVS2 35
U70
2

2
35 AD21/A5 24 24 58 58 CRST#/RESET 35 MDIO00/SDCD

1
35 AD22/A4 25 25 59 59 CSERR#/WAIT# 5,35 1 A Vcc 5
26 60 SD_CD 2 MDIO04/SDPC/MSPC
35 AD23/A3 26 60 CREQ#/INPACK# 35 B MS_CD 35 MDIO04/SDPC/MSPC Please as
35 AD24/A2 27 27 61 61 CBE3#/REG# 35 3 GND C 4
35 AD25/A1 28 28 62 62 CAUDIO/SPKR_IN#/BVD2 5,35 close to card
35 AD26/A0 29 29 63 63 CSTSCHG/STSCHG#/BVD1 5,35 SN74LVC1G66 reader socket
1

30 64 C301 +5V +3V

35 AD27/D0 30 64 AD28/D8 35 as possible.
35 AD29/D1 31 31 65 65 AD30/D9 35
P_GND1
NP_NC1

NP_NC3

32 66 0.01UF/16V U61 Q44

5,35 RFU/D2 32 66 AD31/D10 35
SIDE1

MDIO00/SDCD 1 IRLML5103TR
2

5,35 CLKRUN#/IOIS16# 33 33 67 67 CCD2# 35 OE# VCC 5

34 34 68 68
SDCDAT1 2 2 3

3 D
A +VCCCD
1

MDIO11/SDDA1/MSDA1/XDDA1

2
3 4
69

71

73

75

C304 GND B

G
2
SW_SN74CBT1G125DBV

11
270PF/50V

1
R408 C362 C379
2

+5V
BTOB_CON_68P 10KOhm 0.01UF/16V 0.1uF/10V
U60

2
+VCCCB +VPPCB MDIO00/SDCD 1

1
OE# VCC 5
CCLK_A16 XD_PWR_EN
35 CCLK/A16 SDCDAT2 2 Please as close
A MDIO12/SDDA2/MSDA2/XDDA2
3 GND B 4 to card reader
1

C356 C372 C363 C358 socket as

5 SW_SN74CBT1G125DBV 5
5PF @ 0.01UF/16V 0.01UF/16V 0.1UF possible.
2

To correct the problem when MS Duo To correct the problem when MS Duo
adaptor is in use. adaptor is in use.

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan Cardbus & CardReader & PwrSw LIBRARY DATE :
2.0 SHEET 37 OF 61
A B C D E
A B C D E

+3V +3V_LAN AD[0:31]

1 27,34,40 AD[0:31] 1
L6 +5VS
1 2
@

2
+3VALWAYS 80Ohm/100Mhz +3V_LAN
+

1
L5 R24
1 2 CB1 C13 C11 C15 C7 C16 CT2
22UF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V 4.7U/16V 1KOhm

1
80Ohm/100Mhz

1
R5 ISO#

1
1
R59 C6

2
5.6K
U4 10KOhm 0.1uF/10V R25
EECS

2
1 CS VCC 8
EESK 15KOhm

2
2 SK DC 7
EEDI 3 6
EEDO DI ORG

1
4 DO GND 5

AT93C46

2 2
ER1.1 -> PR2.0 (Obi-Wan)

AVDDL

R23 5.76KOhm
2 1 LAN_RSET X1_LAN +3V_LAN AVDDL
X2_LAN L2 20 mil
PME# 27,34,40 1 2
CTRL25
RDN EECS 120Ohm/100Mhz
39 RDN

1
RDP EESK C5 C9
39 RDP EEDI
TDN
39 TDN TDP EEDO +3V_LAN DVDD 0.1uF/10V 0.1uF/10V
ISO# 39 TDP

2
2 1
R26 0Ohm L1
ISOLATEB 2 1 1 2
26,29,37,55,56 SUSB#_3
R27 0Ohm @
120Ohm/100Mhz
1

C26

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
0.1uF/10V U1
2

ISOLATEB

EECS
AVDD

LWAKE

PMEB

EESK

ROMCS/OEB
NC

EEDI
EEDO
GND_7
TXD+
TXD-
AVDD_2

RXIN+

RTT3
RXIN-
GND_6
RTSET

GND_5
X1
X2
AVDD_1
AVDD25_1

VCTRL
76 50 R28 1 2 0Ohm
LED2 CLKRUNB CLKRUN#_3 26,27,34,40,44,45
77 49 CTRL25
3 LED1 VDD_4 3
78 LED0 VDD25_1 48
79 47 AD0 Q2

1 B
INTBB AD0 AD1 +3V_LAN HM772 @ DVDD
27,34 INT_PIRQE# 80 INTAB AD1 46
AD2
27,34,40 PCIRST#_ICH 1
R12
2
0Ohm
81 RTSB AD2 45 20 mil
27 GNT1#_3 82 GNTB GND_4 44
AD3

3
E

C
2
5,29,34,45 PCIRSTNS#_3 1 2 27 REQ1#_3 83 REQB AD3 43
R13 0Ohm @ 84 42 AD4
27,34,40 C/BE3#_3 CBE3B AD4

1
AD31 85 41 AD5 C4 C12 C25 C8 C24
AD30 AD31 AD5 AD6
86 AD30 AD6 40
AD29 87 39 AD7 10uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V
AD29 AD7

2
88 GND_8 CBE0B 38 C/BE0#_3 27,34,40
AD28 89 37
AD28 VDD_3 AD8
90 VDD_5 AD8 36
AD27 91 35 AD9
AD26 AD27 AD9 AD10
92 AD26 AD10 34
AD25 93 33 AD11
AD25 AD11 AD12
94 VDD25_2 AD12 32
95 VDD_6 GND_3 31
AD24 96 30 AD13
AD24 AD13 AD14
6 CLK_LANPCI 97 PCICLK AD14 29
AD20 AD15
AC_DOUT
AC_SYNC
AC_RSTB

DEVSELB
2 1 98 28

FRAMEB
IDSEL AD15
AC_BCK

R3 33Ohm
AC_DIN

99 27

PERRB
TRDYB

STOPB
GND_1

GND_2
CBE2B
VDD_1

VDD_2
C/BE1#_3 27,34,40

IRDYB
GPIO1 CBE1B
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
100 26

PAR
GPIO0 SERRB SERR#_3 27,34,40
X3
1

C10 RTL8101L X1_LAN 1 2 X2_LAN

4 4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9

10P 25Mhz
2

1
C21 C20

27pF 27pF

2
PERR#_3 27,34,40
PAR_3 27,34,40
STOP#_3 27,34,40
DEVSEL#_3 27,34,40
TRDY#_3 27,34,40
IRDY#_3 27,34,40
FRAME#_3 27,34,40
AD16 C/BE2#_3 27,34,40
AD17
AD18
AD19
AD20
AD21
AD22
AD23

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan LAN (RealTek-RTL8101L) LIBRARY DATE :
2.0 SHEET 38 OF 61

WWW.AliSaler.Com A B C D E
A B C D E

Transformer
MDC Connector
+3V_LAN
1 1
FOR MDC

2
R538

0Ohm @
U39

1
5 NC2 NC4 13
4 NC1 NC3 12

TDN 8 9 LAN_TX- +3VALWAYS +3V

38 TDN TD- TX-
TDP 7 10 LAN_TX+
38 TDP TD+ TX+
6 PTCT/TDCTTXCT 11

1
3 RDCT RXCT 14

1
RDN 2 15 LAN_RX- R51 C33 R52 C34
38 RDN RD- RX-
RDP LAN_RX+ CN1

13
15
17
19
38 RDP 1 RD+ RX+ 16
0Ohm @ 0.1uF/10V @ 0Ohm 0.1uF/10V

1
C480 LF8423

2
GND1
GND3
GND5
NP_NC2 NP_NC1

2
1 1 2 2
0.1uF/10V 3 4
26,30 ACZ_SDOUT 3 4
1

2
5 5 6 6

1
R541 R542 R535 R536 7 8 SR 1.0 -> ER 1.1
26,30 ACZ_SYNC 7 8
2 R537 R540 1 2 9 10 2
26 ACZ_SDIN1 9 10
1

GND2
GND4
GND6
49.9Ohm 49.9Ohm 49.9Ohm 49.9Ohm C481 R15 33Ohm 11 12
26,30,31 ACZ_RST# 11 12 ACZ_BCLK_MDC 26
75Ohm 75Ohm
0.1uF/10V @
2

14
16
18
20
2

C482 C479 BTOB_CON_12P

0.01UF/10V 0.01UF/10V EMI

LAN_GND
1

A seperate float plane is

needed at least 2mm
between Gnd

3 3

RJ11/RJ45 Connector
CN2
3 SIDE1 1 1 1 2
L4 0Ohm
RING
4 2 1 2 TIP
SIDE2 2 L3 0Ohm
fpc_con_2p
LAN_TX+ 2 1 LN1A LAN_TX+_CN
LAN_TX- 0Ohm LAN_TX-_CN
4 3 LN1B
LAN_RX+ 0Ohm LAN_RX+_CN
6 5 LN1C
LAN_RX- 0Ohm
8 7 LN1D
0Ohm
LAN_RX-_CN
COMMON MODE CHOKE
P/N 09-091470000
1

R543 R539

75Ohm 75Ohm

LAN_GND
2

4 4
CN17
12 12 SIDE2 18
11 16 CHASSIS_GND
11 P_GND2
10 10 NP_NC2 14
1

C3 9 9

1
8 8
1500P 7 R2
7
2

6 6
5 0Ohm
CHASSIS_GND 5
4 4

2
3 3 NP_NC1 13
2 2 P_GND1 15

1
1 1 SIDE1 17
R35
MODULAR_JACK_12P
0Ohm

2
ER1.1 -> PR2.0 (Obi-Wan)

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan LAN IO & MDC LIBRARY DATE :
2.0 SHEET 39 OF 61
A B C D E
A B C D E

1 1

27,34,38 AD[0:31] AD[0:31]

+3VS

+3V

125
126
127
128
CN7
2 ER1.1 -> PR2.0 (Obi-Wan)
ER1.1 -> PR2.0 (Obi-Wan) 1 2

HOLD1
HOLD2
HOLD3
HOLD4
R172 TIP RING
3 LAN REV1 LAN REV8 4
5 LAN REV2 LAN REV9 6
10KOhm R183 0Ohm 7 8 R182 0Ohm
LAN REV3 LAN REV10
2

WLAN_LED 1 2 R177 0Ohm 9 10 R179 0Ohm 2 1

LAN REV4 LAN REV11 WLAN_LED 45
R184 @ 2
1

46 WIRELESS_LAN_LED1 1 11 LAN REV5 LAN_REV12 12 1 2 WIRELESS_LAN_LED 46

2 WIRELESS_LAN_ON/OFF# 1 2 13 14 @ 2
10KOhm R178 0Ohm LAN REV6 LAN_REV13
15 LAN REV7 LAN_REV14 16
27 INT_PIRQD# 17 INTB# VCC5_2 18 +5VS
3

3
1

D 19 VCC3_1 INTA# 20 INT_PIRQC# 27

21 REV1 REV3 22
Q33 23 24
GND1 +3.3VAUX1 +3V
45 802WLAN_ON# 11 6 CLK_MINIPCI 25 CLK RST# 26 PCIRST#_ICH 27,34,38
G 2N7002 27 28
2 S GND2 VCC3_5
27 REQ3#_3 29 REQ# GNT# 30 GNT3#_3 27
2

31 VCC3_2 GND9 32
AD31 33 34 R180 1 2 0Ohm
AD29 AD31 PME# PME# 27,34,38
35 AD29 REV4 36 CH_CLK_WLAN 33
37 38 AD30
AD27 GND3 AD30
39 AD27 VCC3_6 40
AD25 41 42 AD28
AD25 AD28 AD26
33 CH_DATA_WLAN 43 REV2 AD26 44
45 46 AD24
27,34,38 C/BE3#_3 AD23 C/BE3# AD24 AD21
47 AD23 IDSEL 48 1 2
49 50 R181 100Ohm
AD21 GND4 GND10 AD22
51 AD21 AD22 52
AD19 53 54 AD20
AD19 AD20
55 GND5 PAR 56 PAR_3 27,34,38
AD17 57 58 AD18
AD17 AD18 AD16
27,34,38 C/BE2#_3 59 C/BE2# AD16 60
27,34,38 IRDY#_3 61 IRDY# GND11 62
63 VCC3_3 FRAME# 64 FRAME#_3 27,34,38
3 65 66 3
26,27,34,38,44,45 CLKRUN#_3 CLKRUN# TRDY# TRDY#_3 27,34,38
27,34,38 SERR#_3 67 SERR# STOP# 68 STOP#_3 27,34,38
69 GND6 VCC3_7 70
27,34,38 PERR#_3 71 PERR# DEVSEL# 72 DEVSEL#_3 27,34,38
27,34,38 C/BE1#_3 73 C/BE1# GND12 74
AD14 75 76 AD15
AD14 AD15 AD13
77 GND7 AD13 78
AD12 79 80 AD11
AD10 AD12 AD11
81 AD10 GND13 82
83 84 AD9
AD8 GND8 AD09
85 AD08 C/BE0# 86 C/BE0#_3 27,34,38
AD7 87 88
AD07 VCC3_8 AD6
89 VCC3_4 AD06 90
AD5 91 92 AD4
AD05 AD04 AD2
93 REV AD02 94
AD3 95 96 AD0
+5VS AD03 AD00
97 VCC5_1 REV5 98
AD1 99 100
AD01 REV6
101 GND16 GND14 102
103 AC_SYNC M66EN 104
105 AC_SDATA_IN1 AC_SDATA_OUT 106
107 AC_BIT_CLK AC_SDATA_IN2 108
109 AC_CODEC_CLK AC_RESET# 110
111 MOD_AUDIO_MON REV7 112
113 AUDIO_GND1 GND15 114
4 115 SYS_AUDIO_OUT SYS_AUDIO_IN 116 4
117 SYS_AUDIO_OUT GND SYS_AUDIO_IN GND 118
119 AUDIO_GND AUDIO_GND2 120
121 NC MCPIACT# 122
123 +5VA +3.3VAUX2 124 +3V
MINI_PCI_124P

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan MiniPCI LIBRARY DATE :
2.0 SHEET 40 OF 61

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A B C D E

ODD Connector HDD Connector

1 1

+5VS

+5VS L65 1 2 80Ohm/100Mhz

U13
9,14,24,27,29,44,45 PLT_RST#_3 1 A VCC 5

2 B

3 GND 4 RSTIDE# +HDD_VCC

Y
NC7SZ08P5X +5VS

1
C502 C501 C511
R633 0Ohm
2 1 0.1uF/10V 0.1uF/10V 10UF/16V

2
1
2 + 2

1
CE17 C658 C660 CN20
2

RSTIDE# 1 48
R645 47U/6.3V 0.1UF 0.1UF 1 NP_NC1
2 2 NP_NC2 46
PDD7

2
3 3
4.7KOhm PDD8 4
PDD6 4
5 5
CN24 PDD9
1

51

53

6 6
PDD5 7
PDD10 7
1 2 8
NP_NC1

P_GND1

30 CD-L_A 1 2 CD-R_A 30 PDD4 8

30 CD_GND 3 3 4 4 9 9
RSTIDE# 5 6 PDD11 10
5 6 PDD8 26 PDD3 10
26 PDD7 7 7 8 8 PDD9 26 11 11
9 10 PDD12 12
26 PDD6 9 10 PDD10 26 PDD2 12
26 PDD5 11 11 12 12 PDD11 26 13 13
13 14 PDD13 14
26 PDD4 13 14 PDD12 26 PDD1 14
26 PDD3 15 15 16 16 PDD13 26 15 15
17 18 PDD14 16
26 PDD2 17 18 PDD14 26 PDD0 16
19 20 +HDD_VCC +HDD_VCC 17
26 PDD1 19 20 PDD15 26 PDD15 17
26 PDD0 21 21 22 22 PDDREQ_35 26 18 18
23 23 24 24 PDIOR#_3 26 19 19
26 PDIOW#_3 25 25 26 26 20 20

2
27 28 PDDREQ_35 21
26 PIORDY_35 27 28 PDDACK#_3 26 21
29 30 1 TP92 R574 22
26,27 IRQ14_3 29 30 DIAGNOSIS PDIOW#_3 22
31 32 1 TP76 23
26 PDA1_3 31 32 23
33 34 4.7KOhm 24
3 26 PDA0_3 33 34 PDA2_3 26 PDIOR#_3 24 3
26 PDCS1#_3 35 35 36 36 PDCS3#_3 26 25 25

1
46 PDACTIVE#_ODD 37 37 38 38 26 26
39 40 PIORDY_35 27
39 40 CSEL1 27
41 41 42 42 28 28
43 44 PDDACK#_3 29
43 44 29
P_GND2
NP_NC2

R641 10KOhm 45 46 30
45 46 R572 10KOhm IRQ14_3 30
1 2 47 47 48 48 31 31
49 49 50 50 2 1 32 32
2

PDA1_3 33
R643 DIAGNOSIS 33
34
52

54

CDROM_CON_50P PDA0_3 34
35 35
10KOhm PDA2_3 36
@ PDCS1#_3 36
37 37
PDCS3#_3
1

38 38
46 PDACTIVE#_HDD 39 39
40 40

2
41 41
R577 42 42
43 43 NP_NC3 45
0Ohm 44 47
44 NP_NC4

1
HDD_CON_44P

4 4

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan HDD & CDROM CN LIBRARY DATE :
2.0 SHEET 41 OF 61
A B C D E
A B C D E

+V1.8S_PROC_VCCA3
+V1.8S_PROC_VCCA3 3
SM BUS +V1.8S_PROC_VCCA2
+V1.8S_PROC_VCCA2 3
+V1.8S_PROC_VCCA1
+V1.8S_PROC_VCCA1 3
+V1.8S_PROC
+V1.8S_PROC 3

+VCCP +VCCP 3,4,5,6,8,9,11,12,26,28,50

1 +1.8VS +1.8VS 3,14,15,16,56,57 1

+3VALWAYS +3VALWAYS +1.5VS +1.5VS 3,9,11,16,27,28,50

+VCORE +VCORE 4,5,7,48

+3VS +5VS +3VS
+3V +3V 5,7,29,33,34,35,36,37,38,39,40,43,44,45,46,47,51,56

+5V +5V 5,9,28,29,30,31,33,37,43,45,46,47,56,57

2
+3VALWAYS +3VALWAYS 5,24,26,27,28,29,31,37,38,39,45,47,51

2
R676 R673

2
+3VS +3VS 6,7,11,14,15,16,17,22,24,25,26,27,28,29,30,33,34,40,43,44,45,47,48,51,56,57
R674
2.2KOhm R677 2.2KOhm
10KOhm +3VS_CLK +3VS_CLK 6
10KOhm
1

1
+5VS +5VS 7,9,24,28,29,30,31,38,40,41,43,45,46,47,56

1
+12V +12V 7,31,32,37,49,56 +5VS_FAN1 +5VS_FAN1 7
Q80
+2.5VS +2.5VS 9,11,13,16,28,50,57 +3V_LAN +3V_LAN 38,39

26 SMBCK_ICH 6 D1 S1 1 SMBCK_3S 6,7,22 +1.8V +1.8V 9,11,12,20,21,22,34,50,51 AVDDL AVDDL 38

+2.5VS_SYNC +2.5VS_SYNC 9,11,13,16,28,50,57 DVDD DVDD 38

5 G2 G1 2
2 +2.5VS_CRTDAC +2.5VS_CRTDAC 11 +HDD_VCC +HDD_VCC 41 2

4 S2 D2 3 SMBDA_ICH 26 +1.5VS_MPLL +1.5VS_MPLL 11 +5V_USB0 +5V_USB0 43

6,7,22 SMBDA_3S
+VCCP_GMCH +VCCP_GMCH 3,4,5,6,8,9,11,12,26,28,50 +5V_USB1 +5V_USB1 43
SI1902DL
+2.5VS_3GBG +2.5VS_3GBG 11 +5V_USB2 +5V_USB2 43

+1.5VS_3GPLL +1.5VS_3GPLL 11 +5V_USB3 +5V_USB3 43

+1.5VS_DDRDLL +1.5VS_DDRDLL 11 A/D_DOCK_IN A/D_DOCK_IN 44,52,53

+1.5VS_DLVDS +1.5VS_DLVDS 3,9,11,16,27,28,50 +5VLCM +5VLCM 45,46,52,55

+2.5VS_ALVDS +2.5VS_ALVDS 9,11,13,16,28,50,57 +1.2VSP +1.2VSP 14,16,57

+2.5VS_HV +2.5VS_HV 9,11,13,16,28,50,57 +ATI_MEM +ATI_MEM 15,16,18,19,56

+1.5VS_TVDAC +1.5VS_TVDAC 3,9,11,16,27,28,50 LVDDR LVDDR 16,57

+1.5VS_QTVDAC +1.5VS_QTVDAC 11 +ATI_VCORE +ATI_VCORE 16,57

+3VS_TVDACA +3VS_TVDACA 11

+3VS_TVDACB +3VS_TVDACB 11 POWER

3 RTC Connector +3VS_TVDACC +3VS_TVDACC 11
3

+3VO +3VO 48,49,50,56

+3VS_TVBG +3VS_TVBG 11
+5VO +5VO 48,49,50,52,56
+1.5VS_HPLL +1.5VS_HPLL 11
+3VAO +3VAO 49,51,55,56
+1.5VS_DPLLB +1.5VS_DPLLB 11
+5VAO +5VAO 49
+1.5VS_DPLLA +1.5VS_DPLLA 11
+12VO +12VO 7,31,32,37,49,56
+1.5VS_HMPLL +1.5VS_HMPLL 11
VREF5 VREF5 50,54,56
+3VALWAYS_P +RTCVCC
+VCC_GMCH_CORE +VCC_GMCH_CORE 11,12,50,51
+2.5VO +2.5VO 50
+VCC_GMCH +VCC_GMCH 11,12,50,51
+1.8VO +1.8VO 50,56
SM_VREF_DDR SM_VREF_DDR 9,20,21,22
D45 C795 1UF/10V
+1.5VO +1.5VO 50
1 2 2 1 M_VREF_DIMM1 M_VREF_DIMM1 9,20,21,22
+1.05VO +1.05VO 50
RB751V_40 +0.9VS +0.9VS 23,51
+1.5VAO +1.5VAO 51
TP106 1
TP59 +12VS +12VS 24,25,56
A/D_VIN A/D_VIN 52,53
TP104 1 LCD_+3VS LCD_+3VS 25
4 A/D_VIN_O A/D_VIN_O 52,53 4
R797 1KOhm D44 R819 180KOhm
1

LCD_VCC LCD_VCC 25
1 2 1 2 1 2 RTC_RST# 26 BAT BAT 52,53,54
AC_BAT_SYS AC_BAT_SYS 25,48,49,50,51,52,53,57
RB751V_40 +5VCHG +5VCHG 52,53
1

C793
+RTCVCC +RTCVCC 26,28
1

+2.5VREF +2.5VREF 52
CN14 0.1uF/10V JRST1
1

+1.5VALWAYS +1.5VALWAYS 28,51

2

NC1 3 BAT_S BAT_S 52,54

2

1 CLEAR_JUMP
SPKL- +5VALWAYS +5VALWAYS 28,50
SPKL+ 2 MAX1909_LDO MAX1909_LDO 53
2

NC2 4 +3VALWAYS_P +3VALWAYS_P 29,46,47,51

fpc_1x2p
+5VA +5VA 30,32,33

+5VAMP +5VAMP 31,32

+5VAMP_PVDD +5VAMP_PVDD 31

+3V_BT +3V_BT 33

+3VS_CB +3VS_CB 34

+VCCCA +VCCCA 37

+VCCCD +VCCCD 37
5 5

+VCCCB +VCCCB 37

+VPPCB +VPPCB 37

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan SM_BUS & RTC CN LIBRARY DATE :
2.0 SHEET 42 OF 61

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A B C D E

ER 1.1 -> PR 2.0

USBPWR_23 R922 1 2 0Ohm

1 1
SR 1.0 -> ER 1.1 @
+5V_USB2

+5V_USB0 +5V
U71
+5V 1 8 USBPWR_67 L36 1 2 400Ohm/100Mhz
U14 GND OUT1 l0805_h43
2 IN1 OUT2 7
1 8 USBPWR_23 L21 1 2 400Ohm/100Mhz 3 6
GND OUT1 IN2 OUT3

1
2 7 l0805_h43 4 5 1 2 +
IN1 OUT2 EN#/EN OC# USB_OC_67# 27

1
3 6 R881 0Ohm C678 C694
IN2 OUT3

1
4 5 1 2 + G547B2P1U
EN#/EN OC# USB_OC_23# 27

1
R263 0Ohm C171 C197 C840 0.1uF/10V 47UF/6.3V

1
G547B2P1U

2
0.1UF/16V
C236 0.1uF/10V 47UF/6.3V R882 0Ohm

2
@
SUSC_PWR

2
0.1UF/16V 1 2

2
R265 0Ohm CN26

2
@
1 2 SUSC_PWR R883 5 SIDE_G1 7
2

ER 1.1 -> PR 2.0 R279 0Ohm 1 VCC SIDE_G3

R262 0Ohm
@ 1 2 2 DATA0-
ER 1.1 -> PR 2.0 R225 0Ohm 3 DATA0+
0Ohm CN23

1
@ 1 2 4 GND

5 SIDE_G1 7 27 USBP4-_5 6 SIDE_G2 8

1
C259 C257
1

1 VCC SIDE_G3 SIDE_G4

2
2 DATA0- USB_CON_1X4P
27 USBP2-_5
3 DATA0+ L38 5PF @ 5PF @
1

2
2 4 GND
200Ohm 2
L19 6 8
SIDE_G2
@

3
SIDE_G4
200Ohm 27 USBP4+_5

1
C167 C161 USB_CON_1X4P
@ R278 0Ohm
4

27 USBP2+_5 3
5PF @ 5PF @ 1 2

2
1 2

R214 0Ohm

ER 1.1 -> PR 2.0

USBPWR_23 R921 1 2 0Ohm

SR 1.0 -> ER 1.1 @
+5V_USB3
+5V_USB1
+5V
+5V U72
U10 1 8 USBPWR_45 L35 1 2 400Ohm/100Mhz
USBPWR_01 L14 GND OUT1
1 GND OUT1 8 1 2 400Ohm/100Mhz 2 IN1 OUT2 7 l0805_h43
2 7 l0805_h43 3 6
IN1 OUT2 IN2 OUT3

1
3 IN2 OUT3 6 4 EN#/EN OC# 5 1 2 USB_OC_45# 27 +
1

1
4 5 1 2 + R884 0Ohm C238 C255
EN#/EN OC# USB_OC_01# 27
1

1
R131 0Ohm C122 C117 G547B2P1U
1

3 G547B2P1U C841 0.1uF/10V 47UF/6.3V 3

C103 0.1uF/10V 47UF/6.3V

2
0.1UF/16V
R885 0Ohm
2

2
0.1UF/16V @
R123 0Ohm SUSC_PWR
2

@ 1 2

2
1 2 SUSC_PWR
2

R886 CN25
R122 ER 1.1 -> PR 2.0 5 7
ER 1.1 -> PR 2.0 CN22 0Ohm R266 0Ohm
SIDE_G1

0Ohm @ 1 VCC SIDE_G3

@ 5 SIDE_G1 7 1 2 2 DATA0-
R166 0Ohm

1
1 VCC SIDE_G3
3 DATA0+
1

1 2 2 DATA0- 4 GND

3 DATA0+
27 USBP3-_5 6 SIDE_G2 8
4 GND SIDE_G4

1
6 8 C237 C231 USB_CON_1X4P
27 USBP1-_5 SIDE_G2
SIDE_G4 L31
1

C128 C134 USB_CON_1X4P 5PF @ 5PF @

L16 200Ohm

2
5PF @ 5PF @ @

3
200Ohm 27 USBP3+_5
2

@
4

27 USBP1+_5
1 2

1 2 R264 0Ohm

R167 0Ohm
4 4

+5V +3V +5VS +3VS

2
49 SUSC_PWR 56 SUSB_PWR
R462 R483 R808 R830
100Ohm 100Ohm 100Ohm 100Ohm
2

2
R508 R460
1

1
0Ohm 3 0Ohm

3
3 3 3 3
D D D D
Q54 Q57 Q89 Q95
1

1
2N7002 2N7002 2N7002 2N7002
11 11 11 11
G G G G
2 S 2 S 2 S 2 S
2

2
5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan 4*USB2.0 CN LIBRARY DATE :
2.0 SHEET 43 OF 61
A B C D E
A B C D E

TPM 1.2 Infieon

DCIN JACK
ER 1.1 -> PR 2.0

1 1
+3V +3VS
+3VS
Co-Layout

TP63

TP64

TP62

TP65
CN15 L52
U74 DCIN_VCC A/D_DOCK_IN

1
4 P_GND1 1 1 2
1 28 LPC_POWERDOWN 5 2 DCIN_GND
LPCPD# 26
NP_NC
NC1 LPCPD# 680Ohm/100Mhz
1 2 GPIO2 SERIRQ 27 INT_SERIRQ 26,27,34,45 6 P_GND 3

1
TP113 3 26 LAD0 C471 + C2 C1
NC2 LAD0 CT1
4 GND1 GND4 25
5 24 DC_PWR_JACK_3P 0.1uF/10V 1UF/50V 0.1uF/10V
VSB VDD3 LAD1 @ 5.6UF/25V C1206

2
1 6 GPIO LAD1 23
C856 12PF/50V TP114 LFRAME#

2
1 7 PP LFRAME# 22
c0402 TP115 8 21
TESTI LCLK LAD2 CLK_TPMPCI 6
2 1@ R918 1 2 4.7KOhm 9 TESTBI/BADD LAD2 20

1
@ 10 19
VDD1 VDD2
11 GND2 GND3 18
X8 12 17 LAD3

TP15

TP14
XTALI NC3 LAD3 PLT_RST#_3
1 1 13 XTALI/32k_IN LRESET# 16
3 XTALO 14 15
SIDE XTALO CLKRUN# CLKRUN#_3 26,27,34,38,40,45
2 2 CN32 2
2 DCIN_VCC
SLB9635TT 4 1
32.768KHz C852 P_GND1 1 DCIN_GND
@ 2
2
1

1
@ C853 C854 5 3
C855 NP_NC 3
2 1
0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 6
C857 12PF/50V @ @ @ @ P_GND2
2

2
c0402 DC_PWR_JACK_3P_2DC_S026_I12
@

ER1.1 -> PR2.0 (Obi-Wan)

3 3

FWH

+3VS

U36 +3VS
1 NC1 OE#(INIT#) 32 FWH_INIT# 26
2 NC2 WE#(FWH4) 31 LFRAME# 5,26,45
3 NC3 VDD2 30
4 VSS1 DQ7(RES) 29
5 IC DQ6(RES) 28

1
6 A10(FGP14) DQ5(RES) 27
7 26 C451 C617 C458 C619
6 CLK_FWHPCI R/C#(CLK) DQ4(RES)
8 25 0.1uF/10V 0.1uF/10V 10uF/10V 0.1uF/10V
VDD1 DQ3(FWH3) LAD3 5,26,45

2
9 NC4 VSS2 24
9,14,24,27,29,41,45 PLT_RST#_3 2 1 10 RST# DQ2(FWH2) 23 LAD2 5,26,45
R502 100Ohm 11 22
A9(FGP13) DQ1(FWH1) LAD1 5,26,45
12 A8(FGP12) DQ0(FWH0) 21 LAD0 5,26,45
4 13 A7(FGP11) A0(ID0) 20 4
14 A6(FGP10) A1(ID1) 19 DIS_SYSBIOS#_FWH 5
15 A5(WP#) A2(ID2) 18
26,27 FWH_WP# 2 1 16 A4(TBL#) A3(ID3) 17
RN10C
RN10D
RN10A
RN10B
R513

D19 RB751V_40 SST49LF004A

+3VS 1 2
R490 10KOhm
2
4
6
8
1

R512
10KOhm
2
10KOhm 1
10KOhm 3
10KOhm 5
10KOhm 7

2
10KOhm

5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan DCIN Jack & FWH LIBRARY DATE :
2.0 SHEET 44 OF 61

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A B C D E

+3V +3V +5VS

2 1 RN1A MOUSEDATA_5
10KOhm
+3VALWAYS BAT_IN#_OC R135 1 2 47KOhm RP1A 4 3 RN1B KBDDATA_5
10KOhm
ACIN_OC R112 1 2 47KOhm KSI1 1 10KOhm5 6 5 RN1C MOUSECLK_5
10KOhm
RP1B 10 8 7 RN1D KBDCLK_5
10KOhm
KSI0 2 10KOhm5

2
RP1C 10
R168 ANYKEY_RSM R164 1 2 47KOhm KSI3 3 10KOhm5
RP1D 10
8.2KOhm KSI2 4 10KOhm5
1 1
RP1E 10
KSI4

1
6 10KOhm5
RP1F 10 +3V
26 EXTSMI#
KSI5 7 10KOhm5
RP1G 10

3
3 Q34 KSI6 8 10KOhm5
D
2N7002 RP1H 10
KSI7 9 10KOhm5

1
11 EXTSMI_3 10 C135 C136
G
S 2

2
+3VS 0.1uF/10V 0.1uF/10V
R169
2

2
10KOhm U12

2
26,27,34,44 INT_SERIRQ 63 P87/SERIRQ R160 R161
1

6 CLK_KBCPCI 64 P86/LCLK
R115 1 2 0Ohm 65 71
9,14,24,27,29,41,44 PLT_RST#_3 P85/LRESET# VCC 10KOhm @ 10KOhm @
5,26,44 LFRAME# 66 P84/LFRAME#
5,26,44 LAD3 67 P83/LAD3

1
5,26,44 LAD2 68 P82/LAD2 VREF 72
5,26,44 LAD1 69 P81/LAD1
5,26,44 LAD0 70 P80/LAD0
31 SCROLLOCK#_3 1 TP22
P27
R162 1 2 0Ohm 35
P54,P55,P43,P50 are P26 32
33
KPNUM#_3 46
40 WLAN_LED P23 P25 KBCAP#_3 46
2 52,53 BAT_LEARN
R163 1 2 0Ohm 36 P22 wake-up event P24 34 PCIRST#_GATE 29 2
37
+3V 47 SWDJ_LED
38
P21 inputs when KBC in
29 ANYKEY_RSM P20
standby mode P17/KSO15 39 KSO15 46
P16/KOS14 40 KSO14 46
2

7 WATCHDOG 23 P42/INT0 P15/KSO13 41 KSO13 46

R118 R159 1 2 0Ohm 22 42
25,26,29 LID_RSM# P43/INT1* P14/KSO12 KSO12 46
KBDCPURST_3Q 21 43
P44/RXD P13/KSO11 KSO11 46
8.2KOhm A20GATE_3Q 20 44
P45/TXD P12/KSO10 KSO10 46
R117 0Ohm KBDSCI_3Q 19 45
P46/SCLK1 P11/KSO9 KSO9 46
2 BAT_TYPE_3S1P# R148 1 0Ohm
1

1 26,27,34,38,40,44 CLKRUN#_3 2 18 P47/SRDY1#/CLKRUN# P10/KSO8 46 KSO8 46

R144 1 2 10KOhm 47
+3V P07/KSO7 KSO7 46
3

3 R142 1 2 0Ohm 17 48
D 55 BAT_LLOW#_OC P50/INT5* P06/KSO6 KSO6 46
BAT_TYPE_3S1P# 16 49
P51/INT20 P05/KSO5 KSO5 46
Q24 R138 1 2 10KOhm 15 50
+3V 47 MSK_INSTKEY# P52/INT30/1-WIRE1 P04/KSO4 KSO4 46,47
53,54,55 BAT_SEL 11 33 BTLED#/PWRCL# 14 P53/INT40/1-WIRE2 P03/KSO3 51 KSO3 46
G 2N7002 13 52
2 S 47 SWDJ_EN P54/CNTR0* P02/KSO2 KSO2 46
R137 1 2 10KOhm 12 53
+3V 52 BAT_IN#_OC P55/CNTR1* P01/KSO1 KSO1 46
2

7 FAN_DA_PWM 11 P56/DA1/PWM01 P00/KSO0 54 KSO0 46

R100 10
25 ADJ_BL P57/DA2/PWM11
2 1 55 KSI7
55 EOC#_LED P37/KSI8 KSI7 46
1MOhm D9 1SS355 74 56 KSI6
40 802WLAN_ON# EOC#_KBC P67/AN7 P36/KSI7 KSI6 46
@ R114 470KOhm 75 57 KSI5
+3V DJ_SW_EN P66/AN6 P35/KSI6 KSI5 46,47
R113 1 2 0Ohm KSI4
1

76 P65/AN5 P34/KSI5 58 KSI4 46,47

SR 1.0 -> ER 1.1 77 59 KSI3
52 ACIN_OC P64/AN4 P33/KSI4 KSI3 46,47
R101 1 2 0Ohm 78 60 KSI2
3 46 TP_LOCK# P63/AN3 P32/KSI3 KSI2 46,47 3
R111 1 2 0Ohm 79 61 KSI1
46 WIRELESS# P62/AN2 P31/PWM10/KSI2 KSI1 46
R99 1 2 0Ohm 80 62 KSI0
46 BLUETOOTH# P61/AN1 P30/PWM00/KSI0 KSI0 46
46 POWER4_GEAR# R119 1 2 0Ohm 1 P60/AN0 X1_KBC
XIN 28
29 X2_KBC
XOUT
TP17 1 KBDCLK_5 4 P75/INT41
TP16 1 MOUSECLK_5 5 P74/INT31 P40/XCOUT 27 EXTSMI_3 R165 1MOhm @
6 26 1 TP21 1 2
46 INTCLK_Q3 P73/INT21 P41/XCIN
TP18 1 KBDDATA_5 7 P72 BTLED# 46
TP20 1 MOUSEDATA_5 8 P71
9 25 X4
46 INTDATA_Q3 P70 RESET# PCIRSTNS#_3 5,29,34,38
1 3
SCL 2 24 GND
SDA P77/SCL CNVSS
3 P76/SDA VSS 30

1
C149 8MHZ C148

2
AVSS 73
+3V
M38857 20pF/50V 20pF/50V
@ @

2
+5V
2

+5VS
R157 R158
+5VLCM +3V +3V +5VLCM
100KOhm 100KOhm ER 1.1 -> PR 2.0
1 1

4 4
G

KBDSCI_3Q
2 S

26,27 KB_SCI# 2 3
2

2
D

+3V
R104 R105 R116 R103
Q30

2
10KOhm 10KOhm 10KOhm 10KOhm
R924
2N7002
1

1
10KOhm

A20GATE_3Q DJ_SW_EN
S 2

1
D

26 A20GATE_3 2 3
3

Q26

3
3
G

D
SCL
1

Q31 2N7002 1 6 Q122

S1 D1 SMC_BAT 54,55
R925 1KOhm
1

2N7002
47 DJ_SW# 1 2 11
2 5 G
+5VS G1 G2 2 S

2
3 4 SDA
54,55 SMD_BAT D2 S2
1

Q32 2N7002
1

2
G

KBDCPURST_3Q SI1902DL R927

2 S

26 RCIN# 2 3
D

R926
22KOhm
5 22KOhm 5
1
1

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan KEYBOARD CONTROLLER (M38857) LIBRARY DATE :
2.0 SHEET 45 OF 61
A B C D E
A B C D E

Internal Keyboard LEDs

+5V

LED2
KSO[0:15] R521
1 KSO[0:15] 45,47 1
1 2 1 + 2 PWR_LED#
PWR_LED# 47
KSI[0:7] 56Ohm
KSI[0:7] 45,47

1
BLUE
C467
CN4 ER 1.1 -> PR 2.0 33PF/50V @
KSO15

2
1 1
2 KSO14
2 KSO13
25 SIDE1 4
3 3
4 KSI7 Power On
5 KSI6
5 KSI5
6 6
7 KSI4
7 KSO12
8 8
9 KSO11
9 KSI3
10 10
11 KSI2
11 KSI1 +3VALWAYS_P +3V +5V ER1.1 -> PR2.0 (Obi-Wan)
12 12
13 KSI0 +5VLCM ER1.1 -> PR2.0 (Obi-Wan)
13 KSO10
14 14
15 KSO9 CN6
15 KSO8 LED3
16 16
17 KSO7 R523 1 15
17 KSO6 + CHG_LED# LID_BOT# 1 SIDE1
18 18 1 2 1 2 CHG_LED# 55 29 LID_BOT# 2 2
26 19 KSO5 3
SIDE2 19 KSO4 56Ohm POWER4_GEAR# 3
2
20 20 45 POWER4_GEAR# 4 4 2

1
21 KSO3 BLUE BLUETOOTH# 5
21 KSO2 45 BLUETOOTH# WIRELESS# 5
22 C468 6
22 KSO1 45 WIRELESS# TP_LOCK# 6
23 ER 1.1 -> PR 2.0 33PF/50V @ 7
23 45 TP_LOCK# 7
KSO0

2
24 24 8 8
BTLED# 9
45 BTLED# KPNUM#_3 9
ZIF_CON_24P Battery Charging 45
45
KPNUM#_3
KBCAP#_3
KBCAP#_3
10
11
10
11
PWRON# 12
29 PWRON# PWR_LED# 12
13 13
14 14 SIDE2 16

ZIF_CON_14P

+5VS

LED4 D7
R524 2 1 WIRELESS_LED#
1 2 1 + 2 ACTIVE#_HCD
1SS355
56Ohm

1
3 BLUE 3

3
C469 Q20A Q20B
ER 1.1 -> PR 2.0 33PF/50V @ UM6K1N UM6K1N

2
40 WIRELESS_LAN_LED 2 5 WIRELESS_LAN_LED1 40
TP

4
Storage Access

2
R83 R92
+5VS 100KOhm 100KOhm

L37

1
1 2
+5VS
80Ohm/100Mhz
1

SR 1.0 -> ER 1.1 l0805

1

LED5
C254 R269 R268 R525
CN10 0.1UF 4.7KOhm 4.7KOhm + WIRELESS_LED#
1 2 1 2
R514 2 1 0Ohm D24
2

41 PDACTIVE#_HDD ACTIVE#_HCD
56Ohm
2

NC2 14 2 1

1
13 BLUE R515 2 1 0Ohm
NC1 41 PDACTIVE#_ODD
12 C470
12 ER 1.1 -> PR 2.0 33PF/50V @ 1SS355
11 11

2
10 10
9 1 2 INTDATA_Q3
4 9 INTDATA_Q3 45 4
L34 60Ohm/100Mhz
8
7
8
7 1 2 INTCLK_Q3
INTCLK_Q3 45
Wireless Enabling
6 L32 60Ohm/100Mhz
6
5 5
4 TP_SW_L
4 SR 1.0 -> ER 1.1 ER1.1 -> PR2.0 (Obi-Wan)
3 3
2 2
1 TP_SW_R
1 +5V
LED1
FPC_CON_12P R887
1 2 1 2 DJ_LED_EN#
+ DJ_LED_EN# 47
56Ohm
1

BLUE
C842
ER 1.1 -> PR 2.0 33PF/50V @
SW2 SW1
2

1 2 TP_SW_L 1 2 TP_SW_R
1 2 1 2
3 3 4 4 3 3 4 4
Audio DJ Enable
TP_SWITCH_4P TP_SWITCH_4P
5 5

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan LEDs & Internal KB TP LIBRARY DATE :
2.0 SHEET 46 OF 61

WWW.AliSaler.Com A B C D E
5 4 3 2 1

+3VALWAYS

D D

+3VALWAYS_P +3VALWAYS_P +3VS

+5VS

1
R443 C409
R143 R141 R139
10KOhm 0.1uF/10V
10KOhm 10KOhm 10KOhm

2
@ @ @

2
Q56 Q29

2
1 1 2N7002
G
@ 3 4
D2 S2
2 S

3
45 MSK_INSTKEY# 2 3
D
2 G1 G2 5

1
U33A
3 6 DJ_PWR# 1 6

CLR
CK Q# S1 D1 PWRON#_DJ 29
ER1.1 -> PR2.0 (Obi-Wan) R935 0Ohm
2 D Q 5 1 2 SWDJ_EN 45
SI1902DL
7 14 @ @
GND VCC

PR
74LV74A ER1.1 -> PR2.0 (Obi-Wan)

4
ER1.1 -> PR2.0 (Obi-Wan)
DJ_PWR#

C C
ER 1.1 -> PR 2.0

+3VALWAYS

CN11
1 1
DJ POWER DJ_SW# 2
KSO4_DJ 2
3 3
REWIND# 4
45,46 KSI2 FORWARD# 4
45,46 KSI3 5 5
STOP# 6
45,46 KSI4 PLAY/PAUSE# 6
45,46 KSI5 7 7 SIDE1 9
8 8 SIDE2 10

FPC_CON_8P
@

26,29,37,55,56 SUSB#_3
Q35
1

2N7002
1
G

@
KSO4_DJ ER1.1 -> PR2.0 (Obi-Wan)
2 S

45,46 KSO4 2 3
D

ER1.1 -> PR2.0 (Obi-Wan)

B B

+3V

SR 1.0 -> ER 1.1

1
R260 R888

10KOhm 1KOhm
@
+5V +3VALWAYS_P DJ_LED_EN#

2
DJ_LED_EN# 46
Q37 3
1

C
1 R B
R140
Q27 10K
100KOhm SR 1.0 -> ER 1.1 Q38 E
@ DTC114TKA 2
DJ_PWR# DJ_SW# @
2

3 D2 S2 4 DJ_SW# 45 46 PWR_LED# 3 D2 S2 4 POWER_LED# 55

1
2 5 2 5 R261 ER1.1 -> PR2.0 (Obi-Wan)
G1 G2 45 SWDJ_LED G1 G2
1KOhm
SWDJ_LED 1 6 1 6
S1 D1 S1 D1

2
SI1902DL SI1902DL
@

A A
ER1.1 -> PR2.0 (Obi-Wan)

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: Obi-Wan AUDIO DJ LIBRARY DATE :
2.0 SHEET 47 OF 61
5 4 3 2 1
A B C D E

AC_BAT_SYS
T174T175T176T177T178T179
TPC28t
TPC28t
TPC28t
TPC28t
TPC28t
TPC28t AC_BAT_SYS
+3VO

1000P
1U
1

1
VR_VID0 1 2 V2.0

1
R194 47KOhm (no_stuff)

5750
7343
VR_VID1 1 2 15UF/25V +

C620

C618
R196 47KOhm (no_stuff) R318
VR_VID2 C616

2
1 1 2 1 2 1
R204 47KOhm (no_stuff)

2
1
VR_VID3 1 2 0Ohm

5
6
7
8
R202 47KOhm (no_stuff) C269
VR_VID4 1 2 0.1U (no_stuff) Q71

D
R200 47KOhm (no_stuff) R319

2
VR_VID5 IRF7413Z

G
1 2 1 2

S
R198 47KOhm (no_stuff) R327

(no_stuff)

(no_stuff)

(no_stuff)

(no_stuff)

(no_stuff)

(no_stuff)
0Ohm 1 2

4
3
2
1
2

1
R195 0Ohm

R197 0Ohm

R205 0Ohm

R203 0Ohm

R201 0Ohm

R199 0Ohm
0Ohm
C272 +VCORE
0.1U(no_stuff) T39 T46 T44 T41 T40
R326 TPC28t TPC28t TPC28t TPC28t TPC28t

2
1 2 L83 R637

1
1 2 1 2
0Ohm
0.56UH 3mOhm

5
6
7
8

D37

1
C264 Q72 +

D
0.1UF CE12
IRF7831

2
STPCPU#

G
6,26 STP_CPU# 1 2 330UF/2V

S
R314 0Ohm
DPRSLPVR

40 R304 2.7Ohm

2
2 26,27 PM_DPRSLPVR 1 2 2

EC31QS04
R308 0Ohm

4
3
2
1
1
VRON

(no_stuff)
29 CPU_VRON 1 2

1000P

C173
R321 0Ohm T93 T97 T60 T62 T118

1
TPC28t TPC28t TPC28t TPC28t TPC28t

2
1

1
49
48
47
46
45
44
43
42
41

39
38
37
U15
MAX1987 RB717F 1 CCS+

CSP
CSN
CMN
CMP

SUS

BSTS

PGND
LXS
DHS
DLS
GND2

DPSLP#

V+
3
2
TPC28t TIME 1 36 +5VO D13 CCM+ T51 T50 T47 T45
T71 STPCPU# TIME VDD TPC28t TPC28t TPC28t TPC28t
1 2 TON DLM 35
TPC28t 3 34
T72 DPRSLPVR B0 DHM AC_BAT_SYS

1
1 4 B1 LXM 33

1000P
TPC28t 5 32 1 2 1 2
B2 BSTM

1U
T73 1 VRON 6 31 R281 2.7Ohm V2.0
S0 DD0#

1
7 30 C260 0.1UF
S1 D0

5750
7343
8 29 15UF/25V +
S2 D1
2

C706

C701
R322 9 28
SHDN# D2

1
C702

2
1 2 10 REF D3 27
R306 100KOhm C258

2
11 ILIM D4 26

5
6
7
8
100KOhm 1 2 12 25 4.7UF/16V
+5VO VCC D5

CLKEN#
IMVPOK
R695 10Ohm Q79

2
VR_VID5
VR_VID4
VR_VID3
VR_VID2
VR_VID1
VR_VID0
SYSOK

D
3 3

OAIN+
OAIN-
1

GND

PSI#
NEG
CCV
POS

CC1
IRF7413Z
100P

0.47U

G
FB

S
2

T68
1

TPC28t R323 T147 T43 T42

13
14
15
16
17
18
19
20
21
22
VR_PWRGD23
CLK_EN# 24
C709 TPC28t TPC28t TPC28t

4
3
2
1
62KOhm
C280

C291

4.7UF/16V L86 R644

47P

MCH_OK

+VCORE
1

1
3

3
3
3
3
1 2 1 2

3
VR_VID5

VR_VID3
VR_VID2
VR_VID1
VR_VID0
VR_VID4
MCH_OK
1

51 VCC_MCH_VRPWRGD 1 2
1

330UF/2V
R287 0Ohm 0.56UH 3mOhm (27A)

5
6
7
8
C281

R305 Q78

D
T70

1
2

+5VO 2 1 IRF7831 +

1
TPC28t

S
100KOhm 1 2 CCS+ C184

CE16
R309 511Ohm D39
CCM+ EC31QS04 0.1U
1

4
3
2
1

2
1 2
1 2 R313 511Ohm
3 PM_PSI#

1
R307 0Ohm T15 T17 T19 T140 T146

1
(no_stuff) +3VS C682 TPC28t TPC28t TPC28t TPC28t TPC28t
1000P (no_stuff)
470PF/50V

R316

1
1

1 2
4 R284 4
1MOhm
10KOhm
1

V1.1
C268
2

VR_PWRGD R317 200Ohm R310

2

6,9,26,29,55 VRM_PWRGD 1 2
R280 0Ohm 1 2 1 2 R343
U53 +5VO 1 2 TIME
1KOhm

6
R345 R324 R325 C282 R311 R312 1 NC 15KOhm
VCC 5
1 2 1 2 1 2 2 1 1 2 DPRSLPVR 1 2 2 A Q39A
100KOhm 3 GND Y 4 2
1.2KOhm 4.7KOhm 1KOhm R283 0Ohm UM6K1N R320
4700P

1
+3VS 2 1 1 2
U52 NC7ST04M5

1
4.7KOhm 36.5KOhm

3
R282 1 NC VCC 5 R344
CLK_EN# 1 2 2 A Q39B
Y 4 56KOhm
3 GND 5 UM6K1N
0Ohm

2
NC7ST04M5

5 for C4 fast exit event 5

T148
TPC28t
Title : VCORE
1

6 CLK_PWR_GD# ASUSTeK COMPUTER INC Engineer: Louis_Lin

Size Project Name Rev
Custom Obi-Wan 1.0

WWW.AliSaler.Com
Date: Thursday, August 04, 2005 Sheet 48 of 61
A B C D E
1 2 3 4 5

1 1
T151
+3VO TPC28t
AC_BAT_SYS
U29 +12VO

1
1
C448 1 2 AC_BAT_SYS D17 1 +12VO
VOUT

1
1 2 +12VIN 3 VIN

1
1000P C414 R470 10Ohm + 2 (0.2A)
R494 C822 C812 GND

2
FS05J10TP
100KOhm 1UF 0.1UF
5.6UF/25V L78L12ACUTR

2
2

2
3V_5V_PRWGD
55 3V_5V_PWRGD

1
C408 C417

5
6
7
8
4.7uF/25V 4.7uF/25V
Q109

2
D
3V_5V_PRWGD
SI4800DY

S
+5VAO (5.0A)

RUN_5VO
+5VO T104 T98 T85 T84
TPC28t +5VO TPC28t TPC28t TPC28t

4
3
2
1
R471
V1.1

1
1 2
100KOhm

2 2
0Ohm
1

4
R507 107KOhm

(no_stuff)

10mOhm

5
6
7
8
U35
1

180P

Q110
32
31
30
29
28
27
26
25

D
1

EC31QS04
R518

LTC3728LX L48
SI4800DY

1
2

100UF/6.3V
4.7UH

G
NC +

PGOOD
NC_3
SENSE1–
SENSE1+

RUN/SS1

TG1
SW1
R517

CE7
D53
C440 C453
2

2
C456

T56 T49 T65 T55

2

2
1UF/10V
0.1UF TPC28t TPC28t TPC28t TPC28t
2

4
3
2
1

2
1

2
1 VOSENSE1 BOOST1 24
JP21

1
2 PLLFLTR VIN 23
1

20KOhm

3 22 +5VAO D18 5V_GND 1 2

PLLIN BG1 +5VO
4 FCB EXTVCC 21 1
5 20 +5VAO 3 SHORT_PIN
ITH1 INTVCC
6 SGND PGND 19 2
7 18 C445 0.1UF
3.3VOUT BG2
R506

RB717F
2

8 17 1 2
VOSENSE2

ITH2 BOOST2 T99

SENSE2+
SENSE2–

RUN/SS2

TPC28t
NC_1

NC_2

33
SW2
TG2

SIDE1
1

C427 AC_BAT_SYS
1000P

3 4.7u 3
10
11
12
13
14
15
16
1000P

2
1

1
+
RUN_3VO
C464

0Ohm (no_stuff)

C411 C401
1U
C466

5.6UF/25V
2

2
1

2
1
R516 0Ohm
C463 220P

C465 220P

V1.1
1

1
R520 150KOhm

R522 150KOhm

C450 Q50
2

2
1

1000P
R519

(4.3A)
2

1 D1_1 G1 8
T86 T160 T80 T81 T139 T138
C454 180P 2 D1_2 S1/D2_3 7 TPC28t +3VO TPC28t TPC28t TPC28t TPC28t TPC28t
2 1 L44 R419
2

1
3 G2 S1/D2_2 6 1 2 1 2
R511 R503
1 2 1 2 +3VO 4 5 4.7UH 12mOhm
S2 S1/D2_1

CE4
20KOhm 64.9KOhm SI4814DY

1
+

1
4 4
Vref = 0.8 V C400

120UF/4V
1UF/10V
T59 T52 T54

2
V1.1 JP8 TPC28t TPC28t TPC28t
D62 RB715F 3V_GND 1 2

1
2
3 SHORT_PIN
51,52 SHUT_DOWN#
1
+3VAO

D21 RB715F
1

2 RUN_3VO
3
R509 1 RUN_5VO
6

100KOhm
Q58A
2

43 SUSC_PWR 2 UM6K1N
1
3

0.01U

0.01U

Q58B
1

5 55,56 SUSC#_PWR 5 UM6K1N 5

C447

C444
4

Title : SYSTEM
ASUSTeK COMPUTER INC Engineer: Louis_Lin
Size Project Name Rev
Custom Obi-Wan 1.0
Date: Thursday, August 04, 2005 Sheet 49 of 61
1 2 3 4 5
A B C D E

VREF5
T163
ON_1.8 TPC28t AC_BAT_SYS

100KOhm

0.1UF
1

1
1 + 1
R809 C832
55,56 SUSC#_PWR

5
6
7
8
C827 5.6UF/25V

2
2

C837
Q93A Q105 JP25 SHORT_PIN

2
2 1

D
1
R816 UM6K1N +1.8VGND 1 2
C789 +1.5VO +1.8VO SI4800BDY TPC28t

G
2 0.1UF

S
210KOhm (3.5A) T78
4700P

3
Q93B +1.8VO T34 T33

2
1 2
UM6K1N (5.0A) TPC28tTPC28t T35 +1.8V
1

4
3
2
1
JP4

1
6800P

6800P
R855 0Ohm L46 TPC28t

1
5

C808

C815
+1.8VO

1
1 2 1 1 2 2
1

10.2KOhm
C788

C392 10UF/6.3V
4

1
2

11.8KOhm
3.8UH 3MM_OPEN_5MIL

1
R836

330UF/2V
0.1UF V1.1 +

5
6
7
8

1
R853

CE5
T58 T95 T92
2

2
330Ohm
R805 15KOhm Q104 TPC28t TPC28t TPC28t

D
1
R833
D23

1
1 2 SI4800BDY

330Ohm
1

2
G

S
1SS355

R854
2
2 1
R844 C786 0.1UF

4
3
2
1
AC_BAT_SYS

2
1 2

0.01uF/25V
2
+1.8VGND 2
VREF5 12.7KOhm R856 10.2KOhm AC_BAT_SYS
1 2 T165
ON_1.5 1 2 1 2 TPC28t
1

1
100KOhm

2.7Ohm
R861 10.2KOhm R858 0Ohm

VREF5

1
51,55,56 SUSB#_PWR

1
C817

0.1UF
R828 2 1 Q114 +

3300P

R857
C829 0.1UF C833

1
C825
+1.8VGND TPC28tTPC28t (3A) TPC28t+1.5VS

1
1 8
2

D1_1 G1
Q96A +1.5VGND 5.6UF/25V T94 T90 +1.5VO T53
2

1
R824 UM6K1N

2
2 7 JP9
1

1
D1_2 S1/D2_3

C809
C830 L49

2
2

1
0Ohm C797 C800 0.1UF +1.5VO1

1
3 6 1 2 1 2 2
3

G2 S1/D2_2
D49
1

2
48
47
46
45
44
43
42
41
40
39
38
37
4700P 5600P

330UF/2V
2.7KOhm
Q96B U65 5.2UH 3MM_OPEN_5MIL
1

1 2 4 5

1
S2 S1/D2_1

R846

2
5 +

OUT1_U

OUT1_D

OUT2_D
INV1
FLT
LH1

LL1

OUTGND1
TRIP1
VIN_SENSE12
TRIP2
OUTGND2

CE9
UM6K1N 1SS355 SI4814DY
1

C796 VREF5 T91

4

R835 JP23 TPC28t

2

(no_stuff)

0.22UF +1.5VGND

2
1 FB1 LL2 36 1 2
0Ohm

@ 1.8KOhm ON_1.8
2

1
2 SS_STBY1 OUT2_U 35
R810

3 34 SHORT_PIN
INV2 LH2
2

4 FB2 VIN 33 +5VO

ON_1.5
3 5 SS_STBY2 TPS5130 VREF3.3 32
VREF5
V1.1 3
1

6 PWM_SEL VREF5 31
7 CT REG5V_IN 30
8 GND LDO_IN 29 2 1 C804 0.1UF
2

9 REF LDO_CUR 28 1 2 +3VO

1

47pF/50V

R822 1 2 10 27
STBY_VREF5 LDO_GATE
1
R814

C806

0.1U
0Ohm

200KOhm R815 100KOhm 11 26 R831 20mOHM

STBY_VREF3.3 LDO_OUT

1
VIN_SENSE3
SUSB#_PWR 1 2 ON_2.5 12 25

PG_DELAY
STBY_LDO INV_LDO
SS_STBY3
AC_BAT_SYS

OUTGND3

4.7uF/25V
C811
2

1
OUT3_U

OUT3_D
C803
1

PGOUT
1UF
1

8
TRIP3
C801

2
INV3
FB3

LH3

LL3
Q92
0.22UF R827 D

2
ON_2.5 RSS090N03
2

1 2
13
14
15
16
17
18
19
20
21
22
23
24

C452
0Ohm C798
ON_1.05 +1.05VGND 2 1 G S (0.2A) TPC28t
+2.5VO T156 +2.5VS T76
0.1UF TPC28t
D46

1
JP16
2

VREF5 R817 R821

1
2 1
C792
100KOhm

2.7KOhm

ON_1.05 1 2 1 2 +2.5VO 1 2
1 2
R807

2 1
1

10.2KOhm

4 1SS355 10KOhm 20KOhm V1.1 1MM_OPEN_5MIL 4

29 CPU_VRON

1
0.1UF

0.1UF

0.1UF T79 + C787

1

R823 TPC28t AC_BAT_SYS

1

V1.1
2

1
C782 0.01U

Q98A
1

R829 UM6K1N 100UF/4V

1
C785

C807
2

2
2

1
C791

R813

0Ohm
2

3300P +
3

Q98B C395 (4A)

1

UM6K1N
V1.1 Q45
1

5.6UF/25V T82 T83 +1.05VO JP7

5
TPC28t TPC28t (2A)

2
1 8 1 1 2 2 +VCCP
1

D1_1 G1
C802 L45
4

1 2
R818 0Ohm +1.05VO 2MM_OPEN_5MIL

1
2 D1_2 S1/D2_3 7 1 2
0.01U
(no_stuff) 5.2UH JP6
2

3 6
2

G2 S1/D2_2
49.9KOhm

1 1 2 2 +VCC_GMCH_CORE

1
680Ohm

4 S2 S1/D2_1 5 +
R796

R800

T96 T48 CE6 2MM_OPEN_5MIL (2A)

2

12.7KOhm

SI4814DY TPC28t TPC28t 330UF/2V

R799

+3VO
1

2
1

JP5
1

C784 +1.05VGND
1

5 1 2 5
5600P
+5VALWAYS R804 SHORT_PIN
2

T103 T105
+1.05VO 100KOhm
TPC28t TPC28t
Title : 2.5V & 1.5V & 1.8V & 1.05V
2

JP10 4_IN_ONE_PWRGD 55
VREF5 1 ASUSTeK COMPUTER INC Engineer: Louis_Lin
1

VREF5 1 2 2
Size Project Name Rev
1MM_OPEN_5MIL Custom Obi-Wan 1.0
Date: Thursday, August 04, 2005 Sheet 50 of 61
A B C D E

WWW.AliSaler.Com
5 4 3 2 1

T171

TPC28t

D59

1
49,52 SHUT_DOWN# 2 1

D F01J2E T180 D
TPC28t
+3VALWAYS T109 TPC28t TPC28t +1.5VALWAYS
AC_BAT_SYS Vref=1.215V T74
+1.5VAO
R867 JP3

1
U17 +1.5VAO

1
1 2 1 1 2 2
1 IN OUT 5

2
100KOhm T170 2 1MM_OPEN_5MIL
GND R359
T172 T30 3 EN ADJ 4
U67 TPC28t
TPC28t TPC28t SI9183DT 2.4KOhm

1
1 6 +3VAO +3VALWAYS_P C317
FB OUT L51 JP24

1
2 GND SHDN# 5
+3VAO 4.7u

1
3 IN LX 4 1 2 1 1 2 2

2
MAX1837EUT33 22uH 1MM_OPEN_5MIL (0.1A) R358

2
10UF/35V
1

1
+ + CE21 10KOhm

1
CE8

D58
C828

1
FS05J10TP 100UF/4V 0.1UF/25V
2

2
C SR1.0-->ER1.0 C

+3VS

T181
1

R663 TPC28t +3V

+3VS 100KOhm

1
1
1

+0.9VS R801
2

DDR_PWRGD 55 T77
R689
3

100KOhm 3 100KOhm
D TPC28t
T155 T157
2

Q77 TPC28t TPC28t T158 T75

2
JP15 U64
R662 11 TPC28t TPC28t
2

1
G 2N7002 JP17

1
+1.8V 1 2 1 6
10KOhm 3 2 S 1 2 VIN VCNTL2

1
2 GND VOUT 5 1 1 2 2 +0.9VS
C 2MM_OPEN_5MIL (0.5A)
2

3 VCNTL1 REFEN 4
1 B 2MM_OPEN_5MIL
1

1
RT9173ACL5 +
2

1
E CE20
R656 2 Q75 R802
B PMBS3904 100U/2V B
30KOhm 100KOhm

2
1

1
C790 C799
T89
1

2
10UF/6.3V 10UF/6.3V TPC28t +3V

1
+3VS
R798
T182
1

100KOhm
R650 TPC28t

6
+3VS 100KOhm Q90A

2
UM6K1N
1

2
1

+VCC_GMCH_CORE
2

VCC_MCH_VRPWRGD 48
R648

1
3

3
100KOhm 3 Q90B
D
R803 0Ohm
2

Q74 1 2 5
50,55,56,57 SUSB#_PWR
R646 11 UM6K1N
2

G 2N7002

4
10K 3 2 S
C
2

1 B
1

A A
2

E
1

R649 2 Q73
C674 PMBS3904
30KOhm
0.22UF
2

Title : 1.5VA & DDR2

ASUSTeK COMPUTER INC Engineer: Louis_Lin
Size Project Name Rev
Custom Obi-Wan 1.0
Date: Thursday, August 04, 2005 Sheet 51 of 61
5 4 3 2 1
5 4 3 2 1

A/D_VIN

A/D_VIN_O
T124 +5VCHG +5VO
T119 T122 T120 T121 T1271 T21
TPC28t T36 T37 T38 T141 TPC28t
44,53 A/D_DOCK_IN Q1 D4
R529 D26 +5VLCM

1
TPC28t TPC28t TPC28t TPC28t U3 TPC28t
S D A/D_VIN

1
A/D_DOCK_IN 1 8 1 2 1 TPC28t TPC28t TPC28t TPC28t 1

22KOhm
L78L05ACUTR

1
2 7 2 AC_BAT_SYS 3
3 6 10mOhm 3 3 1 +5VCHG 2
IN OUT

1
0.01UF/25V
D 4 5 D

GND
G

1
FD6JK3TP F02JK2E

C476
TPC8107 Q14 R16

R533
1 S D 8 T4 1KOhm
BAT
TPC28t

2
2 7
+2.5VREF

LM4040BIM3X
2
3 6

2
1 4 G 5

1
D5 +2.5VREF

1
R531

100KOhm D1 TPC8107 C44 C43

UDZS5.6B

1
1U C18
(no_stuff)
2 1 1U

1
2

2
1U
C19

2
1SS355 3

22KOhm
2

U2
(no_stuff)
R1 1UF/10V

2
1

2
1 2 MAX1909_PDS 53
10KOhm

R527
A/D_SD
2
+5VCHG, +5VLCM, +2.5VREF
6

T108 Q63A
3

UM6K1N
TPC28t 2
Q63B AC_BAT_SYS A/D_DOCK_IN
1

45,53 BAT_LEARN 5
UM6K1N (no_stuff)
1
1

(no_stuff)
4
1

R528

100KOhm

R865 100KOhm
T27
100KOhm

TPC28t
(no_stuff)

(no_stuff)

C C

1
R530

2
1
45 ACIN_OC
R872
2
2

Q108 68KOhm

3
3

2
D 2N7002

1
11
BAT_IN 29
G
S 2
AC_BAT_SYS, BATTERY LEARN CIRCUIT

2
T173
3 TPC28t
C R-1
B 1

0.1UF/25V
47K

10KOhm
E
R-2

1
AC_BAT_SYS 47K

1
2

R873

C835
Q113

1
+5VLCM DTC144EK

2
470KOhm

R7 R10

2
1

47KOhm 100KOhm
R57

T3
TPC32t
B B
(8.6V)
2

2
ADAPTER IN CIRCUIT
D2 1SS355

+5VCHG
SHUT_DOWN# 49,51
2
2

1
1

BAT_S
10KOhm

2
Q7 Q9 3
1

D3 C T28
V1.1
E
PMBS3906

1 B PMBS3904 TPC28t
RB715F
2

1
243KOhm

R58

1 B
R31
C E +5VLCM
1

1
3 2 BAT_IN#_OC 45
R33

10KOhm
33

3
2

100KOhm
U5 R53 0Ohm

1
+5VLCM (no_stuff) Q15
1

1 OUT1 VCC 8
2 AC_APR_UC
100KOhm

R102 100KOhm
2 -IN1 OUT2 7 1 11
1

1
2N7002
R8

+2.5VREF 3 6 +2.5VREF G
+IN1 -IN2 2 S
1

A/D_VIN
4.7u
R9

4 VEE +IN2 5

6
R98
C14 Q25A
2

47KOhm

LM393MX

2
0.1UF/25V
2

C51

UM6K1N
2

2
R38
2

2
T16
1

1
143KOhm
1

1
100KOhm

0.1UF

TPC28t

3
R39

C42

(9.66V)
1

1
1

0.1UF
2

53,54,55 TS# 5
2
C35

Q25B
1

0.1UF
C32

R32 UM6K1N
2

4
AC_APR_UC 53,55

1000PF/16V
2

49.9KOhm

1
V1.1
1

C93
2

A A
R36
1

100KOhm

2
2

BATTERY IN CIRCUIT
Title : BATLOW/SD#
AC_IN & BATTERY SHUT_DOWN ASUSTeK COMPUTER INC Engineer: Louis_Lin
Size Project Name Rev
Custom Obi-Wan 1.0

WWW.AliSaler.Com
Date: Thursday, August 04, 2005 Sheet 52 of 61
5 4 3 2 1
1 2 3 4 5

A/D_VIN
A/D_VIN_O

0.1U

0.1U
A/D_DOCK_IN

1
C59

C57
1 1
T144

2
TPC32t

52 MAX1909_PDS AC_BAT_SYS

1
5.6UF/25V

5.6UF/25V
52,55 AC_APR_UC

1
+ +

C49

C48
MAX1909_LDO

4
3
2
1
CHG_GND T8 T7
A/D_VIN A/D_DOCK_IN Q17 TPC32tTPC32t

2
S
2

0.1U

G
SI4835BDY

1
R87 MAX1909_LDO

D
CHG_GND

1
100KOhm

C63

2
2

5
6
7
8
R73

1 PKPRES#
LDO : 5.4V D6

29
28
27
26
25
24
23
22
33Ohm
2

1SS400
100K
R89

REF : 4.2235V

PDS
CSSP
CSSN
SRC
GND2

DHI
DHIV
PDL
C58 0.1U T24 T10 T9

1
2 2
1 21 1 2 TPC32t TPC32t TPC32t
DCIN DLOV
2 LDO DLO 20
L11 R54
1

3 ACIN PGND 19
1909_REF BAT

1
4 REF CSIP 18 1 2 1 2 BAT
5 PKPRES# CSIN 17

10uF/25V

10uF/25V
6 16 10UH 15mOhm
ACOK BATT

VCTL
7 15

ICTL

CCV
CCS
IINP
CLS
MODE GND1
2

5
6
7
8
CCI
1U

1U

1U
2

1
27KOhm

Q22

D
27KOhm
R88

U8 SI4800DY

10
11
12
13
14
MODE
R95

C47

C36
MAX1909 D8

8
9

S
C68

C71

C85
EC31QS04

2
2

33.2KOhm
1

12.7KOhm

R97
1

4
3
2
1

1
R94

IINP

10KOhm
CHG_GND
VVCTL

R85
AC_IN Threshold 2.089Vmax
1

A/D_DOCK_IN > 9.83V VICTL

VCLS
active

1
C77

C74
0.01U

0.01U
1.860V 1.80V 1.576V

1 CHG_CCV
3 3
2

2
10KOhm

20KOhm

2
20KOhm
R93

R96

0.1U
R84

1
10KOhm
+5VCHG R91

0.1U
C76
1

C87
2
2

2
R107
100KOhm
3

3
D
1

R108 Q23
55 CHG_EN# 2 1 11
G 2N7002
3.3KOhm 2 S
1

MAX1909_LDO
2

R109
10KOhm
(no_stuff)

2
4 4
R11 PKPRES#
2

100KOhm

3
3
D

1
Adapter Iin(max) = [0.075V/Rsense(ADin)]*[VCLS/VREF] VICTL MODE Q5
Rsense(ADin)=0.01 ohm 11
VCLS=1.864V 1.008V=> 1.4A G 2N7002
2 S

3
=> Iin(max)=3.41A 3 3
D D
2

14.7KOhm

=> Constant Power = 19 * 3.41= 64.79W

2
R34

Q8 Q6
Charge Current Ichg = [0.075V/Rsense(CHG)]*[ICTL/3.6V]
45,52 BAT_LEARN 11 52,54,55 TS# 11

1
Rsense(CHG)=0.015 ohm G 2N7002 G 2N7002
VICTL= 1.8V T128 2 S 2 S C17
=> Ichg = 2.5A TPC32t
1

2
0.22UF

2
3

Vbatt = Cell * { Vref +[ (VCTL- 1.8V) / 9.52 ] } 3

D
VCTL= 1.576V
1

=> Vbatt = 4.2V Q13

45,54 BAT_SEL 11
Mode pin : Vmode > 2.8V (trie to LDO pin) ----> 4 Cells G 2N7002
2.0 > Vmode > 1.6V (floating) ----> 3 Cells 2 S
0.8 > Vmode (trie to GND) ----> Learning mode
2

5 5

VICTL< 0.8V or DCIN < 7V -->Charger Disable

Title : CHARGER
Pre_CHG_V = 3.1V Engineer:
Pre_CHG_I = 300mA ASUSTeK COMPUTER INC Louis_Lin
Size Project Name Rev
Custom Obi-Wan 1.0
Date: Thursday, August 04, 2005 Sheet 53 of 61
1 2 3 4 5
A B C D E

1 TPC28t 1
T116 (no_stuff)
R548 0Ohm

1
1 2 BAT_SEL 45,53,55

R547 0Ohm
1 2 BAT_S
T110 T114 T111 T113
TPC28tTPC28tTPC28tTPC28t

BAT

1
1 2
CN18
TPC28t
6 T117 L62 150Ohm/100Mhz
5 R556 0Ohm

1
4 1 2 SMC_BAT 45,55
3 TPC28t
2 T112
R550 0Ohm

1
1 1 2 SMD_BAT 45,55
2 2
TPC28t
BATT_CON_6P T115
R549 100Ohm

1
1 2 TS# 52,53,55

D29 D30 D28

2
V0402MHS03

V0402MHS03

V0402MHS03
1

1
T63 T57 T88 T64 C500 C499
C495 C496 C498 C497 C503
TPC28t
TPC28t
TPC28t
TPC28t 0.1UF/25V 0.1UF/25V
1KOhm 100P 100P 100P 100P
2

2
1

1
ER1.1 -> PR2.0 (Obi-Wan)

3 3

95 DEGREE C
T102 THERMAL PROTECTION
TPC28t PLACE UNDER CPU

1
VREF5 R754==> 23.3k==>95 degree c

2
R806 R754==> 33.2k==>80 degree c
23.2KOhm
T154
RT1 100KOhm

1
TPC28t
2 2 1 1
4 C783 4

1
2 1
T159
0.01U TPC28t
U63

1
1 NC VCC 5
2 R812
SUB
3 GND VOUT 4 1 2 0Ohm OTP#_P 7,29
PST9013

5 5

Title : BAT CONNECT

ASUSTeK COMPUTER INC Engineer: Louis_Lin
Size Project Name Rev
Custom Obi-Wan 1.0

WWW.AliSaler.Com
Date: Thursday, August 04, 2005 Sheet 54 of 61
A B C D E
5 4 3 2 1

+5VLCM
U6

2
SOT23_S5_NB
D 5 VCC NC 1 D
C37 R76 2
100KOhm SUB TPC28t TPC28t
1U 4 VOUT GND 3
TPC28t TPC28tTPC28tTPC28t TPC28t T5 T126

2
T26 T135 T131 T123 T23
PST9142

1
U7

1
CHG_LED

1
1 RA2 RA1 20 AC_APR_UC 52,53
2 19 TS#
53 CHG_EN# RA3 RA0 TS# 52,53,54
3 18 TPC28t TPC28t
T0CKL OSC1/CLKIN T20 T11 T18
4 MCLR#/Vpp OSC2/CLKOUT 17
5 16 TPC28t
Vss1 Vdd2

1
6 Vss2 Vdd1 15
SMC_BAT BAT_LLOW

1
45,54 SMC_BAT 7 RB0 RB7 14
SMD_BAT 8 13 SEL_1POR2P 2 1 BAT_SEL
45,54 SMD_BAT POWER_LED RB1 RB6 BAT_SEL 45,54
9 12 2 1 FULL_LED R70 10KOhm
RB2 RB5 10KOhm R49
50,51,56,57 SUSB#_PWR 10 RB3 RB4 11
R50
PIC16C54C_04/SS TPC28t 1 2 TPC28t 1 2 RST_BTN# 27,29
T6 T14
1MOhm R75 4.7KOhm
(no_stuff)

1
X1

1
1 3
GND C52
1UF/10V T1 TPC28t
4MHZ

2
C C

1
BAT_LLOW#_OC 45

3
3
D
Q12
BAT_LLOW 11
G 2N7002
2 S

2
Q68 2N7002

POWER_LED#

S 2

D
2 3 POWER_LED# 47

3
G
1
3
3

1
D
Q67
14

U69D POWER_LED 11 SUSC#_PWR

VCC 2N7002 SUSC#_PWR 49,50,56,57
12 G
11 2 S T25
2

13
GND
TPC28t
LV08A CHG_LED#

1
B EOC#_LED CHG_LED# 46 B
7

EOC#_LED 45

3
3
D

3
3 Q21
D
CHG_LED 11
Q18 G 2N7002
CHG_EN# 11 2 S
+3VAO 26,29,37,38,47,56 SUSB#_3 2N7002
T61 T152 G

2
2 S
TPC28t TPC28t
2

R866

2
2
1SS355

422KOhm
14

D57

U69A
1

1 VCC
6,9,26,29,48 VRM_PWRGD POWERGD 29
3
6
1

51 DDR_PWRGD 2
GND T87
1

LV08A TPC28t 2
Q111A
7

14

U69B UM6K1N
1

VCC POWERGD Q111B

1

4
6 5 UM6K1N PWRERR# 29
1

5
T168 T100 GND C836
4

TPC28t TPC28t LV08A 1uF/6.3V

7

2
14

U69C
1

A A
9 VCC
49 3V_5V_PWRGD
8
50 4_IN_ONE_PWRGD 10
GND
LV08A
7

Title : PIC16C54 & PRO_CIR

ASUSTeK COMPUTER INC Engineer: Louis_Lin
Size Project Name Rev
Custom Obi-Wan 1.0
Date: Thursday, August 04, 2005 Sheet 55 of 61
5 4 3 2 1
5 4 3 2 1

T183
TPC28t
TPC28t
T31
Q36 JP1

1
8 D S 1 1 2
+1.8VO 1 2 +1.8VS
(4.2A)

1
7 2

1
6 3 C138 3MM_OPEN_5MIL
5 G 4 SUSB#_PWR_ON
0.1UF/25V

2
SI4800BDY
D T164 D
TPC28t TPC28t TPC28tTPC28t
T166 T136 T169 T167 TPC28t
JP20
PMN45EN
1

1
+3VO 1 1 2 2 +3VS
(3A)

6
5
4

1
C824 3MM_OPEN_5MIL
Q99

S
0.1UF/25V

2
D

G
1
2
3
T145
TPC28t TPC28t TPC28t TPC28t
T67 T66 T162 T161 TPC28t
JP19
+5VO PMN45EN
1

1
1 1 2 2 +5VS
(2.5A)

6
5
4
3MM_OPEN_5MIL

1
Q97 C820

S
0.1UF/25V

2
G
1
2
3
C R820 C
2 1 TPC28t
T106
Q91 10KOhm
UMC4N
TPC28t

1
+12VO +12VS
T32

4
3

E
47K

2
B
TPC28t
1

26,29,37,38,47,55 SUSB#_3 2 1
T29 R795
47K
2

10K
B
47K

R826 1KOhm

1
C794 100KOhm
1

6
50,51,55,57 SUSB#_PWR
0.1UF/25V

1
2
VREF5 2 1

R825 0Ohm
(no_stuff)

+3VAO

T184
TPC28t
TPC28t
B T137 B
JP18

2
1

1 2 R811 SUSB#_PWR_ON
+3VO 1 2 +3V (1.2A)
1

C826 1MM_OPEN_5MIL 100KOhm

6
0.1UF/25V

1
2

+12VO +12V 43 SUSB_PWR 2

1

T185 (0.1A) Q94A

TPC28t C695 UM6K1N

1
TPC28t
T69 0.1UF/25V
2

JP2
1

+5VO 1 2 (2.5A)
1 2 +5V
1

3
Q94B
1

C174 3MM_OPEN_5MIL UM6K1N

SUSB#_PWR 5
0.1UF/25V
2

4
T186
TPC28t TPC28t
T101 TPC28t
T12
JP14
1

+1.8VS
1

26,29 SUSC#_3 2 1 1 1 2 2 +ATI_MEM

1

T143
1

A A
TPC28t R510 C604 3MM_OPEN_5MIL
1KOhm
0.1UF/25V
1

49,50,55,57 SUSC#_PWR

VREF5 2 1 Title : LOAD SWITCH

R504 0Ohm Engineer:
(no_stuff) ASUSTeK COMPUTER INC Louis_Lin
Size Project Name Rev
Custom Obi-Wan 1.0

WWW.AliSaler.Com
Date: Thursday, August 04, 2005 Sheet 56 of 61
5 4 3 2 1
5 4 3 2 1

AC_BAT_SYS
+3VS +5V

L80 1 2 70Ohm/100Mhz
C595

0.1UF/25V

5.6UF/25V

5.6UF/25V
1

1
C591

C587

C580
D C92 C91 2 1 + + D

2
R124 0.1UF/25V 4.7UF/6.3V 2200P

1
R129 +ATI_VCORE 8A

2
10KOhm D10

2
4.7UF/6.3V 20Ohm
MAX1844EEP SS0540
V1.1

5
6
7
8
C96

1
U11 Q65 JP13 JP12 JP26

2
2 1

2
3MM_OPEN_5MIL

3MM_OPEN_5MIL

3MM_OPEN_5MIL
13 VDD V+ 16

2
S
1844VCC 14 18 1 2 2 1 SI4894DY-TI
VCC BST

1
R132 0Ohm C105 0.1U

4
3
2
1
17 SKIP DH 20
TP84 TP19

1
14 PWR_OK_VGA 10 PGOOD LX 19
R605 L77

1
55,56 SUSC#_PWR 1 2 3 SHDN CS 1 1 2

2
10KOhm 7 12 1.8UH
ILIM DL

1
+ + D33

5
6
7
8
2 4 V1.1 C524 C523 C555
LATCH OVP

2
D36 R127 Q64 SS0540

D
1 2 8 9 1844VCC 330UF/2V 330UF/2V 0.1UF/25V (no_stuff)
51,55,56 SUSB#_PWR REF UVP D35

1
G

S
1SS355 71.5KOhm 15 6 SI4894DY-TI EC31QS04
TON OUT
2

4
3
2
1

1
11 GND FB 5

2
R136 C110 R130 C101 C106

1
C 150KOhm R128 R133 C
10KOhm 0.1UF/25V 1UF/10V REF=2.0V

0.1UF/25V
(no_stuff) (no_stuff) 0Ohm 2.1KOhm

2
(no_stuff)
1

2
2

1
2
+5V R134
TON :
Max IL(Min) = 10KOhm C104
NC =

2
Iocp-0.5IL(pp)
300KHz R600 0.1UF/25V

1
=10-0.5*2.45A
=8.775A

3
100KOhm 3
D
Ilimt= 8.775*10A*0.018*1.3
H: 1.0V

1
=2.05V > 2.0V
L: 1.2V 11 Q28
G 2N7002 For LVDDR_25 power
2 S

3
3
D
Q66

2
2N7002 Option 1 : remove R2148 add R2147 LVDDR=2.5V
14 ATI_PERF# 11
G Option 2 : remove R2147 add R2148 LVDDR=2.8V
2 S

2
R603
1 2 +2.5VS
0Ohm (no_stuff)
B T132 T133 B
TPC32t TPC32t
V2.0 R602

1
1 2 LVDDR
0Ohm
(400mA)

TP79 TP80 TP81 TP82 TP83

127KOhm
T134 +3VS
+1.8VS +5V +1.8VS TPC32t

R606
1

1
1

T125 +ATI_VCORE R604 100KOhm U44

1
TPC28b R565 SUSB#_PWR

2
1 2 1 EN GND1 5
U40
49.9KOhm 2 IN GND2 6
+1.2VSP 1 8 3 7
VIN PGND C599 OUT GND3
1

JP11 2 VFB AGND 7 4 ADJ GND4 8

2

3 VOUT0 VCCA 6

100KOhm
1 2 4 5 0.1UF/25V MIC39102BM
GND

1 2 VOUT1 REFEN

1
R607
(2A) T13

10UF/6.3V

10UF/6.3V
C594

C593
2MM_OPEN_5MIL TPC32t
VFB=1V
2

CM8562
1

C513 C509 C512 C858 R573 TP41 TP37 TP38 TP36 TP35
9

2
2

1
10uF 10uF 10uF 0.1UF/25V 100KOhm
2

1
1

A A

Title : VGA CORE

ASUSTeK COMPUTER INC Engineer: Louis_Lin
Size Project Name Rev
Custom Obi-Wan 1.0
Date: Thursday, August 04, 2005 Sheet 57 of 61
5 4 3 2 1
1 2 3 4 5

A/D_DOCK_IN +5VLCM
L78L05 +5VCHG (20mA)
SWITCH
(Regulator)
(F02JK2E) LM4040BIM +2.5VREF
1
+5VO (Regulator) 1

AC_BAT_SYS +3VALWAYS_P(0.25A)
MAX1837EUT33

+3VAO SI9183DT +1.5VALWAY

SUSC#_PWR
+3VO(4.3A) +3V(1.2A)

LTC3728LX +5VO(5.0A) +5V(2.5A)

(Controllor)
+12VO(0.2A) +12V(0.1A)
2 2

SUSB#_PWR
+0.9VS(0.5A)
+1.8VO(6.7A) +1.8V(3.5A) RT9173ACL5
SUSC#_PWR
(Regulator)

+1.5VS(3A)
SUSB#_PWR
+5VO +1.05VO(4A) +VCCP(2A)
CPU_VRON
+1.05VS(2A)
3 TPS5130 VREF5
3
+5VALWAYS
(Controllor)

+2.5VS(0.2A)
SUSB#_PWR

SUSB#_PWR
+12VS(0.1A)
(UMC4N)
+5VS(2.5A)
PMN45EN +3VS(3.1A)
4 MIC49150 +1.2VSP(1.52A) 4
+1.8VS(2.7A)
CPU_VRON SI2304DS (Regulator)
+5VO
MAX1987 +VCORE
(27A)
(Controllor)
VRM_PWRGD, CLK_EN#
VR_VID0 - VR_VID5, STP_CPU#, PM_DPRSLPVR, PM_PSI#
SUSB#_PWR
+ATI_VCORE
MAX1844EEP (8A)

5 5

Title : POWER FLOWCHART

ASUSTeK COMPUTER INC Engineer: Louis_Lin
Size Project Name Rev
Custom Obi-Wan 1.0

WWW.AliSaler.Com
Date: Thursday, August 04, 2005 Sheet 58 of 61
1 2 3 4 5
5 4 3 2 1

POWER REVISION HISTORY

PAGE 41
PAGE 42
PAGE 42
PAGE 42
PAGE 42
D PAGE 43 D

PAGE 43
PAGE 43
PAGE 43
PAGE 44
PAGE 45
PAGE 46
PAGE 46
PAGE 48
PAGE 48
PAGE 48
PAGE 49
PAGE 49

C C

B B

A A

REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: M9 POWER_HISTORY LIBRARY DATE :
1.0 SHEET 59 OF 61
5 4 3 2 1
A B C D E

POWER INTERFACE IMPEDENCE PCB STACK-UP

REVISION HISTORY SIGNALS TYPE POWER PCB THICKNESS: 1.2 mm
Single-Ended
03/09 AUDIO CODEC REALTEK ALC880 ---> ADI AD1986A CLK_EN# I +3V
L1 TOP
03/22 RENAME PM_PSI# O +VCCP 27.4 OHM WIDTH
L2 GND1
05/05 ADD U70, DEL C396, CHANGE CN21 3P--->4P, CHANGE U54 VR_VID[5:0] O +VCCP TOP/IN3/BOT 14 mils
1
IN1/IN2 16.5 mils L3 IN1 1
ADT7460--->ADT7473, CHANGE CN13, DEL R768, DEL R774, CPU_VRON O +3V
L4 IN2
CHANGE CN10(P1<->P12), CHANGE CN3(P5<->P7), ADD U71, R881, VRM_PWRGD I +3V 37.5 OHM WIDTH
L5 VCC
R882, R883, C840, U72, R884, R885, R886, C841 CPU_STP# O +3V TOP/IN3/BOT 8.5 mils
IN1/IN2 10 mils L6 IN3
05/06 DEL R267, ADD R887, R888, C842 CHG_LED I +3V
L7 GND2
05/09 UPDATE POWER SCHMATIC, ADD U32.P2 R889, R890, R891, RST_BTN# O +3V 42 OHM WIDTH
L8 BOT
DJ_SW# -> U12.P76 OTP_RESET# I +3V TOP/IN3/BOT 7 mils PAGE 41

05/10 ADD R892, R893, R894, R895, R896, R897, R898 SHUT_DOWN# I +3V IN1/IN2 8.5 mils
SIGNAL IN: VR_VID0 - 5
PM_DPRSLPVR
05/16 ADD R899, R900, R901, R902 +V5_LCM PWR +5V 55 OHM WIDTH STP_CPU#
PM_PSI#
PM_SLPDLY_S3# O +3V TOP/IN3/BOT 4 mils IMVP_VR_ON
PM_SLP_S4# O +3V IN1/IN2 4.5 mils
OUT: DELAY_VR_PWRGD
VR_PWDGD_CK410#
SR1.0 -> ER1.1 BAT_LEARN I +3V 60 OHM WIDTH
POWER IN: AC_BAT_SYS
Page5, Change H8,H3 from AM20~30 to AM20. BAT_LLOW#_OC I +3V TOP/IN3/BOT 3 mils +5VO
Page6, Change value of C267 and C271 from 12PF to 3PF. BAT1_IN#_OC I +3V IN1/IN2 4 mils +3VO
2 2
OUT: +VCORE
Add net CLK_TPMPCI from pin8 of U16 to pin21 of U74 and add BAT2_IN#_OC I +3V
R919 on this net. ACIN_OC I +3V Differential PAGE 42

Page7, Change CN21 from WTOB_CON_3P to WTOB_CON_4P. CHG_EN_OC I +3V 70 OHM WIDTH/SPACE SIGNAL IN: SUSC#_PWR
VSUS_ON
Add net PWN1 from pin4 of CN21 to pin15 of U54 and add R902 PM_DPRSLPVR O +3V TOP/IN3/BOT 8 mils/ 5 mils
on this net. ACIN_3VA I +3V IN1/IN2 8 mils/ 4.5 mils
POWER IN: AC_BAT_SYS
Page9, Add R896,R897,R898 on pinA15,C16,A17 of U48F . Add +5VAO PWR +3V 90 OHM WIDTH/SPACE
OUT: +12VO
R903,R904,R905 on pinD21,B20,B19 of U48F for option. EN_+3VALWAYS O +3V TOP/IN3/BOT 5 mils/ 8 mils +3VO
Page14, Add net LVDS_DDC2BC,LVDS_DDC2BD on pinAE13,AE14 of AC_BAT_SYS PWR DC IN1/IN2 5 mils/ 6 mils +5VO

U9A. A/D_DOCK_IN PWR DC 100 OHM WIDTH/SPACE PAGE 43

SMCLK_BAT1 IO +3V TOP/IN3/BOT 4 mils/ 9 mils SIGNAL IN: SUSB#_PWR
Page25, Swap pin5,7 of CN3. SUSC#_PWR
Page26, Add net ACZ_BCLK_MDC through R899 on pinC10 of U62D. SMDATA_BAT1 IO +3V IN1/IN2 4.5 mils/ 7.5 mils
Rename net ACZ_BCLK to ACZ_BCLK_AC. SMCLK_BAT2 IO +3V POWER IN: AC_BAT_SYS
+3VO
Page27, Change net name on pinC27,B27 of U62B from USB_OC_012# SMDATA_BAT2 IO +3V
3

to USB_OC_01#. BAT_LOW# I +5VLCM

PCI INTERFACE OUT: +1.8V
+1.5V
3

+2.5V
+VCC_GMCH_CORE
Change net name on pinB26,C26 of U62B from USB_OC_3# to 1.5V_PWRGD I +3V PCI_REQ# +5VALWAYS
+3VALWAYS
USB_OC_23#. 1.8V_PWRGD I +3V
LAN PCI_REQ#1 PAGE 44
Change net name on pinC23,D23 of U62B from USB_OC_045# CB&1394 PCI_REQ#2
to USB_OC_45#. SIGNAL IN: SUSB#_PWR
POWER PLANE MINIPCI PCI_REQ#3 OUT: VCC_MCH_VRPWRGD
Change net name on pinC25 of U62B from USB_OC_06# to POWER VOLTAGE CURRENT IMVP_VR_ON
USB_OC_67#. +VCORE 0.7 - 1.77V 27A
IDSEL POWER IN: +3VA
Change net name on pinC24 of U62B from USB_OC_07# to +VCCP 1.05 - 1.2V 3.32A +3V
+1.8V
USB_OC_67#. Remove R774. +VCC_GMCH 1.05V 3.9A LAN PCI_AD16 +VCC_GMCH_CORE
Page29, Add R895(Un-mount),R894. +0.9VS 1.25V 2.28A CB&1394 PCI_AD17 OUT: +0.9VS
Page30, Rename net ACZ_BCLK to ACZ_BCLK_AC. +1.5VS 1.5V 4.69A MINIPCI PCI_AD19 +1.5VA
+VCCP
Add R891 on pin47 of U32.(Un-mount). +1.5VA 1.5V 270 mA
4
Add R889 from pin2 of U32 pull down to ground. +1.8V 1.8V 7.89A
4

Add R901. +1.8VS 1.8V 3.2A

Page32, Add R901,R902 to connect digital and analog ground. +2.5VS 2.5V 200 mA
Page37, Remove C348,C345. +3VS 3.3V 2.69A
Change CN13 from CARD_BUS_68P to BTOB_CON_68P. +3V 3.3V 2.17A
Add R900 on pin15 of CN31 to pull down to ground. +3VA 3.3V 435 mA
Add D63,U70. Remove C345. Add net SD_CD,MS_CD. +5VS 5V 5.37A
Change inter-sheet port MDIO00/SDCD from pin23 to pin21 of +5V 5V 4.3A
CN31. +12V 12V 50 mA
Page39, Rename net ACZ_BCLK to ACZ_BCLK_MDC. +12VS 12V 10 mA
Page43, Add U71,U72,R881~6,C840,C841 for over current function. ATI_+VCORE 1.0V - 1.2V 8A
Page45, Replace power plane +VCORE with inter-sheet port DJ_SW# on +1.2VSP 1.2V 1.5 A
pin76 of U12.
5 5
Page46, Change connections of CN10.
Add R887,C842,VCC +5V of LED1. Add inter-sheet port
DJ_LED_EN# on pin2 of LED1.
REVISION DATE: Thursday, August 04, 2005 DESCRIPTION: SCHEMATIC FILE NAME : <Doc> DESIGN ENGINEER :
PROJECT: M9V REVISION HISTORY LIBRARY DATE :
1.1 SHEET 60 OF 61

WWW.AliSaler.ComA B C D E
5 4 3 2 1

D DC D

IN Battery Speaker Speaker

S-Video
Power
Instant Key Button LED*3 Button
RJ45 LAN MDC
RJ11

FAN
CRT LAN ATI M24-C

USB
HDD
USB KEYBOARD
CPU USB
915 PM

USB
ODD
C
1394 C

SO DIMM
Audio Touchpad
Jack
ICH6-M
4 IN 1 Left Right
Audio DJ Card Reader Button Button
PCMCIA Audio DJ Button LED*5

Page47, Change Rename net DJ_LED_EN to DJ_LED_EN# and change inter-sheet port Page44, Add C852,C853,C854,C855,C856,C857,R918,U74,X8 for TPM 2.1 function.
from pin2 to pin3 of Q37. Page45, Add R924,R925,Q122, net DJ_SW# to inverse net DJ_SW_EN.
Add inter-sheet port DJ_SW# on pin4 of Q27. Add R888. Page46, Change value of R521,R523,R524,R525,R887 from 300 to 56 Ohm.
Page48, Change value of R317 from 360 to 200 Ohm. Page47, Change CN11 VCC from +3V to +3VALWAYS.
Page49, Un-mount R517. Mount R516. Add D62,inter-sheet port SHUT_DOWN#.
Page50, Change value R805 from 12.7K to 15K Ohm. ER1.1 -> PR2.0 (Obi-Wan)
Change value C807 from 2200P to 3300P. Page6, Un-mount C261. Improve clock quality to meet reduce rise & fall time specification.
Change value R813 from 12.7K to 10.2K Ohm. Add R929,R930 from net CLK_PCIE_PEG,CLK_PCIE_PEG# pull down to ground
B
Change value C787 from 10UF to 100UF. Un-mount C804. for termination. B

Page52, Change value R31 from 47K to 10K Ohm. Page24, Change value of L76,L75,L74 from 120 to 80 Ohm/100MHz and add
Change value R36 from 15K to 100K Ohm. R931,R932,R933,C859~C864(un-mount) to improve signal quality.
Page57, Add JP26. Change Diode D35 form SS0540 to EC31QS04. Page29, Un-mount SW3 for HP request. Un-mount D56 to disable Audio DJ function.
Page32, Add R934 on net S/PDIF to pull down ground.
Page33, Un-mount L82,R259,R258 to disable CMOS camera.
ER1.1 -> PR2.0 Change value of C443 from 1u to 2.2u ; R489 from 300k to 200k ; C441 from 150p
Page5, Add H26,H27. to 18p to improve clock quality to meet specification.
Page7, Change U54 VCC from +3VS to +VCORE. Change CN9 from WTOB_CON_7P to fpc_1x2p.
Add Q118 on net VGA_THERM_DA,VGA_THERM_DC Page38, Change value of R23 from 5.6k to 5.76k Ohm to meet LAN specification.
and Un-mount. Page39, Change CN17 from LAN_12P to MODULAR_JACK_12P.
Page14, Change U47 VCC from +5VS to +3Vs. Add R907,C843,R906,R909. Page40, Un-mount R177,R179 and mount R183,R182 for Wireless LED controlled by EC.
Un-mount R553,R554. Page44, Add CN32 to replace CN15. (HP request)
Page25, Un-mount L58. Mount L57. Page46, Un-mount R887,LED1 to disable Audio DJ function.
Page26, Un-mount R789. Mount R786. Change color of LED3 from orange to blue.(HP request)
Change net name of pinAB21 of U62D from Change CN6 from FPC CON_13P to ZIF_CON_14P and add net PWR_LED# on pin13.
PWRLED_1HZ to GPIO_MUTE_POP. Change value of R523 from 470 to 56Ohm.
Add net LPCPD# through R920 to pinW3 of U62D and Page47, Un-mount Q56,Q35,Q27,R140,R143,R139,Q29,CN11,R888,Q37 to disable Audio DJ
Un-mount R920. function. Add R935 (un-mount) on net SWDJ_EN to prevent current leakage to EC.
A A
Page27, Mount R463,R440,R790. Un-mount R464,R452,R792. Page54, Change C495 from 100P to 1K Ohm.
Page28 Un-mount R848,Q101,R851,Q102,R842. Add R923(un-mount).
Page29, Add net OTP#_P through D67 on pin1 of U66A.
Page31, Change value of C448 from 0 to 1K Ohm.
Page32, Add C844,C845,C846,C847,C848,C849,C850,C851,D64,D65,L95,L96,L97,L98,Q119,
Q120,R910,R911,R912,U73 for SPIDIF function.
Title
Page33, Add R914~R917,Q121 to prevent current leakage. <Title>

Page37, Add R906 on pin6 of CN31 to pull high to +3V. Size Document Number Rev
C <Doc> <RevCode>
Page43, Change value of R263,R131,R881,R884 from 10K to 0 Ohm. Un-mount C236,C840,C103,C841.
Date: Thursday, August 04, 2005 Sheet 61 of 61
5 4 3 2 1