A Central Processing Unit is the most important component of a computer

system. A control unit is a part of the CPU. A control unit controls the operations
of all parts of the computer but it does not carry out any data processing
operations.

Q1) What is a Control Unit?

The Control Unit is the part of the computer’s central processing unit (CPU), which
directs the operation of the processor. It was included as part of the Von Neumann
Architecture by John von Neumann. It is the responsibility of the control unit to tell
the computer’s memory, arithmetic/logic unit, and input and output devices how to
respond to the instructions that have been sent to the processor. It fetches internal
instructions of the programs from the main memory to the processor instruction register,
and based on this register contents, the control unit generates a control signal that
supervises the execution of these instructions. A control unit works by receiving input
information which it converts into control signals, which are then sent to the central
processor. The computer’s processor then tells the attached hardware what operations
to perform. The functions that a control unit performs are dependent on the type of CPU
because the architecture of the CPU varies from manufacturer to manufacturer.

Examples of devices that require a CU are:

• Control Processing Units(CPUs)

• Graphics Processing Units(GPUs)

Functions of the Control Unit

• It coordinates the sequence of data movements into, out of, and between a
processor’s many sub-units.

• It interprets instructions.

• It controls data flow inside the processor.

• It receives external instructions or commands to which it converts to

sequence of control signals.

• It controls many execution units(i.e. ALU, data buffers and registers)

contained within a CPU.

• It also handles multiple tasks, such as fetching, decoding, execution

handling and storing results.

Types of Control Unit

There are two types of control units:

• Hardwired

• Micro programmable control unit.

Q2) Hardwired Control Unit

In the Hardwired control unit, the control signals that are important for instruction
execution control are generated by specially designed hardware logical circuits, in
which we can not modify the signal generation method without physical change of the
circuit structure. The operation code of an instruction contains the basic data for control
signal generation. In the instruction decoder, the operation code is decoded. The
instruction decoder constitutes a set of many decoders that decode different fields of
the instruction opcode.

As a result, few output lines going out from the instruction decoder obtains active signal
values. These output lines are connected to the inputs of the matrix that generates
control signals for execution units of the computer. This matrix implements logical
combinations of the decoded signals from the instruction opcode with the outputs from
the matrix that generates signals representing consecutive control unit states and with
signals coming from the outside of the processor, e.g. interrupt signals. The matrices are
built in a similar way as a programmable logic arrays.
Control signals for an instruction execution have to be generated not in a single time
point but during the entire time interval that corresponds to the instruction execution
cycle. Following the structure of this cycle, the suitable sequence of internal states is
organized in the control unit. A number of signals generated by the control signal
generator matrix are sent back to inputs of the next control state generator matrix.

This matrix combines these signals with the timing signals, which are generated by the
timing unit based on the rectangular patterns usually supplied by the quartz generator.
When a new instruction arrives at the control unit, the control units is in the initial state
of new instruction fetching. Instruction decoding allows the control unit enters the first
state relating execution of the new instruction, which lasts as long as the timing signals
and other input signals as flags and state information of the computer remain unaltered.

A change of any of the earlier mentioned signals stimulates the change of the control
unit state. This causes that a new respective input is generated for the control signal
generator matrix. When an external signal appears, (e.g. an interrupt) the control unit
takes entry into a next control state that is the state concerned with the reaction to this
external signal (e.g. interrupt processing).

The values of flags and state variables of the computer are used to select suitable states
for the instruction execution cycle. The last states in the cycle are control states that
commence fetching the next instruction of the program: sending the program counter
content to the main memory address buffer register and next, reading the instruction
word to the instruction register of computer. When the ongoing instruction is the stop
instruction that ends program execution, the control unit enters an operating system
state, in which it waits for a next user directive.

Q3) Micro Programmable control unit

The fundamental difference between these unit structures and the structure of the
hardwired control unit is the existence of the control store that is used for storing words
containing encoded control signals mandatory for instruction execution.
In microprogrammed control units, subsequent instruction words are fetched into the
instruction register in a normal way. However, the operation code of each instruction is
not directly decoded to enable immediate control signal generation but it comprises the
initial address of a microprogram contained in the control store.

• With a single-level control store: In this, the instruction opcode from

the instruction register is sent to the control store address register. Based
on this address, the first microinstruction of a microprogram that interprets
execution of this instruction is read to the microinstruction register. This
microinstruction contains in its operation part encoded control signals,
normally as few bit fields. In a set microinstruction field decoders, the
fields are decoded. The microinstruction also contains the address of the
next microinstruction of the given instruction microprogram and a control
field used to control activities of the microinstruction address

generator.

The
last mentioned field decides the addressing mode (addressing operation)
to be applied to the address embedded in the ongoing microinstruction. In
microinstructions along with conditional addressing mode, this address is
refined by using the processor condition flags that represent the status of
computations in the current program. The last microinstruction in the
instruction of the given microprogram is the microinstruction that fetches
the next instruction from the main memory to the instruction register.

• With a two-level control store: In this, in a control unit with a two-level

control store, besides the control memory for microinstructions, a nano-
instruction memory is included. In such a control unit, microinstructions
do not contain encoded control signals. The operation part of
microinstructions contains the address of the word in the nano-instruction
memory, which contains encoded control signals. The nano-instruction
memory contains all combinations of control signals that appear in
microprograms that interpret the complete instruction set of a given
computer, written once in the form of nano-instructions. In this way,
unnecessary storing of the same operation parts of microinstructions is
avoided. In this case, microinstruction word can be much shorter than with
the single level control store. It gives a much smaller size in bits of the
microinstruction memory and, as a result, a much smaller size of the entire
control memory. The microinstruction memory contains the control for
selection of consecutive microinstructions, while those control signals are
generated at the basis of nano-instructions. In nano-instructions, control
signals are frequently encoded using 1 bit/ 1 signal method that eliminates
decoding.

Advantages of a Well-Designed Control Unit

• Efficient instruction execution: A well-designed control unit can
execute instructions more efficiently by optimizing the instruction pipeline
and minimizing the number of clock cycles required for each instruction.

• Improved performance: A well-designed control unit can improve the

performance of the CPU by increasing the clock speed, reducing the
latency, and improving the throughput.

• Support for complex instructions: A well-designed control unit can

support complex instructions that require multiple operations, reducing the
number of instructions required to execute a program.

• Improved reliability: A well-designed control unit can improve the

reliability of the CPU by detecting and correcting errors, such as memory
errors and pipeline stalls.

• Lower power consumption: A well-designed control unit can reduce

power consumption by optimizing the use of resources, such as registers
and memory, and reducing the number of clock cycles required for each
instruction.

• Better branch prediction: A well-designed control unit can improve

branch prediction accuracy, reducing the number of branch mispredictions
and improving performance.

• Improved scalability: A well-designed control unit can improve the

scalability of the CPU, allowing it to handle larger and more complex
workloads.

• Better support for parallelism: A well-designed control unit can better

support parallelism, allowing the CPU to execute multiple instructions
simultaneously and improve overall performance.

• Improved security: A well-designed control unit can improve the

security of the CPU by implementing security features such as address
space layout randomization and data execution prevention.

• Lower cost: A well-designed control unit can reduce the cost of the CPU
by minimizing the number of components required and improving
manufacturing efficiency.
Disadvantages of a Poorly-Designed Control Unit

• Reduced performance: A poorly-designed control unit can reduce the

performance of the CPU by introducing pipeline stalls, increasing the
latency, and reducing the throughput.

• Increased complexity: A poorly-designed control unit can increase the

complexity of the CPU, making it harder to design, test, and maintain.

• Higher power consumption: A poorly-designed control unit can

increase power consumption by inefficiently using resources, such as
registers and memory, and requiring more clock cycles for each
instruction.

• Reduced reliability: A poorly-designed control unit can reduce the

reliability of the CPU by introducing errors, such as memory errors and
pipeline stalls.

• Limitations on instruction set: A poorly-designed control unit may limit

the instruction set of the CPU, making it harder to execute complex
instructions and limiting the functionality of the CPU.

• Inefficient use of resources: A poorly-designed control unit may

inefficiently use resources such as registers and memory, leading to
wasted resources and reduced performance.

• Limited scalability: A poorly-designed control unit may limit the

scalability of the CPU, making it harder to handle larger and more complex
workloads.

• Poor support for parallelism: A poorly-designed control unit may limit

the ability of the CPU to support parallelism, reducing the overall
performance of the system.

• Security vulnerabilities: A poorly-designed control unit may introduce

security vulnerabilities, such as buffer overflows or code injection attacks.

• Higher cost: A poorly-designed control unit may increase

the cost of the CPU by requiring additional components or
increasing the manufacturing complexity.
Microprogram for Instructions with Three Phases
Assumptions:

• The target architecture is a simplified model with a control unit (CU), arithmetic

logic unit (ALU), memory data register (MDR), and program counter (PC).

• Instructions have a fixed format (opcode + operands).

• Microinstructions control the flow of data and activation of functional units.

Microprogram Structure:

Each microinstruction will typically have the following fields:

• Control Signals: Activate specific units like the ALU, memory, registers, and data

paths.

• Next State Address (NSA): Determines the next microinstruction to execute based

on the current instruction phase and any branching conditions.

Q3) Microprogram for Sample Instructions:

Instruction Phase Microinstruction Control NSA (Next

Signals State)
1. ADDR1, Fetch Fetch instruction Fetch unit Operand Fetch
R2 1
Operand Fetch Decode opcode, Decoder Execution
1 identify operands
Execution Send R2 value to ALU B ALU Store Result
input, ADDR1 to ALU A Control,
input, perform addition Register
File
Store Result Store ALU output in Register Instruction
register R1 File Fetch
Control
2. ADDR1, Fetch Fetch instruction Fetch unit Operand Fetch
50 2
Operand Fetch Decode opcode, Decoder Execution
2 identify operands
(ADDR1, immediate
value 50)
Execution Send immediate value ALU Store Result
50 to ALU B input, Control,
ADDR1 to ALU A input, Register
perform addition File
Store Result Store ALU output in Register Instruction
register R1 File Fetch
Control
3. ADD R1, Fetch Fetch instruction Fetch unit Operand Fetch
M 3
Operand Fetch Decode opcode, Decoder Memory Read
3 identify operands (R1,
memory location)
Memory Read Read data from Memory Execution
memory location Control
addressed by R1 into
MDR
Execution Send MDR value to ALU Store Result
ALU B input, R1 value Control,
to ALU A input, Register
perform addition File
Store Result Store ALU output in Register Instruction
register R1 File Fetch
Control
4. SUB(R3), Fetch Fetch instruction Fetch unit Operand Fetch
R4 4
Operand Fetch Decode opcode, Decoder Execution
4 identify operands (R3,
R4)
Execution Send R4 value to ALU B ALU Store Result
input (inverted), R3 Control,
value to ALU A input, Register
perform subtraction File
Store Result Store ALU output in Register Instruction
register R3 (overwrite File Fetch
original R3 value) Control
5. JN LA: Fetch Fetch instruction Fetch unit Operand Fetch
(Jump if 5
Negative)
Operand Fetch Decode opcode, Decoder Check Flag
5 identify operand (label
LA)
Check Flag Check ALU Zero flag ALU Branch Not
(set if result is zero) Status Negative
Branch Not Next instruction after PC Instruction
Negative current one Control Fetch
Check Flag Check ALU Zero flag ALU Branch
(set if result is zero) Status Negative
(Jump)
Branch Jump to instruction at PC -
Negative label LA Control
(Jump) (load LA
address)
6. JMP L1: Fetch Fetch instruction Fetch unit Operand Fetch
(Jump) 6
Operand Fetch Decode opcode, Decoder Jump
6 identify operand (label (Unconditional)
L1)
Jump Jump to instruction at PC -
(Unconditional) label L1 Control
(load L1
address)
Explanation:

• Each instruction is broken down into the three phases: Fetch, Operand Fetch, and

Execution.

• Microinstructions within each phase activate the appropriate control signals and

determine the next state address (NSA) based on the current phase and any

necessary branching (e.g., JN for jump if negative).

• The microprogram provides a detailed roadmap for the control unit to execute the

instructions.

Q4) Difference between Horizontal and Vertical micro-programmed Control Unit

The control unit (CU) is the engine that runs the entire functions of a computer with the
help of control signals in the proper sequence. In the micro-programmed control unit
approach, the control signals that are associated with the operations are stored in
special memory units. It is convenient to think of sets of control signals that cause
specific micro-operations to occur as being “micro-instructions”. The sequences of
micro-instructions could be stored in an internal “control” memory.

The micro-programmed control unit can be classified into two types based on the type
of Control Word stored in the Control Memory, viz., Horizontal micro-programmed
control unit and Vertical micro-programmed control unit.

• In the Horizontal micro-programmed control unit, the control signals are

represented in the decoded binary format, i.e., 1 bit/CS. Here ‘n’ control
signals require n bit encoding. On the other hand.
• In a Vertical micro-programmed control unit, the control signals are
represented in the encoded binary format. Here ‘n’ control signals require
log2n bit encoding.
Q5) Hardwired Control Unit Vs Micro - Programmed Control Unit

Hardwired Control Micro-programmed

Unit Control Unit

With the help of a hardware While with the help of

circuit, we can implement programming, we can
the hardwired control unit. implement the micro-
In other words, we can say programmed control unit.
that it is a circuitry
approach.

The hardwired control unit The micro-programmed CU

uses the logic circuit so that uses microinstruction so that
it can generate the control it can generate the control
signals, which are required signals. Usually, control
for the processor. memory is used to store
these microinstructions.

In this CU, the control It is very easy to modify the

signals are going to be micro-programmed control
generated in the form of unit because the
hard wired. That's why it is modifications are going to be
very difficult to modify the performed only at the
hardwired control unit. instruction level.

In the form of logic gates, The micro-programmed

everything has to be control unit is less costly as
realized in the hardwired compared to the hardwired
control unit. That's why CU because this control unit
this CU is more costly as only requires the
compared to the micro- microinstruction to generate
programmed control unit. the control signals.
The complex instructions The micro-programmed
cannot be handled by a control unit is able to handle
hardwired control unit the complex instructions.
because when we design a
circuit for this instruction,
it will become complex.

Because of the hardware The micro-programmed

implementation, the control unit is able to
hardwired control unit is generate control signals for
able to use a limited many instructions.
number of instructions.

The hardwired control unit The micro-programmed

is used in those types of control unit is used in those
computers that also use the types of computers that also
RISC (Reduced instruction use the CISC (Complex
Set Computers). instruction Set Computers).

Q6) Difference between Horizontal and Vertical micro-programmed Control

Unit:

S. Horizontal µ-programmed Vertical µ-programmed CU

No CU
1. It supports longer control It supports shorter control word.
word.
2. It allows a higher degree of It allows a low degree of
parallelism. If degree is n, parallelism i.e., the degree of
then n Control Signals are parallelism is either 0 or 1.
enabled at a time.
3. No additional hardware is Additional hardware in the form of
required. decoders is required to generate
control signals.

4. It is faster than a Vertical it is slower than a Horizontal micro-

micro-programmed control programmed control unit.
unit.
5. It is more flexible than a It is less flexible than horizontal but
vertical micro-programmed more flexible than that of a
control unit. hardwired control unit.

6. A horizontal micro- A vertical micro-programmed

programmed control unit control unit uses vertical micro-
uses horizontal micro- instruction, where a code is used
instruction, where every bit for each action to be performed
in the control field attaches and the decoder translates this
to a control line. code into individual control signals.
7. The horizontal micro- The vertical micro-programmed
programmed control unit control unit makes more use of
makes less use of ROM ROM encoding to reduce the
encoding than the vertical length of the control word.
micro-programmed control
unit.

Q7) Vertical And horizontal Microprogrammed Unit

Example: Consider a hypothetical Control Unit that supports 4 k words. The Hardware
contains 64 control signals and 16 Flags. What is the size of control word used in bits
and control memory in a byte using:
a) Horizontal Programming
b) Vertical programming

Solution:
a)For Horizontal

64 bits for 64 signals % 16 bits for flags

Control Word Size = 64 + 16 = 80 bits
Control Memory = 4 kW = ( (4* 80) / 8 ) = 40 kByte

b)For Vertical
6 bits for 64 signals i.e log264
4 bits for 16 flags i.e log216
12 bits for 4K words i.e log2(4*1024)
Control Word Size = 4 + 6 + 12 = 22 bits

Control Memory = 4 kW = ( (4* 22) / 8 ) = 11 kByte

Designing methods of hardwired control unit

Here the control signals are generated using hardware.

There are three types of Hardwired Control Units.
1. State table method :
State table method

• Here the behavior of control unit is represented in the form of a table,

which is known as the state table.
• Here, each row represents the T-states and the columns represent the
instructions.
• Every intersection of the specific column to each row indicates which
control signal will be produced in the corresponding T- state of an
instruction.
• Here the hardware circuitry is designed for each column(i.e. for a specific
instruction) for producing control signals in different T-states.

Advantage –

• It is the simplest method.

• This method is mainly used for small instruction set processors(i.e. in RISC
processors).

Drawback –

• In modern processors ,there is a very large number of instruction set.

Therefore, the circuit becomes complicated to design, difficult to debug,
and if we make any modifications to the state table then the large parts of
the circuit need to be changed.
• Therefore ,this is not widely used for these kinds of processors.
• There are many redundancies in circuit design like the control signals are
required for fetching the instruction is common and which is repeated for
N number of instruction. So the cost of circuitry design may increase.

2. Delay element method :

• Here the control unit behavior is represented in the form of a flowchart.
• Each step in the flowchart represents a control signal that needs to be
produced for processing the instructions.
• If all the steps of the instructions are performed, this means the instruction
is executed completely.
• Control signals perform micro-operations and each micro-operation requires one
T-state.
• For the micro-operations which are independent, they are required to be
performed in different T-state. Therefore, for every consecutive control
signal an exactly 1-state delay is required, which can be produced with the
help of D FF.
• Therefore. D Flip-Flops are inserted between every two consecutive
control signals.

• As we can observe, the D FF is introduced between each pair of control

signals .Therefore, after a control signal is generated, then the delay
element before that control signal is not in use until before the next
instruction required that control signal. Therefore, of all D Flip-Flops, only
one will be active at a time. Therefore, this method is also known as one hot
method.
• In a flowchart, if there is a multiple entry point for control signal then to
combine two or more paths, we use an OR gate.
• A decision box is converted into a set of two complementing AND gates.

Example –
Suppose the processor has two instructions add or subtract (Therefore an opcode of 1
bit is needed in which 0 opcode for add instruction and 1 for subtract is used.

Delay element method for generating control signals.

Flowchart design –
Say C1,C2,C3 is the control signals for fetching the instruction. When X= 0, then
C4 control signal is produced (i.e. decoding) which is used for performing add
operation, and when x=1, then control signal C5 will be produced for performing the
subtract operation. And c6 control signal is used for storing the result and the process
ends.

Circuit design –
Between two consecutive control signals which are independent, one delay element is
introduced between them to produce a delay of 1 T state. The decision box is
converted into and complemented AND gate circuit(i.e. if x= 0 then x’= 1, so, a
c4 control signal is generated.

Advantage –

• This method has a logical approach ,therefore it helps to reduce the circuit
complexity.
• For the common control signals which need to be generated in every
instruction, for them only one circuitry can be designed .

Drawback –

• As the number of instructions increases , the number of D FF for

generating delay is increased, so overall circuit complexity and cost
increases.

3. Sequence counter method :

Sequence Counter method

• This is the most popular and most commonly used method for generating
delays between every consecutive control signal.
It’s main advantage is that it uses the logical approach of flowchart and
doesn’t use the unnecessary number of D FF.
• First, a flowchart is designed to represent the behavior of a control unit.
• It is then converted into a circuit using the same method of AND & OR
gates (as seen above in the Delay element method).
Example of 2 instructions used in the delay element method

• It is similar to the delay element method, but the only difference is that
instead of unnecessary D Flip flops there are triggering points in the
circuit. They are activated after a gap of one-one T-state.

Working of Sequence counter circuit –

• Here one SR FF , one decode and one counter is used.

Truth table of SR FF

• When the instruction cycle starts, then start = 1.

• As we know, when Start = 1, because S is connected to Start, therefore
Q becomes 1 and and Q’ becomes 0.
• Here the level triggering clock is used. Therefore, when clock = 1 or high
and Start=1, as both outputs are connected to AND gate, so if the resultant
of both is 1 that will enable the counter and counter starts counting from 0
0 0 state. So the 0 0 0 state is decoded by a decoder and produces output
O1 , which will trigger the triggering point in the control circuit.
• As the clock becomes high again after 1 T-state. Therefore, when clock = 0,
then the counter state is preserved(Q and Q’) remains the same until the
clock becomes high again. This makes sure that the counter changes its
states after a gap of one-one T state.
• Suppose the counter is 3 bits, it generates 23 = 8 states(000 001 ….. 111) . The
first count 0 0 0 is given to 3:8 decoder. It will active output number 1. This
output is not a control signal but this will trigger the triggering point in the
control unit circuit.
• As the clock becomes high again after a gap of one T state, therefore clock
=1 and start = 1 ,then the counter is enabled and changes it state to 001
and the counter decodes the count and makes O2 output high . And this
will trigger a second triggering point in the circuit.
• All counting states are decoded in the same manner.
If the counter is of K bits then K:2K decoder is required this can produce 2K outputs
and that will trigger the 2K triggering points after a gap of 1-1 T-states in the circuit.

• When the instruction ends, the control signal is generated to make End pin
= 1, and the counter is reset, so the next time, it begins from the first
count(0 0 0 ).
• If reset pin =1, then the counter will reset and after that it will again start
counting from 000 states.

Advantages :

• Less number of flip-flops are used.

Disadvantages of hardwired control unit :

• In modern processors ,there is a very large number of instruction set.

Therefore, the circuit becomes complicated to design, difficult to debug,
and if we make any modifications then a large part of the circuit needs to
be changed. Therefore, it is suited for RISC processors.